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61. 发明授权

US07422961B2 Method of forming isolation regions for integrated circuits 有权
标题翻译：形成集成电路隔离区的方法
公开(公告)号：US07422961B2
公开(公告)日：2008-09-09
申请号：US10389456
申请日：2003-03-14
申请人： Haihong Wang , Minh-Van Ngo , Qi Xiang , Paul R. Besser , Eric N. Paton , Ming-Ren Lin
发明人： Haihong Wang , Minh-Van Ngo , Qi Xiang , Paul R. Besser , Eric N. Paton , Ming-Ren Lin
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L21/823481 , H01L29/1054
摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a CVD process.
摘要翻译：集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。浅沟槽隔离技术用于应变硅（SMOS）工艺。用于沟槽的衬垫由半导体或金属层形成，该半导体或金属层在低温过程中沉积，这降低了锗除气。低温工艺可以是CVD工艺。

62. 发明授权

US07402207B1 Method and apparatus for controlling the thickness of a selective epitaxial growth layer 有权
标题翻译：用于控制选择性外延生长层厚度的方法和装置
公开(公告)号：US07402207B1
公开(公告)日：2008-07-22
申请号：US10839378
申请日：2004-05-05
申请人： Paul R. Besser , Eric N. Paton , William G. En
发明人： Paul R. Besser , Eric N. Paton , William G. En
IPC分类号： C30B21/04
CPC分类号： C30B25/16 , G01B11/0616 , H01L21/67167 , H01L21/67207 , H01L21/67745 , Y10T117/1004 , Y10T117/1008
摘要： Methods and systems for permitting thickness control of the selective epitaxial growth (SEG) layer in a semiconductor manufacturing process, for example raised source/drain applications in CMOS technologies, are presented. These methods and systems provide the capability to measure the thickness of an SEG film in-situ utilizing optical ellipsometry equipment during or after SEG layer growth, prior to removing the wafer from the SEG growth tool. Optical ellipsometry equipment can be integrated into the SEG platform and control software, thus providing automated process control (APC) capability for SEG thickness. The integration of the ellipsometry equipment may be varied, dependent upon the needs of the fabrication facility, e.g., integration to provide ellipsometer monitoring of a single process tool, or multiple tool monitoring, among other configurations.
摘要翻译：提出了在半导体制造工艺中允许厚度控制选择性外延生长（SEG）层的方法和系统，例如CMOS技术中的升高的源/漏应用。这些方法和系统提供了在从SEG生长工具移除晶片之前在SEG层生长期间或之后使用光学椭偏仪设备原位测量SEG膜的厚度的能力。光学椭圆测量设备可以集成到SEG平台和控制软件中，从而为SEG厚度提供自动化过程控制（APC）能力。椭圆测量设备的集成可以根据制造设施的需要而变化，例如集成以提供单个处理工具的椭偏仪监控，或者多个工具监视以及其他配置。

63. 发明申请

US20080149990A1 MEMORY SYSTEM WITH POLY METAL GATE 审中-公开
标题翻译：具有多金属门的记忆系统
公开(公告)号：US20080149990A1
公开(公告)日：2008-06-26
申请号：US11735241
申请日：2007-04-13
申请人： Connie Pin Chin Wang , Paul R. Besser , Simon Siu-Sing Chan , YouSeok Suh , Shenqing Fang
发明人： Connie Pin Chin Wang , Paul R. Besser , Simon Siu-Sing Chan , YouSeok Suh , Shenqing Fang
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/40114
摘要： A memory system includes a substrate, forming an insulator over the substrate, forming a gate layer over the insulator, forming a stability layer over the gate layer, and forming a conductive layer over the stability layer.
摘要翻译：存储器系统包括：衬底，在衬底上形成绝缘体，在绝缘体上形成栅极层，在栅极层上形成稳定层，并在稳定层上形成导电层。

64. 发明授权

US07312125B1 Fully depleted strained semiconductor on insulator transistor and method of making the same 有权
标题翻译：绝缘子晶体管的全耗尽应变半导体及其制造方法
公开(公告)号：US07312125B1
公开(公告)日：2007-12-25
申请号：US10773026
申请日：2004-02-05
申请人： Qi Xiang , Paul R. Besser , Minh Van Ngo , Eric N. Paton , Haihong Wang
发明人： Qi Xiang , Paul R. Besser , Minh Van Ngo , Eric N. Paton , Haihong Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L27/1203 , H01L29/66553 , H01L29/66621 , H01L29/7848 , H01L29/78621 , H01L29/78684 , Y10S438/938
摘要： An integrated circuit includes multiple layers. A semiconductor-on-insulator (SOI) wafer can be used to house transistors. Two substrates or wafers can be bonded to form the multiple layers. A strained semiconductor layer can be between a silicon germanium layer and a buried oxide layer. A hydrogen implant can provide a breaking interface to remove a silicon substrate from the silicon germanium layer.
摘要翻译：集成电路包括多层。可以使用绝缘体上半导体（SOI）晶片来容纳晶体管。可以结合两个基板或晶片以形成多个层。应变半导体层可以在硅锗层和掩埋氧化物层之间。氢注入可以提供断开界面以从硅锗层去除硅衬底。

65. 发明授权

US07132352B1 Method of eliminating source/drain junction spiking, and device produced thereby 有权
标题翻译：消除源极/漏极结尖峰的方法，以及由此产生的器件
公开(公告)号：US07132352B1
公开(公告)日：2006-11-07
申请号：US10913184
申请日：2004-08-06
申请人： Simon Siu-Sing Chan , Paul R. Besser , Jeffrey P. Patton
发明人： Simon Siu-Sing Chan , Paul R. Besser , Jeffrey P. Patton
IPC分类号： H01L21/28
CPC分类号： H01L21/324 , H01L21/26506 , H01L21/28518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A metallic layer is formed on the semiconductor substrate, and the metallic layer is reacted with the semiconductor substrate to form an early phase of silicide. Implanted shallow source/drain junctions are formed immediately beneath the silicide. A final phase of the silicide is formed. An interlayer dielectric is deposited above the semiconductor substrate, and contacts are then formed to the silicide.
摘要翻译：提供一种形成具有半导体衬底的集成电路的方法。在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。在半导体衬底上形成金属层，金属层与半导体衬底反应形成硅化物的早期阶段。在硅化物的正下方形成植入的浅源极/漏极结。形成硅化物的最终相。在半导体衬底上沉积层间电介质，然后与硅化物形成接触。

66. 发明授权

US07005357B2 Low stress sidewall spacer in integrated circuit technology 有权
标题翻译：集成电路技术中的低应力侧壁间隔
公开(公告)号：US07005357B2
公开(公告)日：2006-02-28
申请号：US10756023
申请日：2004-01-12
申请人： Minh Van Ngo , Simon Siu-Sing Chan , Paul R. Besser , Paul L. King , Errol Todd Ryan , Robert J. Chiu
发明人： Minh Van Ngo , Simon Siu-Sing Chan , Paul R. Besser , Paul L. King , Errol Todd Ryan , Robert J. Chiu
IPC分类号： H01L21/336 , H01L21/441
CPC分类号： H01L29/6659 , H01L29/665
摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A sidewall spacer is formed around the gate using a low power plasma enhanced chemical vapor deposition process A silicide is formed on the source/drain junctions and on the gate, and an interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.
摘要翻译：提供一种形成具有半导体衬底的集成电路的方法。在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。在半导体衬底中形成源极/漏极结。使用低功率等离子体增强化学气相沉积工艺在栅极周围形成侧壁间隔物。在源极/漏极结和栅极上形成硅化物，并且在半导体衬底上沉积层间电介质。然后在层间电介质中形成与硅化物的接触。

67. 发明授权

US06951220B1 Method of decontaminating equipment 有权
标题翻译：去污设备的方法
公开(公告)号：US06951220B1
公开(公告)日：2005-10-04
申请号：US10288157
申请日：2002-11-05
申请人： Farzad Arasnia , Paul R. Besser , Minh V. Ngo , Qi Xiang
发明人： Farzad Arasnia , Paul R. Besser , Minh V. Ngo , Qi Xiang
IPC分类号： B08B7/00 , B08B9/00 , C23C16/44
CPC分类号： B08B7/00 , C23C16/4405 , Y10S134/902 , Y10S438/905
摘要： A method of performing decontamination of a chamber for use in an IC fabrication system includes providing wet oxygen or a mixture comprising hydrochloric gas and oxygen in the chamber and raising the temperature in the chamber from a first lower temperature to a second higher temperature to cause the wet oxygen or the mixture comprising hydrochloric gas and oxygen to react with the germanium.
摘要翻译：对用于IC制造系统的室进行净化的方法包括在室中提供湿氧气或包含盐酸气体和氧气的混合物，并将室中的温度从第一较低温度升至第二较高温度，以使湿氧气或包含氯化氢气体和氧气的混合物与锗反应。

68. 发明授权

US06943569B1 Method, system and apparatus to detect defects in semiconductor devices 有权
标题翻译：检测半导体器件缺陷的方法，系统和装置
公开(公告)号：US06943569B1
公开(公告)日：2005-09-13
申请号：US10121252
申请日：2002-04-12
申请人： Laura Pressley , David E. Brown , Travis Lewis , Edward E. Ehrichs , Paul R. Besser
发明人： Laura Pressley , David E. Brown , Travis Lewis , Edward E. Ehrichs , Paul R. Besser
IPC分类号： G01R27/08 , G01R31/302 , G01R31/305
CPC分类号： G01R31/307 , G06T7/0006 , G06T2207/10056 , G06T2207/20068 , G06T2207/30148 , H01J2237/2817 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： A method and system to locate and detect voids in films that are involved in critical dimension (CD) structures and non-critical dimension structures in semiconductor devices are presented. One or more test structures (resolution devices) are formed on a semiconductor wafer. A scanning electron microscope is operated in voltage contrast mode to obtain a digital representation of the test structure. The voltage contrast image of the test structure is then analyzed with a system which automates the location, identification, and categorization of voids in the test structure. Additionally, the method is more sensitive to electrical marginalities caused by voids than other wafer electrical testing methods. The method is suitable inline monitoring during a manufacturing process by utilizing the automation of void identification, location, and categorization as a process monitoring parameter.
摘要翻译：提出了一种在半导体器件中涉及关键尺寸（CD）结构和非关键尺寸结构的薄膜中定位和检测空隙的方法和系统。在半导体晶片上形成一个或多个测试结构（分辨率器件）。扫描电子显微镜以电压对比模式工作，以获得测试结构的数字表示。然后用自动化测试结构中空隙的位置，识别和分类的系统分析测试结构的电压对比图像。此外，该方法比其他晶片电气测试方法对由空隙引起的电气边界更敏感。该方法通过利用空白识别，位置和分类的自动化作为过程监控参数，在制造过程中适合于在线监测。

69. 发明授权

US06861350B1 Method of manufacturing semiconductor device comprising silicon-rich tasin metal gate electrode 有权
标题翻译：一种制造半导体器件的方法，所述半导体器件包括富含硅的金属栅电极
公开(公告)号：US06861350B1
公开(公告)日：2005-03-01
申请号：US10464508
申请日：2003-06-19
申请人： Minh Van Ngo , Christy Mei-Chu Woo , Jinsong Yin , James Pan , Paul R. Besser
发明人： Minh Van Ngo , Christy Mei-Chu Woo , Jinsong Yin , James Pan , Paul R. Besser
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H10L21/4763 , H10L21/44
CPC分类号： H01L29/66606 , H01L21/28088 , H01L29/4966 , H01L29/66545
摘要： Micro-miniaturized semiconductor devices are fabricated with silicon-rich tantalum silicon nitride replacement metal gate electrodes. Embodiments include removing a removable gate, depositing a layer of tantalum nitride, as by PVD at a thickness of 25 Å to 75 Å, and then introducing silicon into the deposited tantalum nitride layer by thermal soaking in silane or silane plasma treatment to form a layer of silicon-rich tantalum silicon nitride. In another embodiment, the intermediate structure is subjected to thermal soaking in silane or silane plasma treatment before and after depositing the tantalum nitride layer. Embodiments further include pretreating the intermediate structure with silane prior to depositing the tantalum nitride layer, treating the deposited tantalum nitride layer with silane, and repeating these steps a number of times to form a plurality of sub-layers of silicon-rich tantalum silicon nitride.
摘要翻译：微型半导体器件由富含硅的钽氮化硅替代金属栅电极制成。实施例包括去除可移除栅极，通过PVD沉积氮化钽层，厚度为25埃，然后通过在硅烷或硅烷等离子体处理中热浸泡形成层，将硅引入沉积的氮化钽层中的富硅钽硅氮化物。在另一个实施方案中，在沉积氮化钽层之前和之后，使中间体在硅烷或硅烷等离子体处理中进行热浸。实施例还包括在沉积氮化钽层之前用硅烷预处理中间结构，用硅烷处理沉积的氮化钽层，并重复这些步骤多次以形成多个富硅钽硅氮化物的子层。

70. 发明授权

US06858503B1 Depletion to avoid cross contamination 失效
标题翻译：消耗以避免交叉污染
公开(公告)号：US06858503B1
公开(公告)日：2005-02-22
申请号：US10358484
申请日：2003-02-05
申请人： Minh V. Ngo , Ming-Ren Lin , Paul R. Besser , Qi Xiang , Eric N. Paton , Jung-Suk Goo
发明人： Minh V. Ngo , Ming-Ren Lin , Paul R. Besser , Qi Xiang , Eric N. Paton , Jung-Suk Goo
IPC分类号： H01L21/306 , H01L29/10 , H01L21/336
CPC分类号： H01L21/02046 , H01L29/1054
摘要： A fabrication system utilizes a protocol for removing germanium from a top surface of a wafer. An exposure to a gas, such as a gas containing the hydrochloric acid can remove germanium from the top surface. The protocol can allow shared equipment to be used in both Flash product fabrication lines and strained silicon (SMOS) fabrication lines. The protocol allows better silicidation in SMOS devices.
摘要翻译：制造系统利用从晶片顶表面去除锗的方案。暴露于气体，如含有盐酸的气体，可以从上表面除去锗。该协议可以允许在Flash产品制造线和应变硅（SMOS）生产线中使用共享设备。该协议允许在SMOS器件中更好的硅化。

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