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1. 发明授权

US07005357B2 Low stress sidewall spacer in integrated circuit technology 有权
标题翻译：集成电路技术中的低应力侧壁间隔
公开(公告)号：US07005357B2
公开(公告)日：2006-02-28
申请号：US10756023
申请日：2004-01-12
申请人： Minh Van Ngo , Simon Siu-Sing Chan , Paul R. Besser , Paul L. King , Errol Todd Ryan , Robert J. Chiu
发明人： Minh Van Ngo , Simon Siu-Sing Chan , Paul R. Besser , Paul L. King , Errol Todd Ryan , Robert J. Chiu
IPC分类号： H01L21/336 , H01L21/441
CPC分类号： H01L29/6659 , H01L29/665
摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A sidewall spacer is formed around the gate using a low power plasma enhanced chemical vapor deposition process A silicide is formed on the source/drain junctions and on the gate, and an interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.
摘要翻译：提供一种形成具有半导体衬底的集成电路的方法。在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。在半导体衬底中形成源极/漏极结。使用低功率等离子体增强化学气相沉积工艺在栅极周围形成侧壁间隔物。在源极/漏极结和栅极上形成硅化物，并且在半导体衬底上沉积层间电介质。然后在层间电介质中形成与硅化物的接触。

2. 发明授权

US07151020B1 Conversion of transition metal to silicide through back end processing in integrated circuit technology 有权
标题翻译：在集成电路技术中通过后端处理将过渡金属转化为硅化物
公开(公告)号：US07151020B1
公开(公告)日：2006-12-19
申请号：US10839437
申请日：2004-05-04
申请人： Jeffrey P. Patton , Austin C. Frenkel , Thorsten Kammler , Robert J. Chiu , Errol Todd Ryan , Darin A. Chan , Paul R. Besser , Paul L. King , Minh Van Ngo
发明人： Jeffrey P. Patton , Austin C. Frenkel , Thorsten Kammler , Robert J. Chiu , Errol Todd Ryan , Darin A. Chan , Paul R. Besser , Paul L. King , Minh Van Ngo
IPC分类号： H01L21/336 , H01L21/44
CPC分类号： H01L21/28518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A transition metal layer is formed on the source/drain junctions and on the gate. An interlayer dielectric is formed above the semiconductor substrate. Contacts are then formed in the interlayer dielectric, whereby a silicide is formed from the transition metal layer at a temperature no higher than the maximum temperature at which the interlayer dielectric and the contacts are formed.
摘要翻译：提供一种形成具有半导体衬底的集成电路的方法。在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。在半导体衬底中形成源极/漏极结。在源极/漏极结和栅极上形成过渡金属层。在半导体衬底上形成层间电介质。然后在层间电介质中形成触点，由此在不高于形成层间电介质和触点的最高温度的温度下由过渡金属层形成硅化物。

3. 发明授权

US07064067B1 Reduction of lateral silicide growth in integrated circuit technology 有权
标题翻译：降低集成电路技术中的侧硅化物生长
公开(公告)号：US07064067B1
公开(公告)日：2006-06-20
申请号：US10770905
申请日：2004-02-02
申请人： Paul L. King , Simon Siu-Sing Chan , Jeffrey P. Patton , Minh Van Ngo
发明人： Paul L. King , Simon Siu-Sing Chan , Jeffrey P. Patton , Minh Van Ngo
IPC分类号： H01L21/336 , H01L21/44
CPC分类号： H01L29/665 , H01L21/28518 , H01L29/6659 , H01L29/7833
摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A sidewall spacer is formed around the gate. Source/drain junctions are formed in the semiconductor substrate. An intermediate phase silicide is formed on the source/drain regions and on the gate. The sidewall spacer is removed. A final phase silicide is formed from the intermediate phase silicide. An interlayer dielectric is deposited above the semiconductor substrate, and contacts are then formed in the interlayer dielectric to the final phase silicide.
摘要翻译：提供一种形成具有半导体衬底的集成电路的方法。在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。在栅极周围形成侧壁间隔物。在半导体衬底中形成源极/漏极结。在源极/漏极区域和栅极上形成中间相硅化物。去除侧壁间隔物。由中间相硅化物形成最终相硅化物。在半导体衬底上沉积层间电介质，然后在层间电介质中形成接触到最终相硅化物。

4. 发明授权

US06605513B2 Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing 有权
标题翻译：使用一步快速热退火工艺和后端加工形成硅化镍的方法
公开(公告)号：US06605513B2
公开(公告)日：2003-08-12
申请号：US09729699
申请日：2000-12-06
申请人： Eric N. Paton , Ercan Adem , Jacques J. Bertrand , Paul R. Besser , Matthew S. Buynoski , John Clayton Foster , Paul L. King , George Jonathan Kluth , Minh Van Ngo , Christy Mei-Chu Woo
发明人： Eric N. Paton , Ercan Adem , Jacques J. Bertrand , Paul R. Besser , Matthew S. Buynoski , John Clayton Foster , Paul L. King , George Jonathan Kluth , Minh Van Ngo , Christy Mei-Chu Woo
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L21/28061 , H01L21/28518 , H01L29/4933
摘要： A self-aligned silicide process that can accommodate a low thermal budget and form silicide regions of small dimensions in a controlled reaction. In a first temperature treatment, nickel metal or nickel alloy is reacted with a silicon material to form at least one high resistance nickel silicide region. Unreacted nickel is removed. A dielectric layer is then deposited over a high resistance nickel silicide regions. In a second temperature treatment, the at least one high resistance nickel silicide region and dielectric layer are reacted at a prescribed temperature to form at least one low resistance silicide region and process the dielectric layer. Bridging between regions is avoided by the two-step process as silicide growth is controlled, and unreacted nickel between silicide regions is removed after the first temperature treatment. The processing of the high resistance nickel silicide regions and the dielectric layer are conveniently combined into a single temperature treatment.
摘要翻译：自对准硅化物工艺，可以适应低热预算，并在受控反应中形成小尺寸的硅化物区域。在第一温度处理中，镍金属或镍合金与硅材料反应以形成至少一个高电阻镍硅化物区域。去除未反应的镍。然后将电介质层沉积在高电阻镍硅化物区域上。在第二温度处理中，至少一个高电阻镍硅化物区域和电介质层在规定温度下反应以形成至少一个低电阻硅化物区域并处理介电层。通过控制硅化物生长的两步法避免区域之间的桥接，并且在第一温度处理之后去除硅化物区域之间的未反应的镍。将高电阻镍硅化物区域和电介质层的处理方便地组合成单温度处理。

5. 发明授权

US07250667B2 Selectable open circuit and anti-fuse element 有权
标题翻译：可选开路和反熔丝元件
公开(公告)号：US07250667B2
公开(公告)日：2007-07-31
申请号：US11306663
申请日：2006-01-05
申请人： Darin A. Chan , Simon Siu-Sing Chan , Paul L. King
发明人： Darin A. Chan , Simon Siu-Sing Chan , Paul L. King
IPC分类号： H01L29/00
CPC分类号： H01L27/112 , H01L23/5252 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit is provided with a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that segregates to the top surface of a silicide when the semiconductor substrate is reacted to form such a silicide. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. Source/drain junctions are in the semiconductor substrate. A silicide is on the source/drain junctions and dopant is segregated to the top surface of the silicide. The dopant on the top surface of the segregated dopant is oxidized to form an insulating layer of oxidized dopant above the silicide. An interlayer dielectric is above the semiconductor substrate. Contacts and connection points are in the interlayer dielectric to the insulating layer of oxidized dopant above the silicide.
摘要翻译：集成电路设置有半导体衬底，当半导体衬底反应以形成这种硅化物时，半导体衬底被掺杂为具有与硅化物的顶表面分离的类型的可氧化掺杂剂的设定浓度。栅极电介质位于半导体衬底上，栅极位于栅极电介质上。源极/漏极结在半导体衬底中。硅化物在源极/漏极结上，掺杂剂分离到硅化物的顶表面。分离的掺杂剂的顶表面上的掺杂剂被氧化以在硅化物之上形成氧化掺杂剂的绝缘层。层间电介质在半导体衬底之上。触点和连接点位于硅化物之上的氧化掺杂剂的绝缘层的层间电介质中。

6. 发明授权

US07015076B1 Selectable open circuit and anti-fuse element, and fabrication method therefor 失效
标题翻译：可选开路和反熔丝元件及其制造方法
公开(公告)号：US07015076B1
公开(公告)日：2006-03-21
申请号：US10791098
申请日：2004-03-01
申请人： Darin A. Chan , Simon Siu-Sing Chan , Paul L. King
发明人： Darin A. Chan , Simon Siu-Sing Chan , Paul L. King
IPC分类号： H01L21/82
CPC分类号： H01L27/112 , H01L23/5252 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： A method is provided of forming an integrated circuit with a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that segregates to the top surface of a silicide when the semiconductor substrate is reacted to form such a silicide. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain junctions and dopant is segregated to the top surface of the silicide. The dopant on the top surface of the segregated dopant is oxidized to form an insulating layer of oxidized dopant above the silicide. An interlayer dielectric is deposited above the semiconductor substrate. Contacts and connection points are then formed in the interlayer dielectric to the insulating layer of oxidized dopant above the silicide.
摘要翻译：提供了一种形成集成电路的方法，该半导体衬底在半导体衬底反应形成这种硅化物时，掺杂有一定类型的可氧化掺杂剂的分解与硅化物顶表面的浓度。在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。在半导体衬底中形成源极/漏极结。在源极/漏极结上形成硅化物，掺杂剂分离到硅化物的顶表面。分离的掺杂剂的顶表面上的掺杂剂被氧化以在硅化物之上形成氧化掺杂剂的绝缘层。在半导体衬底上沉积层间电介质。接触点和连接点然后在层间电介质中形成到硅化物之上的氧化掺杂剂的绝缘层。

7. 发明授权

US06784506B2 Silicide process using high K-dielectrics 失效
标题翻译：使用高K电介质的硅化物工艺
公开(公告)号：US06784506B2
公开(公告)日：2004-08-31
申请号：US09939744
申请日：2001-08-28
申请人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John Clayton Foster , Paul L. King , Eric N. Paton
发明人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John Clayton Foster , Paul L. King , Eric N. Paton
IPC分类号： H01L2976
CPC分类号： H01L29/4933 , H01L21/28167 , H01L21/28194 , H01L29/517 , H01L29/518 , H01L29/665
摘要： A method for preventing the thermal decomposition of a high-K dielectric layer of a gate electrode during the formation of a metal silicide on the gate electrode by using nickel as the metal component of the silicide.
摘要翻译：通过使用镍作为硅化物的金属成分，在栅电极形成金属硅化物期间防止栅电极的高K电介质层的热分解的方法。

8. 发明授权

US06610181B1 Method of controlling the formation of metal layers 有权
标题翻译：控制金属层形成的方法
公开(公告)号：US06610181B1
公开(公告)日：2003-08-26
申请号：US09845952
申请日：2001-04-30
申请人： Paul R. Besser , Paul L. King , Susan Kim
发明人： Paul R. Besser , Paul L. King , Susan Kim
IPC分类号： C23C1434
CPC分类号： C23C14/545 , C23C8/00 , C23C16/52 , C23C26/00
摘要： The present invention is directed to a method of controlling the formation of metal layers. In one illustrative embodiment, the method comprises depositing a layer of metal above a structure, irradiating at least one area of the layer of metal, and analyzing an x-ray spectrum of x-rays leaving the irradiated area to determine a thickness of the layer of metal. In further embodiments of the present invention, a plurality of areas, and in some cases at least five areas, of the layer of metal are irradiated. The layer of metal may be comprised of, for example, titanium, cobalt, nickel, copper, tantalum, etc.
摘要翻译：本发明涉及一种控制金属层形成的方法。在一个说明性实施例中，该方法包括在结构上沉积金属层，照射金属层的至少一个区域，并分析离开照射区域的x射线的X射线光谱，以确定层的厚度的金属。在本发明的另外的实施例中，照射金属层的多个区域，并且在一些情况下至少五个区域。金属层可以由例如钛，钴，镍，铜，钽等组成。

9. 发明授权

US06559051B1 Electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors 有权
标题翻译：用于嵌入栅极MOS晶体管的介电材料前体材料的无电沉积
公开(公告)号：US06559051B1
公开(公告)日：2003-05-06
申请号：US09679881
申请日：2000-10-05
申请人： Matthew S. Buynoski , Paul R. Besser , Paul L. King , Eric N. Paton , Qi Xang
发明人： Matthew S. Buynoski , Paul R. Besser , Paul L. King , Eric N. Paton , Qi Xang
IPC分类号： H01L2144
CPC分类号： H01L21/28194 , H01L21/28114 , H01L29/42376 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/517 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/66583
摘要： High quality dielectric layers, e.g., high-k dielectric layers comprised of at least one refractory or lanthanum series transition metal oxide or silicate, for use as gate insulator layers in in-laid metal gate MOS transistors and CMOS devices, are formed by electrolessly plating a metal or metal-based dielectric precursor layer comprising at least one refractory or lanthanum series transition metal, such as of Zr and/or Hf, on a silicon-based semiconductor substrate and then reacting the precursor layer with oxygen or with oxygen and the Si-based semiconductor substrate to form the at least one metal oxide or silicate. The inventive methodology prevents, or at least substantially reduces, oxygen access to the substrate surface during at least the initial stage(s) of formation of the gate insulator layer, thereby minimizing deleterious formation of oxygen-induced surface states at the semiconductor substrate/gate insulator interface.
摘要翻译：通过无电镀法形成高质量电介质层，例如由至少一种耐火材料或镧系列过渡金属氧化物或硅酸盐构成的高k电介质层，用作叠层金属栅极MOS晶体管和CMOS器件中的栅极绝缘体层金属或金属基电介质前体层，其在硅基半导体衬底上包含至少一种难熔或镧系过渡金属，例如Zr和/或Hf，然后使前体层与氧或氧与Si反应的半导体衬底以形成至少一种金属氧化物或硅酸盐。本发明的方法在至少形成栅极绝缘体层的初始阶段期间防止或至少基本上减少氧接触到衬底表面，从而最小化半导体衬底/栅极处的氧诱导表面状态的有害形成绝缘子接口。

10. 发明授权

US06380057B1 Enhancement of nickel silicide formation by use of nickel pre-amorphizing implant 有权
标题翻译：通过使用镍前非晶化植入物来增强硅化镍的形成
公开(公告)号：US06380057B1
公开(公告)日：2002-04-30
申请号：US09781225
申请日：2001-02-13
申请人： Matthew S. Buynoski , George Jonathan Kluth , Paul R. Besser , Paul L. King
发明人： Matthew S. Buynoski , George Jonathan Kluth , Paul R. Besser , Paul L. King
IPC分类号： H01L213205
CPC分类号： H01L29/665 , H01L21/26506 , H01L21/28044 , H01L21/28052 , H01L21/28518
摘要： Nickel salicide processing is implemented by implanting nickel into the active regions, prior to depositing Ni, to catalyze the reaction of Ni and Si during annealing to form a NiSi layer on the polysilicon gate electrodes and source/drain regions without the formation of rough interfaces between the nickel silicide layers and underlying silicon and without conductive bridging between the metal silicide layer on the gate electrode and the metal silicide layers on associated source/drain regions, particularly in the presence of silicon nitride sidewall spacers.
摘要翻译：镍自杀化处理通过在沉积Ni之前将镍注入活性区域来实现，以在退火期间催化Ni和Si的反应，以在多晶硅栅极电极和源极/漏极区域上形成NiSi层，而不形成在硅化镍层和底层硅，并且在栅电极上的金属硅化物层与相关源极/漏极区域上的金属硅化物层之间没有导电桥接，特别是在存在氮化硅侧壁间隔物的情况下。

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