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1. 发明授权

US06861350B1 Method of manufacturing semiconductor device comprising silicon-rich tasin metal gate electrode 有权
标题翻译：一种制造半导体器件的方法，所述半导体器件包括富含硅的金属栅电极
公开(公告)号：US06861350B1
公开(公告)日：2005-03-01
申请号：US10464508
申请日：2003-06-19
申请人： Minh Van Ngo , Christy Mei-Chu Woo , Jinsong Yin , James Pan , Paul R. Besser
发明人： Minh Van Ngo , Christy Mei-Chu Woo , Jinsong Yin , James Pan , Paul R. Besser
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H10L21/4763 , H10L21/44
CPC分类号： H01L29/66606 , H01L21/28088 , H01L29/4966 , H01L29/66545
摘要： Micro-miniaturized semiconductor devices are fabricated with silicon-rich tantalum silicon nitride replacement metal gate electrodes. Embodiments include removing a removable gate, depositing a layer of tantalum nitride, as by PVD at a thickness of 25 Å to 75 Å, and then introducing silicon into the deposited tantalum nitride layer by thermal soaking in silane or silane plasma treatment to form a layer of silicon-rich tantalum silicon nitride. In another embodiment, the intermediate structure is subjected to thermal soaking in silane or silane plasma treatment before and after depositing the tantalum nitride layer. Embodiments further include pretreating the intermediate structure with silane prior to depositing the tantalum nitride layer, treating the deposited tantalum nitride layer with silane, and repeating these steps a number of times to form a plurality of sub-layers of silicon-rich tantalum silicon nitride.
摘要翻译：微型半导体器件由富含硅的钽氮化硅替代金属栅电极制成。实施例包括去除可移除栅极，通过PVD沉积氮化钽层，厚度为25埃，然后通过在硅烷或硅烷等离子体处理中热浸泡形成层，将硅引入沉积的氮化钽层中的富硅钽硅氮化物。在另一个实施方案中，在沉积氮化钽层之前和之后，使中间体在硅烷或硅烷等离子体处理中进行热浸。实施例还包括在沉积氮化钽层之前用硅烷预处理中间结构，用硅烷处理沉积的氮化钽层，并重复这些步骤多次以形成多个富硅钽硅氮化物的子层。

2. 发明授权

US06830998B1 Gate dielectric quality for replacement metal gate transistors 失效
标题翻译：更换金属栅极晶体管的栅极介电质量得到改善
公开(公告)号：US06830998B1
公开(公告)日：2004-12-14
申请号：US10462667
申请日：2003-06-17
申请人： James Pan , Paul Besser , Christy Mei-Chu Woo , Minh Van Ngo , Jinsong Yin
发明人： James Pan , Paul Besser , Christy Mei-Chu Woo , Minh Van Ngo , Jinsong Yin
IPC分类号： H01L213205
CPC分类号： H01L29/66606 , H01L21/28088 , H01L29/4966 , H01L29/66545
摘要： Gate dielectric degradation due to plasma damage during replacement metal gate processing is cured and prevented from further plasma degradation by treatment of the gate dielectric after removing the polysilicon gate. Embodiments include low temperature vacuum annealing after metal deposition and CMP, annealing in oxygen and argon, ozone or a forming gas before metal deposition, or heat soaking in silane or disilane, before metal deposition.
摘要翻译：在更换金属栅极处理期间由于等离子体损坏引起的栅极介质劣化被固化并且通过在去除多晶硅栅极之后处理栅极电介质来防止进一步的等离子体劣化。实施例包括在金属沉积之前的金属沉积和CMP之后的低温真空退火，在氧气和氩气中的退火，在金属沉积之前的臭氧或形成气体，或者在金属沉积之前的硅烷或乙硅烷中的热浸渍。

3. 发明授权

US07060571B1 Semiconductor device with metal gate and high-k tantalum oxide or tantalum oxynitride gate dielectric 有权
标题翻译：具有金属栅极和高k钽氧化物或氮氧化钽栅极电介质的半导体器件
公开(公告)号：US07060571B1
公开(公告)日：2006-06-13
申请号：US10777138
申请日：2004-02-13
申请人： Minh Van Ngo , Christy Woo , James Pan , Paul R. Besser , Jinsong Yin
发明人： Minh Van Ngo , Christy Woo , James Pan , Paul R. Besser , Jinsong Yin
IPC分类号： H01L21/336
CPC分类号： H01L21/28229 , H01L21/28079 , H01L21/28088 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： Microminiaturized semiconductor devices are fabricated with a replacement metal gate and a high-k tantalum oxide or tantalum oxynitride gate dielectric with significantly reduced carbon. Embodiments include forming an opening in a dielectric layer by removing a removable gate, depositing a thin tantalum film, as by PVD at a thickness of 25 Å to 60 Å lining the opening, and then conducting thermal oxidation, as at a temperature of 100° C. to 500° C., in flowing oxygen or ozone to form a high-k tantalum oxide gate dielectric layer, or in oxygen and N2O or ozone and N2O ammonia to form a high-k tantalum oxynitride gate dielectric. Alternatively, oxidation can be conducted in an oxygen or ozone plasma to form the high-k tantalum oxide layer, or in a plasma containing N2O and oxygen or ozone to form the high-k tantalum oxynitride gate dielectric layer.
摘要翻译：微型半导体器件由具有显着降低的碳的替代金属栅极和高k钽氧化物或氮氧化钽栅极电介质制成。实施例包括通过去除可移除栅极来形成电介质层中的开口，沉积薄的钽膜，如通过PVD覆盖厚度为25埃至60埃的开口，然后在100℃的温度下进行热氧化在500℃下，在流动的氧气或臭氧中形成高k氧化钽栅极电介质层，或在氧和N 2 O或臭氧和N 2 O 3 > O氨形成高k钽氮氧化物栅极电介质。或者，可以在氧气或臭氧等离子体中进行氧化以形成高k钽氧化物层，或者在含有N 2 O的氧化物或臭氧的等离子体中进行氧化以形成高k氮氧化钽栅极电介质层。

4. 发明授权

US07071086B2 Method of forming a metal gate structure with tuning of work function by silicon incorporation 有权
标题翻译：通过硅掺入调整功函数形成金属栅结构的方法
公开(公告)号：US07071086B2
公开(公告)日：2006-07-04
申请号：US10420721
申请日：2003-04-23
申请人： Christy Woo , Paul Besser , Minh van Ngo , James Pan , Jinsong Yin
发明人： Christy Woo , Paul Besser , Minh van Ngo , James Pan , Jinsong Yin
IPC分类号： H01L21/3205
CPC分类号： H01L29/66545 , H01L21/28079 , H01L21/28088 , H01L21/3215 , H01L29/495 , H01L29/4966 , H01L29/78
摘要： A method for forming a semiconductor structure having a metal gate with a controlled work function includes the step of forming a precursor having a substrate with active regions separated by a channel, a temporary gate over the channel and within a dielectric layer. The temporary gate is removed to form a recess with a bottom and sidewalls in the dielectric layer. A non-silicon containing metal layer is deposited in the recess. Silicon is incorporated into the metal layer and a metal is deposited on the metal layer. The incorporation of the silicon is achieved by silane treatments that are performed before, after or both before and after the depositing of the metal layer. The amount of silicon incorporated into the metal layer controls the work function of the metal gate that is formed.
摘要翻译：用于形成具有受控功函数的金属栅极的半导体结构的方法包括形成具有基板的前体的步骤，该基板具有被沟道分隔的有源区，在该沟道上的介电层内的临时栅极。移除临时栅极以形成具有介电层中的底部和侧壁的凹部。在凹槽中沉积非硅的金属层。将硅结合到金属层中，并且在金属层上沉积金属。通过在沉积金属层之前，之后或之后进行的硅烷处理来实现硅的引入。结合到金属层中的硅的量控制形成的金属栅的功函数。

5. 发明授权

US08772169B2 Technique for controlling trench profile in semiconductor structures 有权
公开(公告)号：US08772169B2
公开(公告)日：2014-07-08
申请号：US12109302
申请日：2008-04-24
申请人： Hui Chen , Qi Wang , Briant Harward , James Pan
发明人： Hui Chen , Qi Wang , Briant Harward , James Pan
IPC分类号： H01L21/311
摘要： A method for forming a semiconductor structure includes the following steps. Trenches are formed in a semiconductor region using a masking layer such that the trenches have a first depth, a first width along their bottom, and sidewalls having a first slope. The masking layer is removed, and a bevel etch is performed to taper the sidewalls of the trenches so that the sidewalls have a second slope less than the first slope.

6. 发明授权

US08669623B2 Structure related to a thick bottom dielectric (TBD) for trench-gate devices 有权
标题翻译：与沟槽栅极器件的厚底部电介质（TBD）有关的结构
公开(公告)号：US08669623B2
公开(公告)日：2014-03-11
申请号：US12870600
申请日：2010-08-27
申请人： James Pan , Christopher Lawrence Rexer
发明人： James Pan , Christopher Lawrence Rexer
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/8725
摘要： A semiconductor structure which includes a shielded gate FET is formed as follows. A plurality of trenches is formed in a semiconductor region using a mask. The mask includes (i) a first insulating layer over a surface of the semiconductor region, (ii) a first oxidation barrier layer over the first insulating layer, and (iii) a second insulating layer over the first oxidation barrier layer. A shield dielectric is formed extending along at least lower sidewalls of each trench. A thick bottom dielectric (TBD) is formed along the bottom of each trench. The first oxidation barrier layer prevents formation of a dielectric layer along the surface of the semiconductor region during formation of the TBD. A shield electrode is formed in a bottom portion of each trench. A gate electrode is formed over the shield electrode in each trench.
摘要翻译：包括屏蔽栅极的半导体结构如下形成。使用掩模在半导体区域中形成多个沟槽。掩模包括（i）半导体区域的表面上的第一绝缘层，（ii）第一绝缘层上的第一氧化阻挡层，以及（iii）第一氧化阻挡层上的第二绝缘层。形成在每个沟槽的至少下侧壁延伸的屏蔽电介质。沿每个沟槽的底部形成厚底部电介质（TBD）。第一氧化阻挡层防止在形成TBD期间沿着半导体区域的表面形成电介质层。屏蔽电极形成在每个沟槽的底部。在每个沟槽中的屏蔽电极之上形成栅电极。

7. 发明授权

US08541840B2 Structure and method for semiconductor power devices 有权
标题翻译：半导体功率器件的结构和方法
公开(公告)号：US08541840B2
公开(公告)日：2013-09-24
申请号：US13028054
申请日：2011-02-15
申请人： James Pan
发明人： James Pan
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/743 , H01L21/8249 , H01L21/84 , H01L27/0623 , H01L27/0635 , H01L29/1087 , H01L29/4175 , H01L29/78624
摘要： A semiconductor device includes a semiconductor-on-insulator region on a substrate. The semiconductor-on-insulator region includes a first semiconductor region overlying a dielectric region. The device includes an MOS transistor and a bipolar transistor. The MOS transistor has a drain region, a body region, and a source region in the first semiconductor region. The MOS transistor also includes a gate. The device also includes a second semiconductor region overlying the substrate and adjacent to the drain region, and a third semiconductor region overlying the substrate and adjacent to the second semiconductor region. The bipolar transistor includes has the drain region of the MOS transistor as an emitter, the second semiconductor region as a base, and the third semiconductor region as a collector. Accordingly, the drain of the MOS transistor also functions as the emitter of the bipolar transistor. Additionally, the gate and the base are coupled by a resistive element.
摘要翻译：半导体器件包括在衬底上的绝缘体上半导体区域。绝缘体上半导体区域包括覆盖电介质区域的第一半导体区域。该器件包括MOS晶体管和双极晶体管。 MOS晶体管在第一半导体区域中具有漏极区域，体区域和源极区域。 MOS晶体管还包括一个栅极。该器件还包括覆盖衬底并且与漏极区相邻的第二半导体区域，以及覆盖衬底并与第二半导体区域相邻的第三半导体区域。双极晶体管包括MOS晶体管的漏极区域作为发射极，第二半导体区域作为基极，第三半导体区域作为集电极。因此，MOS晶体管的漏极也用作双极晶体管的发射极。此外，栅极和基极通过电阻元件耦合。

8. 发明授权

US08329538B2 Shielded gate trench FET with an inter-electrode dielectric having a low-k dielectric therein 有权
标题翻译：屏蔽栅沟槽FET，其中具有低k电介质的电极间电介质
公开(公告)号：US08329538B2
公开(公告)日：2012-12-11
申请号：US13083253
申请日：2011-04-08
申请人： James Pan , James J. Murphy
发明人： James Pan , James J. Murphy
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/51 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66727 , H01L29/66734
摘要： A method for forming a shielded gate trench field effect transistor (FET) includes forming trenches in a semiconductor region, forming a shield electrode in a bottom portion of each trench, and forming an inter-electrode dielectric (IED) extending over the shield electrode. The IED may comprise a low-k dielectric. The method also includes forming a gate electrode in an upper portion of each trench over the IED.
摘要翻译：一种用于形成屏蔽栅极沟道场效应晶体管（FET）的方法包括在半导体区域中形成沟槽，在每个沟槽的底部形成屏蔽电极，并形成在屏蔽电极上延伸的电极间电介质（IED）。 IED可以包括低k电介质。该方法还包括在IED上的每个沟槽的上部形成栅电极。

9. 发明申请

US20120292676A1 Novel Very Fast Optic Nonvolatile Memory with Alternative Carrier Lifetimes and Bandgap Energies, Optic Random Access, and Mirrored "Fly-back" Configurations 审中-公开
标题翻译：具有替代载波寿命和带隙能量的新型非常快速的非易失性存储器，光学随机存取和镜像“反馈”配置
公开(公告)号：US20120292676A1
公开(公告)日：2012-11-22
申请号：US13113048
申请日：2011-05-21
申请人： James Pan
发明人： James Pan
IPC分类号： H01L31/113
CPC分类号： G11C13/047
摘要： The present invention is for a fast optic nonvolatile memory cell (FONM) that operates with a speed >1000000 times faster than the commercially available FLASH memory. The information (or charges) can be entered into the FONM cell by switching on a built-in laser or LED (Light Emitting Diode). Excited by the lights, and driven by electric fields, the regions of low carrier lifetimes thermally generate excess electrons or positive charges to fill the storage gaps or interfaces. To detect the stored information, two BJTs (Bipolar Junction Transistors) are arranged in a mirrored configuration—with alternative regions of high or low carrier lifetimes and bandgap energies. By comparing the BJT “fly-back” characteristics a voltage difference can be detected as a signal of whether the information is stored or not stored.
摘要翻译：本发明用于快速光学非易失性存储单元（FONM），其以比市售的闪速存储器快1000000倍的速度运行。通过打开内置激光或LED（发光二极管）可以将信息（或电荷）输入到FONM单元。由光激发，由电场驱动，低载流子寿命的区域会产生过量的电子或正电荷，以填充储存间隙或界面。为了检测存储的信息，两个BJT（双极结晶体管）被布置成镜像配置 - 具有高或低载波寿命和带隙能量的替代区域。通过比较BJT回扫特性，可以检测电压差是否存储信息或不存储信息。

10. 发明申请

US20120273884A1 Superjunction Structures for Power Devices and Methods of Manufacture 有权
标题翻译：功率器件的超结构和制造方法
公开(公告)号：US20120273884A1
公开(公告)日：2012-11-01
申请号：US13095690
申请日：2011-04-27
申请人： Joseph A. Yedinak , Christopher L. Rexer , Mark L. Rinehimer , Praveen Muraleedharan Shenoy , Jaegil Lee , Hamza Yilmaz , Chongman Yun , Dwayne S. Reichl , James Pan , Rodney S. Ridley, SR. , Harold Heidenreich
发明人： Joseph A. Yedinak , Christopher L. Rexer , Mark L. Rinehimer , Praveen Muraleedharan Shenoy , Jaegil Lee , Hamza Yilmaz , Chongman Yun , Dwayne S. Reichl , James Pan , Rodney S. Ridley, SR. , Harold Heidenreich
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0878 , H01L29/045 , H01L29/0634 , H01L29/0646 , H01L29/0649 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/404 , H01L29/42372 , H01L29/4238 , H01L29/66712 , H01L29/66734 , H01L29/7811 , H01L29/7813 , H01L29/872 , H01L29/8725
摘要： A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.
摘要翻译：功率器件包括半导体区域，该半导体区域又包括多个交替布置的第一和第二导电类型的柱。第二导电类型的多个柱中的每一个还包括沿着第二导电类型的柱的深度彼此顶部布置的多个第二导电类型的注入区，以及填充有第二导电类型的半导体材料的沟槽部在第二导电类型的多个植入区域的正上方。

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