专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 实用新型

TWM298437U 留置針之改良失效
简体标题：留置针之改良
公开(公告)号：TWM298437U
公开(公告)日：2006-10-01
申请号：TW095206727
申请日：2006-04-20
申请人：林泰亨 , 林明仁 MING-REN LIN
发明人：林泰亨 , 林明仁 MING-REN LIN
IPC分类号： A61M
摘要：本案係一種留置針之改良，其包括：一斜錐管，其具一接孔；一中繼管，係為可壓捏變形管體，其中央開具一貫穿之中繼管；前端連結於接孔；一輸送管，係為尺寸較中繼管為小之管體，其中央開具貫穿之孔洞；其一端穿套入中繼孔並穿越接孔，且至少前端一段突出於斜錐管；一外接管，亦為管體，其中央具一外接孔，一端連結於輸送管，另端則可供外接；俾輸液可經由外接孔後，全程通過輸送管而至人體體內者。
简体摘要：本案系一种留置针之改良，其包括：一斜锥管，其具一接孔；一中继管，系为可压捏变形管体，其中央开具一贯穿之中继管；前端链接于接孔；一输送管，系为尺寸较中继管为小之管体，其中央开具贯穿之孔洞；其一端穿套入中继孔并穿越接孔，且至少前端一段突出于斜锥管；一外置管，亦为管体，其中央具一外置孔，一端链接于输送管，另端则可供外置；俾输液可经由外置孔后，全程通过输送管而至人体体内者。

2. 实用新型

TWM287404U 多方向調整肘節失效
简体标题：多方向调整肘节
公开(公告)号：TWM287404U
公开(公告)日：2006-02-11
申请号：TW094218135
申请日：2005-10-20
申请人：林明仁 MING-REN LIN
发明人：林明仁 MING-REN LIN
IPC分类号： F16M
摘要：本案係一種多方向調整肘節係由一下環座，一桿架，一上環座，一中繼座，一球座，一彈性元件所組合而成。俾可藉旋轉桿架之旋鈕，使其與一楔形塊間之凸部與凸部的彼此頂抵，或者凸部與凹部的彼此接合，而促使該楔形塊沿著下、上環座座槽及座斜向內或向外移動，進而將上環座上頂或下移，而為上環座、中繼座及球座間密合度之鬆緊調整者。
简体摘要：本案系一种多方向调整肘节系由一下环座，一杆架，一上环座，一中继座，一球座，一弹性组件所组合而成。俾可藉旋转杆架之旋钮，使其与一楔形块间之凸部与凸部的彼此顶抵，或者凸部与凹部的彼此接合，而促使该楔形块沿着下、上环座座槽及座斜向内或向外移动，进而将上环座上顶或下移，而为上环座、中继座及球座间密合度之松紧调整者。

3. 发明申请

US20100015778A1 METHOD OF FORMING FINNED SEMICONDUCTOR DEVICES WITH TRENCH ISOLATION 有权
标题翻译：形成具有热分解的微结构半导体器件的方法
公开(公告)号：US20100015778A1
公开(公告)日：2010-01-21
申请号：US12176866
申请日：2008-07-21
申请人： Ming-ren LIN , Zoran KRIVOKAPIC , Witek MASZARA
发明人： Ming-ren LIN , Zoran KRIVOKAPIC , Witek MASZARA
IPC分类号： H01L21/76
CPC分类号： H01L21/823431 , H01L21/76232 , H01L29/66795 , H01L29/66818 , H01L29/7851
摘要： A method of manufacturing a semiconductor device structure, such as a FinFET device structure, is provided. The method begins by providing a substrate comprising a bulk semiconductor material, a first conductive fin structure formed from the bulk semiconductor material, and a second conductive fin structure formed from the bulk semiconductor material. The first conductive fin structure and the second conductive fin structure are separated by a gap. Next, spacers are formed in the gap and adjacent to the first conductive fin structure and the second conductive fin structure. Thereafter, an etching step etches the bulk semiconductor material, using the spacers as an etch mask, to form an isolation trench in the bulk semiconductor material. A dielectric material is formed in the isolation trench, over the spacers, over the first conductive fin structure, and over the second conductive fin structure. Thereafter, at least a portion of the dielectric material and at least a portion of the spacers are etched away to expose an upper section of the first conductive fin structure and an upper section of the second conductive fin structure, while preserving the dielectric material in the isolation trench. Following these steps, the fabrication of the devices is completed in a conventional manner.
摘要翻译：提供了诸如FinFET器件结构的半导体器件结构的制造方法。该方法开始于提供包括体半导体材料的衬底，由体半导体材料形成的第一导电鳍结构以及由体半导体材料形成的第二导电鳍结构。第一导电鳍结构和第二导电鳍结构被间隙分开。接下来，间隔件形成在间隙中并且与第一导电翅片结构和第二导电翅片结构相邻。此后，蚀刻步骤使用间隔物作为蚀刻掩模来蚀刻体半导体材料，以在体半导体材料中形成隔离沟槽。绝缘材料形成在隔离沟槽中，在间隔物之上，在第一导电鳍结构之上，并在第二导电鳍结构之上。此后，介电材料的至少一部分和至少一部分间隔物被蚀刻掉以露出第一导电鳍结构的上部和第二导电翅片结构的上部，同时将介电材料保留在隔离沟按照这些步骤，以常规方式完成装置的制造。

4. 发明授权

US07422961B2 Method of forming isolation regions for integrated circuits 有权
标题翻译：形成集成电路隔离区的方法
公开(公告)号：US07422961B2
公开(公告)日：2008-09-09
申请号：US10389456
申请日：2003-03-14
申请人： Haihong Wang , Minh-Van Ngo , Qi Xiang , Paul R. Besser , Eric N. Paton , Ming-Ren Lin
发明人： Haihong Wang , Minh-Van Ngo , Qi Xiang , Paul R. Besser , Eric N. Paton , Ming-Ren Lin
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L21/823481 , H01L29/1054
摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a CVD process.
摘要翻译：集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。浅沟槽隔离技术用于应变硅（SMOS）工艺。用于沟槽的衬垫由半导体或金属层形成，该半导体或金属层在低温过程中沉积，这降低了锗除气。低温工艺可以是CVD工艺。

5. 发明申请

US20080054316A1 STRAINED FULLY DEPLETED SILICON ON INSULATOR SEMICONDUCTOR DEVICE 有权
标题翻译：绝缘子半导体器件上残留的全部绝缘硅
公开(公告)号：US20080054316A1
公开(公告)日：2008-03-06
申请号：US11926655
申请日：2007-10-29
申请人： Qi Xiang , Niraj Subba , Witold Maszara , Zoran Krivokapic , Ming-Ren Lin
发明人： Qi Xiang , Niraj Subba , Witold Maszara , Zoran Krivokapic , Ming-Ren Lin
IPC分类号： H01L29/78
CPC分类号： H01L29/66772 , H01L29/66636 , H01L29/7842 , H01L29/7848 , H01L29/78639 , H01L29/78684 , Y10S438/938
摘要： A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.
摘要翻译：提供了一种在绝缘体上具有半导体层的绝缘体的半导体衬底。形成深沟槽隔离，向半导体层引入应变。栅极电介质和栅极形成在半导体层上。在栅极周围形成间隔物，并且将半导体层和绝缘体去除在间隔物的外部。凹陷的源极/漏极形成在间隔物外部。

6. 发明申请

US20060177998A1 FULLY SILICIDED GATE STRUCTURE FOR FINFET DEVICES 有权
标题翻译： FINFET器件的完全硅胶结构
公开(公告)号：US20060177998A1
公开(公告)日：2006-08-10
申请号：US11379435
申请日：2006-04-20
申请人： Ming-Ren Lin , Witold Maszara , Haihong Wang , Bin Yu
发明人： Ming-Ren Lin , Witold Maszara , Haihong Wang , Bin Yu
IPC分类号： H01L21/3205
CPC分类号： H01L29/785 , H01L29/4908 , H01L29/66795 , H01L29/7842
摘要： A method may include forming a gate electrode over a fin structure, depositing a first metal layer on a top surface of the gate electrode, performing a first silicide process to convert a portion of the gate electrode into a metal-silicide compound, depositing a second metal layer on a top surface of the metal-silicide compound, and performing a second silicide process to form a fully-silicided gate electrode.
摘要翻译：一种方法可以包括在鳍结构上形成栅电极，在栅电极的顶表面上沉积第一金属层，执行第一硅化工艺以将栅电极的一部分转化为金属硅化物，在金属硅化物化合物的顶表面上的金属层，并且执行第二硅化物处理以形成全硅化物栅电极。

7. 发明授权

US06943087B1 Semiconductor on insulator MOSFET having strained silicon channel 有权
标题翻译：具有应变硅沟道的半导体绝缘体MOSFET
公开(公告)号：US06943087B1
公开(公告)日：2005-09-13
申请号：US10738529
申请日：2003-12-17
申请人： Qi Xiang , Jung-Suk Goo , James N. Pan , Ming Ren Lin
发明人： Qi Xiang , Jung-Suk Goo , James N. Pan , Ming Ren Lin
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L29/66545 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/66772 , H01L29/7848 , H01L29/78654
摘要： Strained silicon is grown on a dielectric material in a trench in a silicon germanium layer at a channel region of a MOSFET after fabrication of other MOSFET elements using a removable dummy gate process to form an SOI MOSFET. The MOSFET is fabricated with the dummy gate in place, the dummy gate is removed, and a trench is formed in the channel region. Dielectric material is grown in the trench, and strained silicon is then grown from the silicon germanium trench sidewalls to form a strained silicon layer that extends across the dielectric material. The silicon germanium sidewalls impart strain to the strained silicon, and the presence of the dielectric material allows the strained silicon to be grown as a thin fully depleted layer. A replacement gate is then formed by damascene processing.
摘要翻译：在使用可移除的虚拟栅极工艺制造其它MOSFET元件以形成SOI MOSFET之后，将应变硅在MOSFET的沟道区的硅锗层中的沟槽中的电介质材料上生长。 MOSFET由虚拟栅极制造在位，虚拟栅极被去除，并且在沟道区域中形成沟槽。电介质材料在沟槽中生长，然后从硅锗沟槽侧壁生长应变硅，以形成延伸穿过电介质材料的应变硅层。硅锗侧壁对应变硅施加应变，并且电介质材料的存在允许应变硅作为薄的完全耗尽层生长。然后通过镶嵌加工形成替换浇口。

8. 发明授权

US06858503B1 Depletion to avoid cross contamination 失效
标题翻译：消耗以避免交叉污染
公开(公告)号：US06858503B1
公开(公告)日：2005-02-22
申请号：US10358484
申请日：2003-02-05
申请人： Minh V. Ngo , Ming-Ren Lin , Paul R. Besser , Qi Xiang , Eric N. Paton , Jung-Suk Goo
发明人： Minh V. Ngo , Ming-Ren Lin , Paul R. Besser , Qi Xiang , Eric N. Paton , Jung-Suk Goo
IPC分类号： H01L21/306 , H01L29/10 , H01L21/336
CPC分类号： H01L21/02046 , H01L29/1054
摘要： A fabrication system utilizes a protocol for removing germanium from a top surface of a wafer. An exposure to a gas, such as a gas containing the hydrochloric acid can remove germanium from the top surface. The protocol can allow shared equipment to be used in both Flash product fabrication lines and strained silicon (SMOS) fabrication lines. The protocol allows better silicidation in SMOS devices.
摘要翻译：制造系统利用从晶片顶表面去除锗的方案。暴露于气体，如含有盐酸的气体，可以从上表面除去锗。该协议可以允许在Flash产品制造线和应变硅（SMOS）生产线中使用共享设备。该协议允许在SMOS器件中更好的硅化。

9. 发明授权

US06855982B1 Self aligned double gate transistor having a strained channel region and process therefor 有权
标题翻译：具有应变通道区域的自对准双栅极晶体管及其工艺
公开(公告)号：US06855982B1
公开(公告)日：2005-02-15
申请号：US10770163
申请日：2004-02-02
申请人： Qi Xiang , James N. Pan , Ming Ren Lin
发明人： Qi Xiang , James N. Pan , Ming Ren Lin
IPC分类号： H01L21/336 , H01L29/51 , H01L29/786 , H11L29/76
CPC分类号： H01L29/78696 , H01L29/51 , H01L29/518 , H01L29/66742 , H01L29/7842 , H01L29/78648 , H01L29/78684
摘要： A method of manufacturing an integrated circuit with a strained semiconductor channel region. The method can provide a double gate structure. The gate structure can be provided in and above a trench. The trench can be formed in a compound semiconductor material such as a silicon-germanium material. The strained semiconductor can increase the charge mobility associated with the transistor. A silicon-on-insulator substrate can be used.
摘要翻译：一种制造具有应变半导体沟道区域的集成电路的方法。该方法可以提供双栅结构。栅极结构可以设置在沟槽中和沟槽上方。沟槽可以形成在诸如硅 - 锗材料的化合物半导体材料中。应变半导体可以增加与晶体管相关的电荷迁移率。可以使用绝缘体上硅衬底。

10. 发明授权

US06764966B1 Spacers with a graded dielectric constant for semiconductor devices having a high-K dielectric 有权
标题翻译：具有高K电介质的半导体器件具有渐变介电常数的间隔物
公开(公告)号：US06764966B1
公开(公告)日：2004-07-20
申请号：US10085278
申请日：2002-02-27
申请人： William George En , Arvind Halliyal , Ming-Ren Lin , Minh Van Ngo , Chih-Yuh Yang
发明人： William George En , Arvind Halliyal , Ming-Ren Lin , Minh Van Ngo , Chih-Yuh Yang
IPC分类号： H01L2128
CPC分类号： H01L29/6656 , H01L29/66833 , H01L29/78
摘要： A semiconductor device formed on a semiconductor substrate having an active region and a method of making the same is disclosed. The semiconductor device includes a dielectric layer interposed between a gate electrode and the semiconductor substrate. Further, the semiconductor device includes graded dielectric constant spacers formed on sidewalls of the dielectric layer, sidewalls of the gate electrode and portions of an upper surface of the semiconductor substrate. The dielectric constant of the graded dielectric constant spacers decreases in a direction away from the sidewalls of the dielectric layer.
摘要翻译：公开了一种形成在具有有源区的半导体衬底上的半导体器件及其制造方法。半导体器件包括插入在栅电极和半导体衬底之间的电介质层。此外，半导体器件包括形成在电介质层的侧壁，栅电极的侧壁和半导体衬底的上表面的部分上的渐变介电常数间隔物。梯度介电常数间隔物的介电常数在远离介电层的侧壁的方向上减小。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式