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61. 发明授权

US06583051B2 Method of manufacturing an amorphized barrier layer for integrated circuit interconnects 失效
公开(公告)号：US06583051B2
公开(公告)日：2003-06-24
申请号：US09989972
申请日：2001-11-20
申请人： Sergey D. Lopatin , Minh Van Ngo , Minh Quoc Tran
发明人： Sergey D. Lopatin , Minh Van Ngo , Minh Quoc Tran
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/76862 , H01L21/76873 , H01L23/53209 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A manufacturing method for an integrated circuit is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. An amorphized barrier layer lines the opening and a seed layer is deposited to line the amorphized barrier layer. A conductor core fills the opening over the barrier layer to form a conductor channel. The seed layer is securely bonded to the amorphized barrier layer and prevents electromigration along the surface between the seed and barrier layers.

62. 发明授权

US06576548B1 Method of manufacturing a semiconductor device with reliable contacts/vias 有权
标题翻译：制造具有可靠接触/通孔的半导体器件的方法
公开(公告)号：US06576548B1
公开(公告)日：2003-06-10
申请号：US10079861
申请日：2002-02-22
申请人： Amy Tu , Minh Van Ngo , Austin Frenkel , Robert J. Chiu , Jeff Erhardt
发明人： Amy Tu , Minh Van Ngo , Austin Frenkel , Robert J. Chiu , Jeff Erhardt
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/31105 , H01L21/76804 , H01L21/76846 , H01L21/76877
摘要： Reliable contacts/vias are formed by sputter etching to flare exposed edges of an opening formed in a dielectric layer, depositing a composite barrier layer and then filling the opening with tungsten at a low deposition rate. The resulting contact/via exhibits significantly reduced porosity and contact resistance. Embodiments include sputter etching to incline the edges of an opening formed in an oxide dielectric layer, e.g., a silicon oxide derived from TEOS or BPSG, at an angle of about 83° to about 86°, depositing a thin layer of Ti, e.g., at a thickness of about 250 Å to about 350 Å, depositing at least one layer of titanium nitride, e.g., three layers of titanium nitride, at a total thickness of about 130 Å to about 170 Å, and then depositing tungsten at a deposition rate of about 1,900 to about 2,300 Å/min to fill the opening.
摘要翻译：通过溅射蚀刻形成可靠的触点/通孔，以对形成在电介质层中的开口的暴露边缘进行曝光，沉积复合阻挡层，然后以低沉积速率用钨填充开口。所得到的接触/通孔显示出显着降低的孔隙率和接触电阻。实施例包括溅射蚀刻，以约83°至约86°的角度倾斜形成在氧化物电介质层中的开口的边缘，例如衍生自TEOS或BPSG的氧化硅，沉积Ti薄层，在约250埃至大约350埃的厚度上沉积至少一层氮化钛，例如三层氮化钛，总厚度为约至约为170埃，然后以沉积速率沉积钨约1,900至约2,300埃/分钟以填充开口。

63. 发明授权

US06548403B1 Silicon oxide liner for reduced nickel silicide bridging 有权
标题翻译：用于还原硅化镍桥接的氧化硅衬垫
公开(公告)号：US06548403B1
公开(公告)日：2003-04-15
申请号：US09679871
申请日：2000-10-05
申请人： Minh Van Ngo , Christy Mei-Chu Woo
发明人： Minh Van Ngo , Christy Mei-Chu Woo
IPC分类号： H01L2144
CPC分类号： H01L29/665 , H01L29/6659
摘要： Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by forming a relatively thick silicon oxide liner on the side surfaces of the gate electrode and adjacent surface of the semiconductor substrate before forming the silicon nitride sidewall spacers thereon. Embodiments include forming a silicon dioxide liner at a thickness of about 200 Å to about 600 Å prior to forming the silicon nitride sidewall spacers thereon.
摘要翻译：在形成氮化硅侧壁之前，通过在栅电极的侧表面和半导体衬底的相邻表面上形成相对较厚的氧化硅衬垫来防止在栅电极上的硅化镍层与氮化硅侧壁间隔物之间的源极/漏极区之间的桥接垫片。在形成氮化硅侧壁间隔物之前，实施例包括在大约至大约600埃的厚度形成二氧化硅衬垫。

64. 发明授权

US06492258B1 METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25-&mgr;M AND SMALLER SEMICONDUCTOR CHIP TECHNOLOGY BY ANNEALING INTERCONNECT LINES AND USING LOW BIAS VOLTAGE AND LOW INTERLAYER DIELECTRIC DEPOSITION RATE AND SEMICONDUCTOR CHIP MADE THEREBY 有权
标题翻译：用于通过退火互连线和使用低偏置电压和低中间层介电沉积速率和半导体芯片制造来减少0.25微米和小型半导体芯片技术的应力诱发电位的方法
公开(公告)号：US06492258B1
公开(公告)日：2002-12-10
申请号：US09881831
申请日：2001-06-14
申请人： Minh Van Ngo , Paul R. Besser , Matthew Buynoski , John Caffall , Nick Maccrae , Richard J. Huang , Khanh Tran
发明人： Minh Van Ngo , Paul R. Besser , Matthew Buynoski , John Caffall , Nick Maccrae , Richard J. Huang , Khanh Tran
IPC分类号： H01L214763
CPC分类号： H01L21/7685 , H01L21/76837 , H01L21/76858 , H01L21/76885 , H01L23/53223 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： A method for making 0.25-micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the contraction being absorbed by the aluminum. Because the alloy is reacted prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation. in the interconnect lines is reduced. The likelihood of undesirable void formation is still further reduced during the subsequent ILD gapfill deposition process by using relatively low bias power to reduce vapor deposition temperature. and by using relatively low source gas deposition flow rates to reduce flow-induced compressive stress on the interconnect lines during ILD formation.
摘要翻译：制造0.25微米半导体芯片的方法包括在线之间沉积层间电介质（ILD）之前退火金属互连线。在退火期间，形成铝和钛的合金，其随后容积收缩，铝的收缩被铝吸收。因为合金在ILD沉积之前反应，所以当铝试图吸收合金的收缩时，铝不受ILD的约束。因此，形成不希望的空隙的可能性。在互连线路中减少。在随后的ILD间隙填充沉积过程中，通过使用相对低的偏压功率来降低气相沉积温度，仍然进一步降低了不希望的空隙形成的可能性。并且通过使用相对低的源气体沉积流速来减少在ILD形成期间在互连线上的流动引起的压缩应力。

65. 发明授权

US06472755B1 Semiconductor device comprising copper interconnects with reduced in-line copper diffusion 有权
标题翻译：包括具有减少的在线铜扩散的铜互连的半导体器件
公开(公告)号：US06472755B1
公开(公告)日：2002-10-29
申请号：US09688928
申请日：2000-10-17
申请人： Minh Van Ngo , Takeshi Nogami
发明人： Minh Van Ngo , Takeshi Nogami
IPC分类号： H01L2348
CPC分类号： H01L23/53238 , H01L21/76826 , H01L21/76829 , H01L21/76834 , H01L21/76883 , H01L23/53233 , H01L2924/0002 , H01L2924/00
摘要： Cu diffusion between Cu and Cu alloy interconnect members, e.g., lines, in a silicon oxide inter-layer dielectric is avoided or substantially reduced by converting an upper portion of the silicon oxide inter-layer dielectric between neighboring lines to silicon oxynitride and then depositing a capping layer. Embodiments include filling damascene trenches in a silicon oxide inter-layer dielectric with Cu or a Cu alloy, CMP to effect planarization such that the upper surfaces of the lines are substantially coplanar with the upper surface of the inter-layer dielectric and treating the exposed surfaces with a high strength ammonia plasma to ion bombard the exposed inter line silicon oxide with nitrogen atoms, thereby converting the upper portion to silicon oxynitride, while simultaneously removing or substantially reducing surface oxides on the lines. A silicon nitride capping layer is then deposited.
摘要翻译：通过将相邻线路之间的氧化硅层间电介质的上部部分转换为氮氧化硅，然后沉积氧化硅层，从而避免或基本上减少氧化硅层间电介质中Cu和Cu合金互连构件（例如线）之间的Cu扩散盖层实施例包括用Cu或Cu合金填充氧化硅层间电介质中的镶嵌沟槽CMP，以实现平面化，使得线的上表面与层间电介质的上表面基本上共面并且处理暴露表面用高强度氨等离子体离子轰击具有氮原子的暴露的线间氧化硅，从而将上部转化为氮氧化硅，同时除去或显着还原线上的表面氧化物。然后沉积氮化硅覆盖层。

66. 发明授权

US06469385B1 Integrated circuit with dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers 有权
标题翻译：集成电路与介质扩散阻挡层形成在互连和层间电介质层之间
公开(公告)号：US06469385B1
公开(公告)日：2002-10-22
申请号：US09874175
申请日：2001-06-04
申请人： Steven C. Avanzino , Pin-Chin Connie Wang , Minh Van Ngo
发明人： Steven C. Avanzino , Pin-Chin Connie Wang , Minh Van Ngo
IPC分类号： H01L23522
CPC分类号： H01L23/5329 , H01L21/76814 , H01L21/76826 , H01L21/76831 , H01L21/76841 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer formed over the semiconductor substrate has an opening provided therein. The dielectric layer is of non-barrier dielectric material capable of being changed into a barrier dielectric material. The dielectric layer around the opening is changed into the barrier dielectric material and the conductor core material is deposited to fill the opening. The conductor core is processed to form a channel for the integrated circuit.
摘要翻译：提供了具有半导体器件的半导体衬底的集成电路及其制造方法。形成在半导体衬底上的电介质层具有设置在其中的开口。电介质层是能够改变为阻挡介电材料的非阻挡介电材料。开口周围的电介质层变成阻挡电介质材料，并且沉积导体芯材以填充开口。处理导体芯以形成用于集成电路的通道。

67. 发明授权

US06459155B1 Damascene processing employing low Si-SiON etch stop layer/arc 有权
标题翻译：使用低Si-SiON蚀刻停止层/电弧的镶嵌加工
公开(公告)号：US06459155B1
公开(公告)日：2002-10-01
申请号：US09729528
申请日：2000-12-05
申请人： Ramkumar Subramanian , Dawn M. Hopper , Minh Van Ngo
发明人： Ramkumar Subramanian , Dawn M. Hopper , Minh Van Ngo
IPC分类号： H01L214763
CPC分类号： H01L21/76829 , H01L21/0276 , H01L21/0332 , H01L21/76807
摘要： The dimensional accuracy of trench formation and, hence, metal line width, in damascene technology is improved by employing a low Si—SiON etch stop layer/ARC with reduced etch selectivity with respect to the overlying dielectric material but having a reduced extinction coefficient (k). Embodiments include via first-trench last dual damascene techniques employing a low Si—SiON middle etch stop layer/ARC having an extinction coefficient of about −0.3 to about −0.6, e.g., about −0.35, with reduced silicon and increased oxygen vis-à-vis a SiON etch stop layer having an extinction coefficient of about −1.1. Embodiments also include removing about 60% to about 90% of the low Si—SiON etch stop layer/ARC during trench formation, thereby reducing capacitance.
摘要翻译：通过使用低Si-SiON蚀刻停止层/ ARC，相对于上覆电介质材料具有降低的蚀刻选择性但具有降低的消光系数（k（k）），改善了镶嵌技术中沟槽形成的尺寸精度以及因此金属线宽度）。实施例包括通过第一沟槽最后的双镶嵌技术，其使用具有约-0.3至约-0.6，例如约-0.35的消光系数的低Si-SiON中间蚀刻停止层/ ARC，其中还原的硅和增加的氧相对于 - 具有约-1.1的消光系数的SiON蚀刻停止层。实施例还包括在沟槽形成期间去除约60％至约90％的低Si-SiON蚀刻停止层/ ARC，从而降低电容。

68. 发明授权

US06432817B1 Tungsten silicide barrier for nickel silicidation of a gate electrode 有权
标题翻译：用于栅电极的硅化硅的硅化钨屏障
公开(公告)号：US06432817B1
公开(公告)日：2002-08-13
申请号：US09731024
申请日：2000-12-07
申请人： Jacques J. Bertrand , Christy Mei-Chu Woo , Minh Van Ngo , George Kluth
发明人： Jacques J. Bertrand , Christy Mei-Chu Woo , Minh Van Ngo , George Kluth
IPC分类号： H01L214763
CPC分类号： H01L29/4941 , H01L21/28052 , H01L21/28518 , H01L29/665
摘要： Nickel silicidation of a gate electrode is controlled using a tungsten silicide barrier layer. Embodiments include forming a gate electrode structure comprising a lower polycrystalline silicon layer, a layer of tungsten silicide thereon and an upper polycrystalline silicon layer on the tungsten silicide layer, depositing a layer of nickel and silicidizing, whereby the upper polycrystalline silicon layer is converted to nickel silicide and the tungsten silicide barrier layer prevents nickel from reacting with the lower polycrystalline silicon layer.
摘要翻译：使用硅化钨阻挡层来控制栅电极的镍硅化。实施例包括在硅化钨层上形成包括下多晶硅层，硅化钨层和上多晶硅层的栅电极结构，沉积镍层和硅化层，由此将上多晶硅层转变为镍硅化物和硅化钨阻挡层防止镍与下部多晶硅层反应。

69. 发明授权

US06383950B1 Insulating and capping structure with preservation of the low dielectric constant of the insulating layer 有权
标题翻译：绝缘和封盖结构保存绝缘层的低介电常数
公开(公告)号：US06383950B1
公开(公告)日：2002-05-07
申请号：US09974568
申请日：2001-10-10
申请人： Suzette K. Pangrle , Minh Van Ngo , Susan Tovar
发明人： Suzette K. Pangrle , Minh Van Ngo , Susan Tovar
IPC分类号： H01L21469
CPC分类号： H01L21/76801 , H01L21/76829
摘要： An insulating and capping structure of an integrated circuit is formed on a semiconductor wafer. An insulating layer is formed on the semiconductor wafer, and the insulating layer is comprised of a dielectric material having a low dielectric constant that is less than about 4.0 and having chemical bonds that are chemically reactive with a predetermined reactant. A reaction barrier layer is formed on the insulating layer, and the reaction barrier layer is comprised of a material that is not chemically reactive with the predetermined reactant. A capping layer is formed on the reaction barrier layer, and the capping layer is formed using the predetermined reactant. The reaction barrier layer prevents contact of the predetermined reactant with the insulating layer to prevent reaction of the predetermined reactant with the chemical bonds of the dielectric material of the insulating layer that are chemically reactive with the predetermined reactant such that the low dielectric constant of the dielectric material of the insulating layer is not increased by the formation of the capping layer. The present invention may be used to particular advantage when the predetermined reactant used for forming the capping layer and that is reactive with the insulating layer is oxygen plasma and when the reaction barrier layer is comprised of silicon nitride.
摘要翻译：在半导体晶片上形成集成电路的绝缘和封盖结构。在半导体晶片上形成绝缘层，绝缘层由具有小于约4.0的低介电常数且具有与预定反应物发生化学反应的化学键的电介质材料构成。在绝缘层上形成反应阻挡层，反应阻挡层由与预定反应物不具有化学反应性的材料构成。在反应阻挡层上形成覆盖层，使用规定的反应物形成覆盖层。反应阻挡层防止预定反应物与绝缘层的接触，以防止预定反应物与绝缘层的电介质材料与预定反应物发生化学反应的化学键的反应，使得电介质的低介电常数通过形成覆盖层，绝缘层的材料不会增加。当用于形成覆盖层并且与绝缘层反应的预定反应物是氧等离子体和当反应阻挡层由氮化硅构成时，本发明可以特别有用。

70. 发明授权

US06380067B1 Method for creating partially UV transparent anti-reflective coating for semiconductors 有权
标题翻译：半导体部分UV透明抗反射涂层的制造方法
公开(公告)号：US06380067B1
公开(公告)日：2002-04-30
申请号：US09588119
申请日：2000-05-31
申请人： Ramkumar Subramanian , Minh Van Ngo , Suzette K. Pangrle , Kashmir Sahota , Christopher F. Lyons
发明人： Ramkumar Subramanian , Minh Van Ngo , Suzette K. Pangrle , Kashmir Sahota , Christopher F. Lyons
IPC分类号： H01L21302
CPC分类号： H01L21/76895 , H01L21/0276 , H01L21/76802 , H01L27/105 , H01L27/11526 , H01L27/11534
摘要： The present invention provides a method for manufacturing a semiconductor device with a bottom anti-reflective coating (BARC) that acts as an etch stop layer and does not need to be removed. In one embodiment, electrical devices are formed on a semiconductor substrate. Contacts are then formed for each electrical device and a partially UV transparent BARC is then deposited. An inter-layer dielectric (ILD) layer is then formed and then covered with photoresist. A top ARC (TARC) is then added and the photoresist is then photolithographically processed and subsequently developed. The TARC, ILD, and BARC layers are then selectively etched down to the device contacts forming local interconnects. The photoresist and TARC are later removed, but the BARC does not require removal due to its optical transparency.
摘要翻译：本发明提供一种用于制造半导体器件的方法，该半导体器件具有用作蚀刻停止层并且不需要去除的底部抗反射涂层（BARC）。在一个实施例中，电子器件形成在半导体衬底上。然后为每个电气设备形成触点，然后沉积部分UV透明的BARC。然后形成层间电介质（ILD）层，然后用光致抗蚀剂覆盖。然后加入顶部ARC（TARC），然后对光致抗蚀剂进行光刻处理并随后显影。然后将TARC，ILD和BARC层选择性地刻蚀成形成局部互连的器件触点。光致抗蚀剂和TARC随后被去除，但由于其光学透明性，BARC不需要去除。

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