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1. 发明授权

US06329718B1 Method for reducing stress-induced voids for 0.25m&mgr; and smaller semiconductor chip technology by annealing interconnect lines and using low bias voltage and low interlayer dielectric deposition rate and semiconductor chip made thereby 失效
标题翻译：通过退火互连线和使用低偏压和低层间电介质沉积速率减少应力诱发的0.25μm及更小的半导体芯片技术的空穴的方法，由此制成半导体芯片
公开(公告)号：US06329718B1
公开(公告)日：2001-12-11
申请号：US09105775
申请日：1998-06-26
申请人： Minh Van Ngo , Paul R. Besser , Matthew Buynoski , John Caffall , Nick MacCrae , Richard J. Huang , Khanh Tran
发明人： Minh Van Ngo , Paul R. Besser , Matthew Buynoski , John Caffall , Nick MacCrae , Richard J. Huang , Khanh Tran
IPC分类号： H01L2348
CPC分类号： H01L21/7685 , H01L21/76837 , H01L21/76858 , H01L21/76885 , H01L23/53223 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： A method for making 0.25 micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the contraction being absorbed by the aluminum. Because the alloy is reacted prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation in the interconnect lines is reduced. The likelihood of undesirable void formation is still further reduced during the subsequent ILD gapfill deposition process by using relatively low bias power to reduce vapor deposition temperature, and by using relatively low source gas deposition flow rates to reduce flow-induced compressive stress on the interconnect lines during ILD formation.
摘要翻译：用于制造0.25微米半导体芯片的方法包括在线之间沉积层间电介质（ILD）之前退火金属互连线。在退火期间，形成铝和钛的合金，其随后容积收缩，收缩被铝吸收。因为合金在ILD沉积之前反应，所以当铝试图吸收合金的收缩时，铝不受ILD的约束。因此，互连线中不希望的空隙形成的可能性降低。在随后的ILD间隙填充沉积过程中，通过使用相对低的偏置功率来降低气相沉积温度，并且通过使用相对较低的源气体沉积流速来减少互连线上的流动引起的压缩应力，仍然进一步降低了不希望的空隙形成的可能性在ILD形成期间。

2. 发明授权

US06492258B1 METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25-&mgr;M AND SMALLER SEMICONDUCTOR CHIP TECHNOLOGY BY ANNEALING INTERCONNECT LINES AND USING LOW BIAS VOLTAGE AND LOW INTERLAYER DIELECTRIC DEPOSITION RATE AND SEMICONDUCTOR CHIP MADE THEREBY 有权
标题翻译：用于通过退火互连线和使用低偏置电压和低中间层介电沉积速率和半导体芯片制造来减少0.25微米和小型半导体芯片技术的应力诱发电位的方法
公开(公告)号：US06492258B1
公开(公告)日：2002-12-10
申请号：US09881831
申请日：2001-06-14
申请人： Minh Van Ngo , Paul R. Besser , Matthew Buynoski , John Caffall , Nick Maccrae , Richard J. Huang , Khanh Tran
发明人： Minh Van Ngo , Paul R. Besser , Matthew Buynoski , John Caffall , Nick Maccrae , Richard J. Huang , Khanh Tran
IPC分类号： H01L214763
CPC分类号： H01L21/7685 , H01L21/76837 , H01L21/76858 , H01L21/76885 , H01L23/53223 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： A method for making 0.25-micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the contraction being absorbed by the aluminum. Because the alloy is reacted prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation. in the interconnect lines is reduced. The likelihood of undesirable void formation is still further reduced during the subsequent ILD gapfill deposition process by using relatively low bias power to reduce vapor deposition temperature. and by using relatively low source gas deposition flow rates to reduce flow-induced compressive stress on the interconnect lines during ILD formation.
摘要翻译：制造0.25微米半导体芯片的方法包括在线之间沉积层间电介质（ILD）之前退火金属互连线。在退火期间，形成铝和钛的合金，其随后容积收缩，铝的收缩被铝吸收。因为合金在ILD沉积之前反应，所以当铝试图吸收合金的收缩时，铝不受ILD的约束。因此，形成不希望的空隙的可能性。在互连线路中减少。在随后的ILD间隙填充沉积过程中，通过使用相对低的偏压功率来降低气相沉积温度，仍然进一步降低了不希望的空隙形成的可能性。并且通过使用相对低的源气体沉积流速来减少在ILD形成期间在互连线上的流动引起的压缩应力。

3. 发明授权

US06281584B1 Integrated circuit with improved adhesion between interfaces of conductive and dielectric surfaces 有权
标题翻译：集成电路，具有改善导电和电介质表面界面之间的粘附性
公开(公告)号：US06281584B1
公开(公告)日：2001-08-28
申请号：US09373482
申请日：1999-08-12
申请人： Minh Van Ngo , Richard J. Huang , Guarionex Morales
发明人： Minh Van Ngo , Richard J. Huang , Guarionex Morales
IPC分类号： H01L2348
CPC分类号： H01L21/31629 , H01L21/76801 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for using low dielectric SiOF in a process to manufacture semiconductor products, comprising the steps of obtaining a layer of SiOF, and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing ammonia. It is further preferred that the treated surface be passivated by a nitrite plasma. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielectric layer includes a first region at one edge thereof which is depleted of fluorine to a predetermined depth.
摘要翻译：一种在制造半导体产品的方法中使用低电介质SiOF的方法，包括以下步骤：获得SiOF层，并从SiOF层的表面上消耗氟。在优选的实施方案中，耗尽步骤包括用含有氨的等离子体处理SiOF层的表面的步骤。进一步优选的是，经过处理的表面被亚硝酸盐等离子体钝化。本发明还包括半导体芯片，其包括具有至少第一和第二层的集成电路，以及设置在层之间的SiOF的半导体层，其中SiOF电介质层包括其一个边缘处的第一区域，该第一区域耗尽氟到预定深度。

4. 发明授权

US06444593B1 Surface treatment of low-K SiOF to prevent metal interaction 有权
标题翻译：表面处理低K SiOF以防止金属相互作用
公开(公告)号：US06444593B1
公开(公告)日：2002-09-03
申请号：US09373483
申请日：1999-08-12
申请人： Minh Van Ngo , Richard J. Huang , Guarionex Morales
发明人： Minh Van Ngo , Richard J. Huang , Guarionex Morales
IPC分类号： H01L21425
CPC分类号： H01L21/31629 , H01L21/02131 , H01L21/02274 , H01L21/02332 , H01L21/0234 , H01L21/02362 , H01L21/76801 , H01L21/76807 , H01L21/76814 , H01L21/76826 , H01L21/76831 , H01L21/76832 , H01L21/76834 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for using low dielectric SiOF in a process to manufacture semiconductor products, comprising the steps of obtaining a layer of SiOF, and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing ammonia. It is further preferred that the treated surface be passivated by a nitrite plasma. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielectric layer includes a first region at one edge thereof which depleted of fluorine to a predetermined depth.
摘要翻译：一种在制造半导体产品的方法中使用低电介质SiOF的方法，包括以下步骤：获得SiOF层，并从SiOF层的表面上消耗氟。在优选的实施方案中，耗尽步骤包括用含有氨的等离子体处理SiOF层的表面的步骤。进一步优选的是，经过处理的表面被亚硝酸盐等离子体钝化。本发明还包括半导体芯片，其包括具有至少第一和第二层的集成电路，以及设置在层之间的SiOF的半导体层，其中所述SiOF电介质层包括其一个边缘处的第一区域，所述第一区域耗尽氟至预定深度。

5. 发明授权

US06596631B1 Method of forming copper interconnect capping layers with improved interface and adhesion 有权
标题翻译：形成具有改善界面和粘合性的铜互连封盖层的方法
公开(公告)号：US06596631B1
公开(公告)日：2003-07-22
申请号：US09626455
申请日：2000-07-26
申请人： Minh Van Ngo , Hartmut Ruelke , Lothar Mergili , Joerg Hohage , Lu You , Robert A. Huertas , Richard J. Huang
发明人： Minh Van Ngo , Hartmut Ruelke , Lothar Mergili , Joerg Hohage , Lu You , Robert A. Huertas , Richard J. Huang
IPC分类号： H01L244
CPC分类号： H01L21/76883 , H01L21/76834 , Y10S438/913
摘要： The integrity of the interface and adhesion between a barrier or capping layer and a Cu or Cu alloy interconnect member is significantly enhanced by delaying and/or slowly ramping up the introduction of silane to deposit a silicon nitride capping layer after treating the exposed planarized surface of the Cu or Cu alloy with an ammonia-containing plasma. Other embodiments include purging the reaction chamber with nitrogen at elevated temperature to remove residual gases prior to introducing the wafer for plasma treatment.
摘要翻译：通过在处理暴露的平坦化表面之后延迟和/或缓慢地升高硅烷的引入以沉积氮化硅覆盖层来显着增强界面的完整性和阻挡层或覆盖层与Cu或Cu合金互连构件之间的粘合性具有含氨等离子体的Cu或Cu合金。其他实施方案包括在升高的温度下用氮气吹扫反应室以在引入用于等离子体处理的晶片之前去除残留气体。

6. 发明授权

US06472336B1 Forming an encapsulating layer after deposition of a dielectric comprised of corrosive material 有权
标题翻译：在沉积由腐蚀性材料构成的电介质之后形成封装层
公开(公告)号：US06472336B1
公开(公告)日：2002-10-29
申请号：US09511585
申请日：2000-02-23
申请人： Suzette K. Pangrle , Minh Van Ngo , Richard J. Huang
发明人： Suzette K. Pangrle , Minh Van Ngo , Richard J. Huang
IPC分类号： H01L2131
CPC分类号： H01L21/76801 , C23C16/401 , H01L21/31629 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Insulating material is formed to surround interconnect structures of an integrated circuit. A first semiconductor wafer is placed in a reaction chamber for forming the insulating material surrounding the interconnect structures of the integrated circuit on the first semiconductor wafer. A corrosive dielectric material having low dielectric constant is deposited to surround the interconnect structures, and the corrosive dielectric material fills any gaps between the interconnect structures. Deposition of the corrosive dielectric material is performed within the reaction chamber, and the corrosive dielectric material is deposited on the reaction chamber during deposition of the corrosive dielectric material on the first semiconductor wafer. An encapsulating layer is formed over the corrosive dielectric material on the first semiconductor wafer and on the reaction chamber to prevent contact of the corrosive dielectric material to any exposed structure of a second semiconductor wafer to be subsequently placed into the reaction chamber when such an exposed structure is reactive with the corrosive dielectric material.
摘要翻译：绝缘材料形成为围绕集成电路的互连结构。将第一半导体晶片放置在用于形成围绕第一半导体晶片上的集成电路的互连结构的绝缘材料的反应室中。沉积具有低介电常数的腐蚀介电材料以包围互连结构，并且腐蚀介电材料填充互连结构之间的任何间隙。在反应室内进行腐蚀性电介质材料的沉积，并且在第一半导体晶片上沉积腐蚀性电介质材料期间，腐蚀性电介质材料沉积在反应室上。在第一半导体晶片上和反应室上的腐蚀介质材料上形成封装层，以防止腐蚀性电介质材料与任何暴露的第二半导体晶片的结构接触，随后将其放置在反应室中，与腐蚀性介电材料反应。

7. 发明授权

US6093635A High integrity borderless vias with HSQ gap filled patterned conductive layers 失效
标题翻译：高完整性无边界通孔与HSQ间隙填充图案导电层
公开(公告)号：US6093635A
公开(公告)日：2000-07-25
申请号：US993124
申请日：1997-12-18
申请人： Khanh Tran , Richard J. Huang , Simon S. Chan , Lu You
发明人： Khanh Tran , Richard J. Huang , Simon S. Chan , Lu You
IPC分类号： H01L21/3105 , H01L21/768 , H01L23/522 , H01L21/4763
CPC分类号： H01L21/3105 , H01L21/76814 , H01L21/76826 , H01L21/76828 , Y10S438/958
摘要： Borderless vias are formed in electrical connection with a lower metal feature of a metal pattern gap filled with HSQ. Heat treatment in an inert atmosphere is conducted before filling the through-hole to outgas water absorbed during solvent cleaning of the through-hole, thereby reducing via void formation and improving via integrity.
摘要翻译：无边界通孔形成为与填充有HSQ的金属图案间隙的下部金属特征电连接。在填充通孔之前，在惰性气氛中进行热处理，以排出在通孔的溶剂清洗期间吸收的水，从而通过空隙形成和通过完整性改善。

8. 发明授权

US6030891A Vacuum baked HSQ gap fill layer for high integrity borderless vias 失效
标题翻译：真空烘烤HSQ间隙填充层，用于高完整性无边界通孔
公开(公告)号：US6030891A
公开(公告)日：2000-02-29
申请号：US993052
申请日：1997-12-18
申请人： Khanh Tran , Richard J. Huang , Guarionex Morales
发明人： Khanh Tran , Richard J. Huang , Guarionex Morales
IPC分类号： H01L21/3105 , H01L21/312 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76852 , H01L21/02134 , H01L21/02164 , H01L21/022 , H01L21/02282 , H01L21/3124 , H01L21/76814 , H01L21/76826 , H01L21/76843 , H01L21/31058 , Y10S438/958
摘要： Borderless vias are formed in electrical connection with a lower metal feature of a metal patterned later gap filled with HSQ. Vacuum baking is conducted before filling the through-hole to outgas water absorbed during solvent cleaning, thereby reducing void formation and improving via integrity. Embodiments include vacuum baking at a temperature of about 300.degree. C. to about 400.degree. C., for about 45 seconds to about 2 minutes, at a pressure of no greater than about 10.sup.-6 Torr, preferably in the same tool employed for depositing the barrier layer in filling the through-hole.
摘要翻译：无边界通孔形成为与填充有HSQ的金属图案化的后续间隙的下部金属特征电连接。在填充通孔之前进行真空烘烤以排出在溶剂清洗期间吸收的水，从而减少空隙形成并改进通过完整性。实施方案包括在约300℃至约400℃的温度下，在不大于约10 -6乇的压力下进行约45秒至约2分钟的真空烘烤，优选在用于沉积的相同工具中进行真空烘烤阻挡层填充通孔。

9. 发明申请

US20120007221A1 MASK FOR FORMING INTEGRATED CIRCUIT 有权
标题翻译：形成集成电路的掩模
公开(公告)号：US20120007221A1
公开(公告)日：2012-01-12
申请号：US13241810
申请日：2011-09-23
申请人： Richard J. Huang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Richard C. Nguyen , Cyrus E. Tabery , Lu You
发明人： Richard J. Huang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Richard C. Nguyen , Cyrus E. Tabery , Lu You
IPC分类号： H01L29/66 , C23F1/00
CPC分类号： H01L21/28123 , H01L21/0332 , H01L21/28035 , H01L21/32139 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an integrated circuit includes providing a buffer layer comprising a dielectric material above a layer of conductive material and providing a layer of mask material above the buffer layer. The mask material comprises amorphous carbon. The method also includes removing a portion of the buffer layer and the layer of mask material to form a mask. A feature is formed in the layer of conductive material according to the mask.
摘要翻译：形成集成电路的方法包括在导电材料层之上提供包括电介质材料的缓冲层，并在缓冲层上方提供一层掩模材料。掩模材料包括无定形碳。该方法还包括去除缓冲层的一部分和掩模材料层以形成掩模。根据掩模在导电材料层中形成特征。

10. 发明授权

US07521304B1 Method for forming integrated circuit 失效
标题翻译：集成电路形成方法
公开(公告)号：US07521304B1
公开(公告)日：2009-04-21
申请号：US10230775
申请日：2002-08-29
申请人： Richard J. Huang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Richard C. Nguyen , Cyrus E. Tabery , Lu You
发明人： Richard J. Huang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Richard C. Nguyen , Cyrus E. Tabery , Lu You
IPC分类号： H01L21/336
CPC分类号： H01L21/28123 , H01L21/0332 , H01L21/28035 , H01L21/32139 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an integrated circuit includes providing a buffer layer comprising a dielectric material above a layer of conductive material and providing a layer of mask material above the buffer layer. The mask material comprises amorphous carbon. The method also includes removing a portion of the buffer layer and the layer of mask material to form a mask. A feature is formed in the layer of conductive material according to the mask.
摘要翻译：形成集成电路的方法包括在导电材料层之上提供包括电介质材料的缓冲层，并在缓冲层上方提供一层掩模材料。掩模材料包括无定形碳。该方法还包括去除缓冲层的一部分和掩模材料层以形成掩模。根据掩模在导电材料层中形成特征。

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