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    • 4. 发明授权
    • Semiconductor device comprising copper interconnects with reduced in-line copper diffusion
    • 包括具有减少的在线铜扩散的铜互连的半导体器件
    • US06472755B1
    • 2002-10-29
    • US09688928
    • 2000-10-17
    • Minh Van NgoTakeshi Nogami
    • Minh Van NgoTakeshi Nogami
    • H01L2348
    • H01L23/53238H01L21/76826H01L21/76829H01L21/76834H01L21/76883H01L23/53233H01L2924/0002H01L2924/00
    • Cu diffusion between Cu and Cu alloy interconnect members, e.g., lines, in a silicon oxide inter-layer dielectric is avoided or substantially reduced by converting an upper portion of the silicon oxide inter-layer dielectric between neighboring lines to silicon oxynitride and then depositing a capping layer. Embodiments include filling damascene trenches in a silicon oxide inter-layer dielectric with Cu or a Cu alloy, CMP to effect planarization such that the upper surfaces of the lines are substantially coplanar with the upper surface of the inter-layer dielectric and treating the exposed surfaces with a high strength ammonia plasma to ion bombard the exposed inter line silicon oxide with nitrogen atoms, thereby converting the upper portion to silicon oxynitride, while simultaneously removing or substantially reducing surface oxides on the lines. A silicon nitride capping layer is then deposited.
    • 通过将相邻线路之间的氧化硅层间电介质的上部部分转换为氮氧化硅,然后沉积氧化硅层,从而避免或基本上减少氧化硅层间电介质中Cu和Cu合金互连构件(例如线)之间的Cu扩散 盖层 实施例包括用Cu或Cu合金填充氧化硅层间电介质中的镶嵌沟槽CMP,以实现平面化,使得线的上表面与层间电介质的上表面基本上共面并且处理暴露表面 用高强度氨等离子体离子轰击具有氮原子的暴露的线间氧化硅,从而将上部转化为氮氧化硅,同时除去或显着还原线上的表面氧化物。 然后沉积氮化硅覆盖层。
    • 5. 发明授权
    • Method of reducing in-line copper diffusion
    • 减少在线铜扩散的方法
    • US06335283B1
    • 2002-01-01
    • US09477719
    • 2000-01-05
    • Minh Van NgoTakeshi Nogami
    • Minh Van NgoTakeshi Nogami
    • H01L2144
    • H01L21/76834H01L21/76826H01L21/76829H01L21/76883
    • Cu diffusion between Cu and Cu alloy interconnect members, e.g., lines, in a silicon oxide inter-layer dielectric is avoided or substantially reduced by converting an upper portion of the silicon oxide inter-layer dielectric between neighboring lines to silicon oxynitride and then depositing a capping layer. Embodiments include filling damascene trenches in a silicon oxide inter-layer dielectric with Cu or a Cu alloy, CMP to effect planarization such that the upper surfaces of the lines are substantially coplanar with the upper surface of the inter-layer dielectric and treating the exposed surfaces with a nitrogen plasma of sufficient strength to ion bombard the exposed inter line silicon oxide with nitrogen, thereby converting the upper portion to silicon oxynitride, while simultaneously removing or substantially reducing surface oxides on the lines. A silicon nitride capping layer is then deposited.
    • 通过将相邻线路之间的氧化硅层间电介质的上部部分转换为氮氧化硅,然后沉积氧化硅层,从而避免或基本上减少氧化硅层间电介质中Cu和Cu合金互连构件(例如线)之间的Cu扩散 盖层 实施例包括用Cu或Cu合金填充氧化硅层间电介质中的镶嵌沟槽CMP,以实现平面化,使得线的上表面与层间电介质的上表面基本上共面并且处理暴露表面 具有足够强度的氮等离子体用氮气轰击暴露的线间氧化硅,从而将上部部分转化为氮氧化硅,同时除去或基本上还原管线上的表面氧化物。 然后沉积氮化硅覆盖层。
    • 8. 发明授权
    • Tungsten plug formation
    • 钨塞形成
    • US06235632B1
    • 2001-05-22
    • US09006495
    • 1998-01-13
    • Takeshi NogamiGuarionex MoralesMinh Van Ngo
    • Takeshi NogamiGuarionex MoralesMinh Van Ngo
    • H01L2144
    • H01L21/76864H01L21/76841H01L21/76843H01L21/76855H01L21/76877H01L21/76895
    • In a preferred embodiment, there is disclosed a method of forming a tungsten plug at the via level. A metal line is formed in a top portion of a first insulating layer. A second insulating layer is formed on the first insulating layer and over an exposed surface of the metal line. An etching process is applied to a region of the second insulating layer formed over the exposed surface of the metal line to create a contact hole within the region. The metal line is exposed at the region. A tungsten nitride thin film is deposited over the second insulating layer and the exposed metal line. A blanket tungsten thin film is deposited to fill the contact hole and to form a planar layer successively to the depositing of the tungsten nitride thin film. The tungsten nitride thin film and the blanket tungsten thin film are chemically mechanically polished until the upper surface of the second insulating layer is exposed.
    • 在优选实施例中,公开了一种在通孔级形成钨丝塞的方法。 金属线形成在第一绝缘层的顶部。 在第一绝缘层上和金属线的暴露表面上形成第二绝缘层。 对形成在金属线的暴露表面上的第二绝缘层的区域施加蚀刻处理,以在该区域内形成接触孔。 金属线暴露在该地区。 在第二绝缘层和暴露的金属线上沉积氮化钨薄膜。 沉积覆盖的钨薄膜以填充接触孔并且连续地形成平坦层以沉积氮化钨薄膜。 化学机械抛光氮化钨薄膜和覆盖钨薄膜,直到第二绝缘层的上表面露出。
    • 10. 发明授权
    • Method of making a semiconductor device comprising copper interconnects
with reduced in-line copper diffusion
    • 制造具有减少的在线铜扩散的铜互连的半导体器件的方法
    • US6146988A
    • 2000-11-14
    • US477820
    • 2000-01-05
    • Minh Van NgoTakeshi Nogami
    • Minh Van NgoTakeshi Nogami
    • H01L21/768H01L21/4763
    • H01L21/76834H01L21/76826H01L21/76829H01L21/76883
    • Cu diffusion between Cu and Cu alloy interconnect members, e.g., lines, in a silicon oxide inter-layer dielectric is avoided or substantially reduced by converting an upper portion of the silicon oxide inter-layer dielectric between neighboring lines to silicon oxynitride and then depositing a capping layer. Embodiments include filling damascene trenches in a silicon oxide inter-layer dielectric with Cu or a Cu alloy, CMP to effect planarization such that the upper surfaces of the lines are substantially coplanar with the upper surface of the inter-layer dielectric and treating the exposed surfaces with a high strength ammonia plasma to ion bombard the exposed inter line silicon oxide with nitrogen atoms, thereby converting the upper portion to silicon oxynitride, while simultaneously removing or substantially reducing surface oxides on the lines. A silicon nitride capping layer is then deposited.
    • 通过将相邻线路之间的氧化硅层间电介质的上部部分转换为氮氧化硅,然后沉积氧化硅层,从而避免或基本上减少氧化硅层间电介质中Cu和Cu合金互连构件(例如线)之间的Cu扩散 盖层 实施例包括用Cu或Cu合金填充氧化硅层间电介质中的镶嵌沟槽CMP,以实现平面化,使得线的上表面与层间电介质的上表面基本上共面并且处理暴露表面 用高强度氨等离子体离子轰击具有氮原子的暴露的线间氧化硅,从而将上部转化为氮氧化硅,同时除去或显着还原线上的表面氧化物。 然后沉积氮化硅覆盖层。