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1. 发明授权

US06459155B1 Damascene processing employing low Si-SiON etch stop layer/arc 有权
标题翻译：使用低Si-SiON蚀刻停止层/电弧的镶嵌加工
公开(公告)号：US06459155B1
公开(公告)日：2002-10-01
申请号：US09729528
申请日：2000-12-05
申请人： Ramkumar Subramanian , Dawn M. Hopper , Minh Van Ngo
发明人： Ramkumar Subramanian , Dawn M. Hopper , Minh Van Ngo
IPC分类号： H01L214763
CPC分类号： H01L21/76829 , H01L21/0276 , H01L21/0332 , H01L21/76807
摘要： The dimensional accuracy of trench formation and, hence, metal line width, in damascene technology is improved by employing a low Si—SiON etch stop layer/ARC with reduced etch selectivity with respect to the overlying dielectric material but having a reduced extinction coefficient (k). Embodiments include via first-trench last dual damascene techniques employing a low Si—SiON middle etch stop layer/ARC having an extinction coefficient of about −0.3 to about −0.6, e.g., about −0.35, with reduced silicon and increased oxygen vis-à-vis a SiON etch stop layer having an extinction coefficient of about −1.1. Embodiments also include removing about 60% to about 90% of the low Si—SiON etch stop layer/ARC during trench formation, thereby reducing capacitance.
摘要翻译：通过使用低Si-SiON蚀刻停止层/ ARC，相对于上覆电介质材料具有降低的蚀刻选择性但具有降低的消光系数（k（k）），改善了镶嵌技术中沟槽形成的尺寸精度以及因此金属线宽度）。实施例包括通过第一沟槽最后的双镶嵌技术，其使用具有约-0.3至约-0.6，例如约-0.35的消光系数的低Si-SiON中间蚀刻停止层/ ARC，其中还原的硅和增加的氧相对于 - 具有约-1.1的消光系数的SiON蚀刻停止层。实施例还包括在沟槽形成期间去除约60％至约90％的低Si-SiON蚀刻停止层/ ARC，从而降低电容。

2. 发明授权

US06576545B1 Semiconductor devices with dual nature capping/ARC layers on fluorine doped silica glass inter-layer dielectrics and method of forming capping/ARC layers 有权
标题翻译：在氟掺杂石英玻璃层间电介质上具有双重性质封装/ ARC层的半导体器件和形成封盖/ ARC层的方法
公开(公告)号：US06576545B1
公开(公告)日：2003-06-10
申请号：US09819987
申请日：2001-03-29
申请人： Dawn M. Hopper , Lu You , Minh Van Ngo
发明人： Dawn M. Hopper , Lu You , Minh Van Ngo
IPC分类号： H01L214763
CPC分类号： H01L21/76829 , H01L21/76807
摘要： Degradation of fluorine-doped silica glass low-k inter-layer dielectrics during fabrication is significantly reduced and resolution of submicron features is improved by the formation of dual nature capping/ARC layers on inter-layer dielectric films. The capping/ARC layer is formed in-situ on a fluorine-doped silica glass inter-layer dielectric. The in-situ formation of the capping/ARC layer provides a strongly adhered capping/ARC layer, formed with fewer processing steps than conventional capping and ARC layers.
摘要翻译：通过在层间电介质膜上形成双重性能覆盖/ ARC层，制造过程中氟掺杂二氧化硅玻璃低k层间电介质的退化显着降低，亚微米特征的分辨率得到改善。封盖/ ARC层在氟掺杂石英玻璃层间电介质上原位形成。封盖/ ARC层的原位形成提供了强烈粘附的封盖/ ARC层，其形成与传统封盖和ARC层相比较少的处理步骤。

3. 发明授权

US06713874B1 Semiconductor devices with dual nature capping/arc layers on organic-doped silica glass inter-layer dielectrics 有权
标题翻译：在有机掺杂的石英玻璃层间电介质上具有双重自然封盖/电弧层的半导体器件
公开(公告)号：US06713874B1
公开(公告)日：2004-03-30
申请号：US09817050
申请日：2001-03-27
申请人： Dawn M. Hopper , Lu You , Minh Van Ngo
发明人： Dawn M. Hopper , Lu You , Minh Van Ngo
IPC分类号： H01L2348
CPC分类号： H01L21/76801 , H01L21/76807 , H01L21/76832 , H01L23/3171 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： Degradation of organic-doped silica glass low-k inter-layer dielectrics during fabrication is significantly reduced and resolution of submicron features is improved by the formation of dual nature capping/ARC layers on inter-layer dielectric films. The capping/ARC layer is formed in-situ on the organic-doped silica glass inter-layer dielectric. The in-situ formation of the capping/ARC layer provides a strongly adhered capping/ARC layer, formed with fewer processing steps than conventional capping and ARC layers.
摘要翻译：通过在层间电介质膜上形成双重性质覆盖/ ARC层，在制造期间降低有机掺杂石英玻璃低k层间电介质的降解显着降低，并提高亚微米特征的分辨率。在有机掺杂的石英玻璃层间电介质上原位形成封盖/ ARC层。封盖/ ARC层的原位形成提供了强烈粘附的封盖/ ARC层，其形成与传统封盖和ARC层相比较少的处理步骤。

4. 发明授权

US06479898B1 Dielectric treatment in integrated circuit interconnects 有权
标题翻译：集成电路互连中的介质处理
公开(公告)号：US06479898B1
公开(公告)日：2002-11-12
申请号：US09760421
申请日：2001-01-11
申请人： Dawn M. Hopper , Minh Van Ngo , Joffre F. Bernard
发明人： Dawn M. Hopper , Minh Van Ngo , Joffre F. Bernard
IPC分类号： H01L23532
CPC分类号： H01L21/76846 , H01L21/32051 , H01L21/76802 , H01L21/76826 , H01L21/76843 , H01L21/76855 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein and a surface region of nitrogen. A barrier layer lines the channel opening and reacts with the nitrogen to form an improved metal nitride surfaced barrier layer. A conductor core fills the opening over the barrier layer.
摘要翻译：提供了具有半导体器件的半导体衬底的集成电路及其制造方法。形成在半导体衬底上的器件电介质层。器件电介质层上的沟道电介质层具有形成在其中的开口和氮的表面区域。阻挡层对通道开口进行排列并与氮反应以形成改进的金属氮化物表面的阻挡层。导体芯填充阻挡层上的开口。

5. 发明授权

US06803265B1 Liner for semiconductor memories and manufacturing method therefor 有权
标题翻译：半导体存储器用衬垫及其制造方法
公开(公告)号：US06803265B1
公开(公告)日：2004-10-12
申请号：US10109234
申请日：2002-03-27
申请人： Minh Van Ngo , Arvind Halliyal , Tazrien Kamal , Hidehiko Shiraiwa , Rinji Sugino , Dawn M. Hopper , Pei-Yuan Gao
发明人： Minh Van Ngo , Arvind Halliyal , Tazrien Kamal , Hidehiko Shiraiwa , Rinji Sugino , Dawn M. Hopper , Pei-Yuan Gao
IPC分类号： H01L21337
CPC分类号： H01L27/11568 , H01L23/26 , H01L27/115 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A manufacturing method for an integrated circuit memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer. First and second bitlines are implanted and a wordline layer is deposited. A hard mask layer is deposited over the wordline layer. A photoresist is deposited over the wordline layer and used to form a hard mask. The photoresist is removed. The wordline layer is processed using the hard mask to form a wordline and the hard mask is removed. A reduced hydrogen, ultra-violet block data retention liner covers the wordline and the charge-trapping dielectric layer. The reduced hydrogen levels reduce the charge loss compared to prior art. The surface of the liner is processed to block UV light before completing the integrated circuit.
摘要翻译：集成电路存储器的制造方法包括提供半导体衬底和沉积电荷俘获电介质层。植入第一和第二位线，并存放字线层。硬掩模层沉积在字线层上。光刻胶沉积在字线层上并用于形成硬掩模。去除光致抗蚀剂。使用硬掩模处理字线层以形成字线，并且去除硬掩模。减少的氢，紫外阻挡数据保持衬里覆盖字线和电荷捕获介电层。与现有技术相比，降低的氢含量降低了电荷损失。在完成集成电路之前，衬里的表面被处理以阻挡UV光。

6. 发明授权

US06653190B1 Flash memory with controlled wordline width 失效
标题翻译：具有受控字线宽度的闪存
公开(公告)号：US06653190B1
公开(公告)日：2003-11-25
申请号：US10023436
申请日：2001-12-15
申请人： Jean Y. Yang , Kouros Ghandehari , Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Dawn M. Hopper , Angela T. Hui , Scott A. Bell
发明人： Jean Y. Yang , Kouros Ghandehari , Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Dawn M. Hopper , Angela T. Hui , Scott A. Bell
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/115
摘要： A method of manufacturing for a MirrorBit® Flash memory includes depositing a charge-trapping material over a semiconductor substrate and implanting first and second bitlines in the semiconductor substrate. A wordline material is deposited over the charge-trapping dielectric material and a hard mask material deposited thereon. An anti-reflective coating (ARC) material is deposited on the hard mask material and a photoresist material is deposited on the ARC followed by processing the photoresist material and the ARC material to form a photomask of a patterned photoresist and a patterned ARC. The hard mask material is processed using the photomask to form a hard mask. The patterned photoresist is removed and then the patterned ARC without damaging the hard mask or the wordline material. The wordline material is processed using the hard mask to form a wordline and the hard mask is removed without damaging the wordline or the charge-trapping material.
摘要翻译：用于MirrorBit（闪存）闪存的制造方法包括在半导体衬底上沉积电荷捕获材料并在半导体衬底中注入第一和第二位线。字线材料沉积在电荷俘获电介质材料上并沉积在其上的硬掩模材料。将抗反射涂层（ARC）材料沉积在硬掩模材料上，并且将光致抗蚀剂材料沉积在ARC上，随后处理光致抗蚀剂材料和ARC材料以形成图案化光致抗蚀剂和图案化ARC的光掩模。使用光掩模处理硬掩模材料以形成硬掩模。去除图案化的光致抗蚀剂，然后去除图案化的ARC，而不损坏硬掩模或字线材料。使用硬掩模处理字线材料以形成字线，并且去除硬掩模而不损坏字线或电荷捕获材料。

7. 发明授权

US06576982B1 Use of sion for preventing copper contamination of dielectric layer 失效
标题翻译：使用硫化物防止介电层的铜污染
公开(公告)号：US06576982B1
公开(公告)日：2003-06-10
申请号：US09776746
申请日：2001-02-06
申请人： Lu You , Dawn M. Hopper , Minh Van Ngo
发明人： Lu You , Dawn M. Hopper , Minh Van Ngo
IPC分类号： H01L2358
CPC分类号： H01L21/76831 , H01L21/76802 , H01L21/76804 , H01L21/76813 , H01L21/76877 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and a via extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization layer. The first etch stop layer is disposed over the first diffusion barrier layer, and the dielectric layer is disposed over the first etch stop layer. The via can also have rounded corners. A sidewall diffusion barrier layer can be disposed on sidewalls of the via, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. The first etch stop layer can be formed from silicon oxynitride. A method of manufacturing the semiconductor device is also disclosed.
摘要翻译：半导体器件包括第一金属化层，第一扩散阻挡层，第一蚀刻停止层，介电层和延伸穿过介电层的通孔，第一蚀刻停止层和第一扩散阻挡层。第一扩散阻挡层设置在第一金属化层上。第一蚀刻停止层设置在第一扩散阻挡层上，并且电介质层设置在第一蚀刻停止层上。通孔也可以有圆角。侧壁扩散阻挡层可以设置在通孔的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。第一蚀刻停止层可以由氮氧化硅形成。还公开了制造半导体器件的方法。

8. 发明授权

US06388330B1 Low dielectric constant etch stop layers in integrated circuit interconnects 有权
标题翻译：集成电路互连中的低介电常数蚀刻停止层
公开(公告)号：US06388330B1
公开(公告)日：2002-05-14
申请号：US09776012
申请日：2001-02-01
申请人： Minh Van Ngo , Dawn M. Hopper , Robert A. Huertas , Terri J. Kitson
发明人： Minh Van Ngo , Dawn M. Hopper , Robert A. Huertas , Terri J. Kitson
IPC分类号： H01L2348
CPC分类号： H01L23/5222 , H01L21/76801 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and method of manufacture therefore is provided having a semiconductor substrate with a semiconductor device with a dielectric layer over the semiconductor substrate. A conductor core fills the opening in the dielectric layer. An etch stop layer with a dielectric constant below 5.5 is formed over the first dielectric layer and conductor core. A second dielectric layer over the etch stop layer has an opening provided to the conductor core. A second conductor core fills the second opening and is connected to the first conductor core.
摘要翻译：因此，提供了具有半导体衬底和半导体器件的集成电路和制造方法，所述半导体衬底具有半导体衬底上的介电层。导体芯填充电介质层中的开口。在第一介电层和导体芯上形成介电常数低于5.5的蚀刻停止层。蚀刻停止层上的第二电介质层具有提供给导体芯的开口。第二导体芯填充第二开口并连接到第一导体芯。

9. 发明授权

US06482755B1 HDP deposition hillock suppression method in integrated circuits 失效
标题翻译：集成电路中的HDP沉积小丘抑制方法
公开(公告)号：US06482755B1
公开(公告)日：2002-11-19
申请号：US09880513
申请日：2001-06-12
申请人： Minh Van Ngo , Dawn M. Hopper , Robert A. Huertas
发明人： Minh Van Ngo , Dawn M. Hopper , Robert A. Huertas
IPC分类号： H01L2131
CPC分类号： H01L21/76834 , H01L21/3212 , H01L21/76801 , H01L21/76883
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is formed over the semiconductor substrate has an opening formed therein. A barrier layer of titanium, tantalum, tungsten, or a nitride of the aforegoing lines the opening, and a copper or copper alloy conductor core fills the channel opening over the barrier layer. After planarization of the conductor core and the barrier layer, an ammonia, nitrogen hydride, or hydrogen plasma treatment is performed below 300° C. and above 3000 watts source power to reduce the residual oxide on the conductor core material. A silicon nitride capping layer is deposited by high density plasma (HDP) deposition with the source power between 2250 and 2750 watts and the bias power between 1800 and 2200 watts to suppress the formation of hillocks.
摘要翻译：提供了具有半导体器件的半导体衬底的集成电路及其制造方法。在半导体衬底上方形成有形成在其中的开口的电介质层。前述的钛，钽，钨或氮化物的阻挡层形成开口，铜或铜合金导体芯填充阻挡层上的通道开口。在导体芯和阻挡层平坦化之后，进行氨，氮化氢或氢等离子体处理，其在低于300℃和高于3000瓦的源功率下进行，以减少导体芯材上的残余氧化物。氮化硅覆盖层通过高功率等离子体（HDP）沉积沉积，源功率在2250和2750瓦之间，偏置功率在1800至2200瓦之间，以抑制形成小丘。

10. 发明授权

US06395644B1 Process for fabricating a semiconductor device using a silicon-rich silicon nitride ARC 有权
标题翻译：使用富硅氮化物ARC制造半导体器件的工艺
公开(公告)号：US06395644B1
公开(公告)日：2002-05-28
申请号：US09484606
申请日：2000-01-18
申请人： Dawn M. Hopper , Minh Van Ngo , David K. Foote
发明人： Dawn M. Hopper , Minh Van Ngo , David K. Foote
IPC分类号： H01L21302
CPC分类号： H01L21/3185 , H01L21/32139 , Y10S438/952
摘要： A process for fabricating a semiconductor device using an ARC layer includes the formation of a silicon-rich silicon nitride material to provide an anti-reflective layer over a electrically conductive or semiconductor surface. The silicon-rich silicon nitride material is plasma deposited to provide a material having a desired refractive index, thickness uniformity, and density. The process includes the formation of a device layer on a semiconductor substrate. The device layer includes at least a silicon layer and a silicon oxide layer. A silicon-rich silicon nitride layer is formed to overlie the device layer. The silicon-rich silicon nitride material can be selectively etched, such that the silicon material and the silicon oxide material in the underlying device layer are not substantially etched.
摘要翻译：使用ARC层制造半导体器件的方法包括形成富硅的氮化硅材料，以在导电或半导体表面上提供抗反射层。富硅氮化硅材料被等离子体沉积以提供具有期望的折射率，厚度均匀性和密度的材料。该方法包括在半导体衬底上形成器件层。器件层至少包括硅层和氧化硅层。形成富含硅的氮化硅层以覆盖器件层。可以选择性地蚀刻富硅的氮化硅材料，使得底层器件层中的硅材料和氧化硅材料基本上不被蚀刻。

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