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61. 发明授权

US08188781B1 Memory interface phase-shift circuitry to support multiple frequency ranges 有权
标题翻译：存储器接口相移电路，以支持多个频率范围
公开(公告)号：US08188781B1
公开(公告)日：2012-05-29
申请号：US11531263
申请日：2006-09-12
申请人： Andy L. Lee
发明人： Andy L. Lee
IPC分类号： H03H11/26
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/222 , G11C11/4076 , G11C11/4096 , H03K2005/00058
摘要： The present invention provides a phase shift circuit that supports multiple frequency ranges. The phase shift circuit receives a plurality of control bits and causes a phase shift in a received signal, the phase shift corresponding to a number of time steps, the number depending on the control bits, and the time step is selected from a plurality of different time steps based on a frequency range associated with the received signal.
摘要翻译：本发明提供一种支持多个频率范围的相移电路。相移电路接收多个控制位，并且在接收信号中产生相移，对应于时间步数的相移，取决于控制位的数量，并且时间步长是从多个不同的基于与接收信号相关联的频率范围的时间步长。

62. 发明申请

US20120039142A1 SCALEABLE LOOK-UP TABLE BASED MEMORY 有权
标题翻译：可扩展的基于表的记忆
公开(公告)号：US20120039142A1
公开(公告)日：2012-02-16
申请号：US13277871
申请日：2011-10-20
申请人： Philip Pan , Andy L. Lee , Lu Zhou , Aniket Kadkol
发明人： Philip Pan , Andy L. Lee , Lu Zhou , Aniket Kadkol
IPC分类号： G11C7/12 , G11C5/14
CPC分类号： G11C11/418 , G11C7/00 , G11C7/1045 , G11C7/1048 , G11C7/12 , G11C7/22 , G11C8/10 , G11C11/4094 , G11C11/413 , G11C11/419 , G11C29/12 , G11C2029/0409 , G11C2029/1204 , G11C2029/2602
摘要： An integrated circuit having a logic element that includes an array of storage elements convertibly functioning as either a configuration random access memory (CRAM) or a static random access memory (SRAM) is provided. The logic element includes first and second pairs of data paths having dedicated multiplexers. In one embodiment, the first and second pairs of data paths are multiplexed into bit lines of a row of the array. The logic element also includes a data path control block generating control signals for each of the dedicated multiplexers. The control signals determine whether the storage elements function as a CRAM or a SRAM. A method for selectively configuring a memory array between a CRAM mode and SRAM mode are provided.
摘要翻译：提供一种集成电路，其具有包括可转换地用作配置随机存取存储器（CRAM）或静态随机存取存储器（SRAM））的存储元件阵列的逻辑元件。逻辑元件包括具有专用复用器的第一和第二对数据路径。在一个实施例中，第一和第二对数据路径被复用到阵列行的位线。逻辑元件还包括数据路径控制块，其产生用于每个专用多路复用器的控制信号。控制信号确定存储元件是否用作CRAM或SRAM。提供了一种用于在CRAM模式和SRAM模式之间选择性地配置存储器阵列的方法。

63. 发明授权

US08030962B2 Configuration random access memory 有权
标题翻译：配置随机存取存储器
公开(公告)号：US08030962B2
公开(公告)日：2011-10-04
申请号：US12868575
申请日：2010-08-25
申请人： Irfan Rahim , Andy L. Lee , Myron Wai Wong , William Bradley Vest , Jeffrey T. Watt
发明人： Irfan Rahim , Andy L. Lee , Myron Wai Wong , William Bradley Vest , Jeffrey T. Watt
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , G11C11/401 , G11C11/404 , G11C14/00 , H03K19/1778
摘要： Integrated circuits such as programmable logic device integrated circuits are provided that have configuration random-access memory elements. The configuration random-access memory elements are loaded with configuration data to customize programmable logic on the integrated circuits. Each memory element has a capacitor that stores data for that memory element. A pair of cross-coupled inverters are connected to the capacitor. The inverters ensure that the memory elements produce output control signals with voltages than range from one power supply rail to another. Each configuration random-access memory element may have a clear transistor. The capacitor may be formed in a dielectric layer that lies above the transistors of the inverters, the address transistor, and the clear transistor. The inverters may be powered with an elevated power supply voltage.
摘要翻译：提供了诸如可编程逻辑器件集成电路的集成电路，其具有配置随机存取存储器元件。配置随机存取存储器元件装载有配置数据以在集成电路上定制可编程逻辑。每个存储器元件具有存储该存储器元件的数据的电容器。一对交叉耦合的反相器连接到电容器。逆变器确保存储元件产生的输出控制信号的电压低于从一个电源轨到另一个电源的范围。每个配置随机存取存储器元件可以具有透明晶体管。电容器可以形成在位于反相器，地址晶体管和透明晶体管的晶体管之上的电介质层中。逆变器可以用升高的电源电压供电。

64. 发明授权

US07969215B1 High-performance memory interface circuit architecture 有权
标题翻译：高性能存储器接口电路架构
公开(公告)号：US07969215B1
公开(公告)日：2011-06-28
申请号：US12467681
申请日：2009-05-18
申请人： Joseph Huang , Chiakang Sung , Philip Pan , Yan Chong , Andy L. Lee , Brian D. Johnson
发明人： Joseph Huang , Chiakang Sung , Philip Pan , Yan Chong , Andy L. Lee , Brian D. Johnson
IPC分类号： H03L7/00
CPC分类号： H03L7/0812 , G11C7/22 , G11C7/222 , H03L7/0805
摘要： A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.
摘要翻译：可编程存储器接口电路包括可编程DLL延迟链，相位偏移控制电路和可编程DQS延迟链。 DLL延迟链使用一组串行连接的延迟单元，可编程开关，相位检测器和数字计数器来产生粗略的相移控制设置。然后，粗略的相移控制设置用于预先计算静态残留相移控制设置或生成动态残留相移控制设置，其中一个由相位偏移控制电路选择以被加到或从粗略相移控制设置，以产生精细的相移控制设置。粗调和精细相移控制设置一致地产生相位延迟的DQS信号，其中心对准其相关联的DQ信号。

65. 发明授权

US07911240B1 Clock switch-over circuits and methods 有权
标题翻译：时钟切换电路和方法
公开(公告)号：US07911240B1
公开(公告)日：2011-03-22
申请号：US11750293
申请日：2007-05-17
申请人： Gary Lai , Andy L. Lee , Ryan Fung , Vaughn Betz , Marcel A. LeBlanc
发明人： Gary Lai , Andy L. Lee , Ryan Fung , Vaughn Betz , Marcel A. LeBlanc
IPC分类号： G06F1/08
CPC分类号： G06F1/10
摘要： Clock switch-over circuits and methods provide clock signals to clock routing networks. According to one embodiment, a multiplexer selects between a first clock signal and a second clock signal in response to a switch select signal received from a control circuit. A storage circuit stores an enable signal in response to an output clock signal of the multiplexer. A logic circuit transmits the output clock signal of the multiplexer to a clock routing network in response to the enable signal from the storage circuit. At least one signal is transmitted from the clock switch-over circuit to the control circuit.
摘要翻译：时钟切换电路和方法为时钟路由网络提供时钟信号。根据一个实施例，多路复用器响应于从控制电路接收的开关选择信号在第一时钟信号和第二时钟信号之间进行选择。存储电路响应于多路复用器的输出时钟信号而存储使能信号。响应于来自存储电路的使能信号，逻辑电路将多路复用器的输出时钟信号传输到时钟路由网络。至少一个信号从时钟切换电路发送到控制电路。

66. 发明授权

US07800405B2 Passgate structures for use in low-voltage applications 有权
标题翻译： Passgate结构用于低压应用
公开(公告)号：US07800405B2
公开(公告)日：2010-09-21
申请号：US12484665
申请日：2009-06-15
申请人： Andy L. Lee , Wanli Chang , Cameron McClintock , John E. Turner , Brian D. Johnson , Chiao Kai Hwang , Richard Yen-Hsiang Chang , Richard G. Cliff
发明人： Andy L. Lee , Wanli Chang , Cameron McClintock , John E. Turner , Brian D. Johnson , Chiao Kai Hwang , Richard Yen-Hsiang Chang , Richard G. Cliff
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K19/17736 , H03K17/063 , H03K19/177 , H03K19/1778
摘要： Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE-Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.
摘要翻译：提出了用于低压系统的增强型门控结构，其中Vt对单晶闸管通道通过的信号范围的影响减小。在一种布置中，通过应用较高的VGATE来提高通过NMOS通道传播的信号的VGATE-Vt极限; 在另一种布置中，Vt被降低。传统上使用单通道闸门的CMOS传动闸门的使用也被提出。

67. 发明授权

US07504855B1 Multiple data rate memory interface architecture 有权
标题翻译：多数据速率存储器接口架构
公开(公告)号：US07504855B1
公开(公告)日：2009-03-17
申请号：US11672438
申请日：2007-02-07
申请人： Andy L. Lee , Brian D. Johnson
发明人： Andy L. Lee , Brian D. Johnson
IPC分类号： H03K19/173 , G11C7/00
CPC分类号： G11C7/10 , H03K19/17744
摘要： The present invention provides a DQS bus for implementing high speed multiple-data-rate interface architectures in programmable logic devices. The DQS bus has a balanced tree structure between at least one data strobe circuit and a plurality of I/O register blocks.
摘要翻译：本发明提供了一种用于在可编程逻辑器件中实现高速多数据速率接口架构的DQS总线。 DQS总线在至少一个数据选通电路和多个I / O寄存器块之间具有平衡树结构。

68. 发明授权

US07432734B2 Versatile logic element and logic array block 有权
公开(公告)号：US07432734B2
公开(公告)日：2008-10-07
申请号：US11743625
申请日：2007-05-02
申请人： David M. Lewis , Paul Leventis , Andy L. Lee , Henry Kim , Bruce Pedersen , Chris Wysocki , Christopher F. Lane , Alexander Marquardt , Vikram Santurkar , Vaughn Betz
发明人： David M. Lewis , Paul Leventis , Andy L. Lee , Henry Kim , Bruce Pedersen , Chris Wysocki , Christopher F. Lane , Alexander Marquardt , Vikram Santurkar , Vaughn Betz
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K19/17764 , H03K19/1737 , H03K19/17728 , H03K19/17736
摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

69. 发明授权

US07112992B1 Configuration shift register 有权
标题翻译：配置移位寄存器
公开(公告)号：US07112992B1
公开(公告)日：2006-09-26
申请号：US11008080
申请日：2004-12-08
申请人： Mario Guzman , Chris Lane , Andy L. Lee , Ninh Ngo
发明人： Mario Guzman , Chris Lane , Andy L. Lee , Ninh Ngo
IPC分类号： H03K19/173
CPC分类号： H03K19/17752 , H03K19/1774 , H03K19/17744 , H03K19/17756
摘要： An electronic device comprises a first plurality of configuration elements connected as a shift register for programming a subset of the programmable functions of the electronic device. The subset of programmable functions may be reprogrammed by loading configuration data into the first plurality of configuration elements such that the subset of programmable functions may be reprogrammed without necessarily reprogramming other programmable functions of the electronic device.
摘要翻译：电子设备包括作为移位寄存器连接的第一多个配置元件，用于对电子设备的可编程功能的子集进行编程。可编程功能的子集可以通过将配置数据加载到第一多个配置元件中来重新编程，使得可编程功能的子集可以被重新编程，而不必重新编程电子设备的其他可编程功能。

70. 发明授权

US07010777B1 Shared lookup table enhancements for the efficient implementation of barrel shifters 失效
标题翻译：共享查找表增强了桶形移位器的有效实现
公开(公告)号：US07010777B1
公开(公告)日：2006-03-07
申请号：US10807360
申请日：2004-03-22
申请人： Michael Hutton , Andy L. Lee , Rahul Saini
发明人： Michael Hutton , Andy L. Lee , Rahul Saini
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , H03K19/1736 , H03K19/17728
摘要： Additional circuitry is provided over a shared-LUT logic circuit to allow functions of different input characteristics to share a logic element which was conventionally illegal. More restrictive circuitry may be provided over a shared-LUT logic circuit to allow functions with particular input characteristics.
摘要翻译：在共享LUT逻辑电路上提供附加电路，以允许不同输入特性的功能共享通常是非法的逻辑元件。可以在共享LUT逻辑电路上提供更多限制性电路以允许具有特定输入特性的功能。

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