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61. 发明授权

US09154188B2 RF identification device with near-field-coupled antenna 有权
标题翻译：具有近场耦合天线的RF识别装置
公开(公告)号：US09154188B2
公开(公告)日：2015-10-06
申请号：US12182893
申请日：2008-07-30
申请人： Alessandro Finocchiaro , Giovanni Girlando , Giuseppe Palmisano , Giuseppe Ferla , Alberto Pagani
发明人： Alessandro Finocchiaro , Giovanni Girlando , Giuseppe Palmisano , Giuseppe Ferla , Alberto Pagani
IPC分类号： G08B23/00 , H04B5/00 , H01L23/66 , H01L25/065 , H01L23/00
CPC分类号： H04B5/00 , H01L23/66 , H01L24/73 , H01L25/0655 , H01L25/0657 , H01L2223/6677 , H01L2224/48091 , H01L2225/06531 , H01L2924/10253 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H04B5/0031 , H04B5/0037 , H04B5/0081 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： An embodiment of a RF identification device is formed by a tag and by a reader. The tag is formed by a processing circuit and a first antenna, which has the function both of transmitting and of receiving data. The reader is formed by a control circuit and by a second antenna, which has the function both of transmitting and of receiving data. The processing circuit is formed by a resonance capacitor, a modulator, a rectifier circuit, a charge-pump circuit and a detection circuit. The antenna of the tag and the processing circuit are integrated in a single structure in completely monolithic form. The first antenna has terminals connected to the input of the rectifier circuit, the output of which is connected to the charge-pump circuit. The charge-pump circuit has an output connected to the detection circuit.
摘要翻译： RF识别装置的实施例由标签和读取器形成。标签由具有发送和接收数据功能的处理电路和第一天线形成。读取器由控制电路和具有发送和接收数据功能的第二天线形成。处理电路由谐振电容器，调制器，整流电路，电荷泵电路和检测电路构成。标签和处理电路的天线以完全整体的形式集成在单个结构中。第一天线具有连接到整流电路的输入的端子，其输出端连接到电荷泵电路。电荷泵电路具有连接到检测电路的输出。

62. 发明授权

US08482085B2 Power MOS electronic device and corresponding realizing method 有权
公开(公告)号：US08482085B2
公开(公告)日：2013-07-09
申请号：US12967861
申请日：2010-12-14
申请人： Angelo Magri , Ferruccio Frisina , Giuseppe Ferla
发明人： Angelo Magri , Ferruccio Frisina , Giuseppe Ferla
IPC分类号： H01L27/088
CPC分类号： H01L29/7802 , H01L29/4238 , H01L29/4916 , H01L29/4933 , H01L29/4983
摘要： Power MOS device of the type comprising a plurality of elementary power MOS transistors having respective gate structures and comprising a gate oxide with double thickness having a thick central part and lateral portions of reduced thickness. Such device exhibiting gate structures comprising first gate conductive portions overlapped onto said lateral portions of reduced thickness to define, for the elementary MOS transistors, the gate electrodes, as well as a conductive structure or mesh. Such conductive structure comprising a plurality of second conductive portions overlapped onto the thick central part of gate oxide and interconnected to each other and to the first gate conductive portions by means of a plurality of conducive bridges.

63. 发明申请

US20060244059A1 Power MOS electronic device and corresponding realizing method 有权
公开(公告)号：US20060244059A1
公开(公告)日：2006-11-02
申请号：US11285741
申请日：2005-11-21
申请人： Angelo Magri , Ferruccio Frisina , Giuseppe Ferla
发明人： Angelo Magri , Ferruccio Frisina , Giuseppe Ferla
IPC分类号： H01L29/76
CPC分类号： H01L29/7802 , H01L29/4238 , H01L29/4916 , H01L29/4933 , H01L29/4983
摘要： Power MOS device of the type comprising a plurality of elementary power MOS transistors having respective gate structures and comprising a gate oxide with double thickness having a thick central part and lateral portions of reduced thickness. Such device exhibiting gate structures comprising first gate conductive portions overlapped onto said lateral portions of reduced thickness to define, for the elementary MOS transistors, the gate electrodes, as well as a conductive structure or mesh. Such conductive structure comprising a plurality of second conductive portions overlapped onto the thick central part of gate oxide and interconnected to each other and to the first gate conductive portions by means of a plurality of conducive bridges.

64. 发明申请

US20060220121A1 Switching-controlled power MOS electronic device 有权
公开(公告)号：US20060220121A1
公开(公告)日：2006-10-05
申请号：US11285759
申请日：2005-11-21
申请人： Ferruccio Frisina , Giuseppe Ferla , Angelo Magri , Antonio Grimaldi , Gaetano Bazzano
发明人： Ferruccio Frisina , Giuseppe Ferla , Angelo Magri , Antonio Grimaldi , Gaetano Bazzano
IPC分类号： H01L29/76
CPC分类号： H01L29/7802 , H01L29/4238 , H01L29/4916 , H01L29/4933 , H01L29/4983
摘要： Power electronic MOS device of the type comprising a plurality of elementary power MOS transistors and a gate structure comprising a plurality of conductive strips realized with a first conductive material such as polysilicon, a plurality of gate fingers or metallic tracks connected to a gate pad and at least a connection layer arranged in series to at least one of said conductive strip. Such gate structure comprising at least a plurality of independent islands formed on the upper surface of the conductive strips and suitably formed on the connection layers. Said islands being realized with at least one second conductive material such as silicide.

65. 发明申请

US20060071242A1 Vertical conduction power electronic device and corresponding realization method 有权
标题翻译：垂直传导功率电子器件及相应的实现方法
公开(公告)号：US20060071242A1
公开(公告)日：2006-04-06
申请号：US11235495
申请日：2005-09-26
申请人： Ferruccio Frisina , Giuseppe Ferla , Angelo Magri
发明人： Ferruccio Frisina , Giuseppe Ferla , Angelo Magri
IPC分类号： H01L29/768
CPC分类号： H01L29/66666 , H01L21/26586 , H01L29/0692 , H01L29/0696 , H01L29/0878 , H01L29/417 , H01L29/41708 , H01L29/41716 , H01L29/41741 , H01L29/41766 , H01L29/66128 , H01L29/66272 , H01L29/66333 , H01L29/66712 , H01L29/7322 , H01L29/7398 , H01L29/7809 , H01L29/8611
摘要： A vertical conduction electronic power device includes respective gate, source and drain areas, realized in an epitaxial layer arranged on a semiconductor substrate. The respective gate, source and drain metallizations may be realized by a first metallization level. The gate, source and drain terminals or pads may be realized by a second metallization level. The device is configured as a set of modular areas extending parallel to each other, each having a rectangular elongate source area perimetrically surrounded by a narrow gate area, and separated from each other by regions with the drain area extending parallel and connected at the opposite ends thereof to a second closed region with the drain area forming a device outer peripheral edge. A sinker structure extends perpendicularly to the substrate and may be formed by a grid of sinkers located below both the first parallel regions and the second closed region to favor a conductive channel for a current coming from the source area and directed towards the drain area across the substrate.
摘要翻译：垂直导电电子功率器件包括在布置在半导体衬底上的外延层中实现的相应的栅极，源极和漏极区域。相应的栅极，源极和漏极金属化可以通过第一金属化水平来实现。栅极，源极和漏极端子或焊盘可以通过第二金属化水平来实现。该装置被配置为一组彼此平行延伸的模块化区域，每个模块区域具有由狭窄的栅极区域周边围绕的矩形细长源区域，并且彼此分开，其中漏区域在相对端平行延伸并连接其具有形成装置外周边缘的第二封闭区域。沉降片结构垂直于衬底延伸，并且可以由位于第一平行区域和第二闭合区域下方的沉陷片形成，以便有助于来自源区域的电流的导电通道，并且引导通过漏极区域基质。

66. 发明授权

US06724009B2 Semiconductor integrated electronic device and corresponding manufacturing method 有权
标题翻译：半导体集成电子器件及相应的制造方法
公开(公告)号：US06724009B2
公开(公告)日：2004-04-20
申请号：US10199964
申请日：2002-07-18
申请人： Gianfranco Cerofolini , Giuseppe Ferla
发明人： Gianfranco Cerofolini , Giuseppe Ferla
IPC分类号： H01L3524
CPC分类号： H01L21/28167 , H01L29/51
摘要： A method of fabricating a MOS transistor with a controllable and modulatable conduction path through a dielectric gate oxide is disclosed, wherein the transistor structure comprises a dielectric oxide layer formed between two silicon plates, and wherein the silicon plates overhang the oxide layer all around to define an undercut having a substantially rectangular cross-sectional shape. The method comprises the steps of: chemically altering the surfaces of the silicon plates to have different functional groups provided in the undercut from those in the remainder of the surfaces; and selectively reacting the functional groups provided in the undercut with an organic molecule having a reversibly reducible center and a molecular length substantially equal to the width of the undercut, thereby to establish a covalent bond to each end of the organic molecule.
摘要翻译：公开了一种通过电介质栅极氧化物制造具有可控和可调制传导路径的MOS晶体管的方法，其中晶体管结构包括在两个硅板之间形成的电介质氧化物层，并且其中硅板全部悬垂在氧化物层周围以限定具有基本上矩形横截面形状的底切。该方法包括以下步骤：将硅板的表面化学改变成在底切中提供的不同的官能团与其余表面中的不同的官能团; 并且将底切中提供的官能团选择性地与具有可逆还原中心和分子长度基本上等于底切宽度的有机分子反应，从而与有机分子的每个末端建立共价键。

67. 发明授权

US06278329B1 Low-noise amplifier stage with matching network 有权
标题翻译：具有匹配网络的低噪声放大器级
公开(公告)号：US06278329B1
公开(公告)日：2001-08-21
申请号：US09466573
申请日：1999-12-21
申请人： Giuseppe Palmisano , Giuseppe Ferla , Giovanni Girlando
发明人： Giuseppe Palmisano , Giuseppe Ferla , Giovanni Girlando
IPC分类号： H03F304
CPC分类号： H03F1/22 , H03F1/565 , H03F2200/294 , H03F2200/372
摘要： An amplifier stage having a first and a second transistor connected in series to each other between a first and a second reference potential line. The first transistor has a control terminal connected to an input of the amplifier stage through a first inductor, a first terminal connected to the second reference potential line through a second inductor, and a third terminal connected to a first terminal of the second transistor. The second transistor has a second terminal forming an output of the amplifier stage, and connected to the first reference potential line through a load resistor. To improve the noise figure, a matching capacitor is connected between the control terminal and the first terminal of the first transistor.
摘要翻译：具有在第一和第二参考电位线之间彼此串联连接的第一和第二晶体管的放大器级。第一晶体管具有通过第一电感器连接到放大器级的输入的控制端子，通过第二电感器连接到第二参考电位线的第一端子和连接到第二晶体管的第一端子的第三端子。第二晶体管具有形成放大器级的输出的第二端子，并通过负载电阻器连接到第一参考电位线。为了提高噪声系数，在控制端子与第一晶体管的第一端子之间连接有匹配电容器。

68. 发明授权

US6140679A Zero thermal budget manufacturing process for MOS-technology power devices 失效
标题翻译：用于MOS技术功率器件的零热预算制造工艺
公开(公告)号：US6140679A
公开(公告)日：2000-10-31
申请号：US856109
申请日：1997-05-14
申请人： Giuseppe Ferla , Ferruccio Frisina
发明人： Giuseppe Ferla , Ferruccio Frisina
IPC分类号： H01L21/265 , H01L21/336 , H01L29/10 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66712 , H01L29/1095 , H01L21/26586
摘要： A zero thermal budget manufacturing process for a MOS-technology power device. The method comprises the steps of: forming a conductive insulated gate layer on a surface of a lightly doped semiconductor material layer of a first conductivity type; removing the insulated gate layer from selected portions of the semiconductor material layer surface; implanting a first dopant of a second conductivity type into the selected portions of the semiconductor material layer, the insulated gate layer acting as a mask and the first dopant of the first conductivity type being implanted in a dose and with an implantation energy suitable to obtain heavily doped regions substantially aligned with the edges of the insulated gate layer; implanting a second dopant of the second conductivity type along directions at prescribed angles with respect to a direction orthogonal to the semiconductor material layer surface, the insulated gate layer acting as a mask, the second dopant being implanted in a dose and with an implantation energy suitable to obtain lightly doped channel regions extending under the insulated gate layer; and implanting a third dopant of the first conductivity type into the heavily doped regions, to form source regions substantially aligned with the edges of the insulated gate layer.
摘要翻译：用于MOS技术功率器件的零热预算制造过程。该方法包括以下步骤：在第一导电类型的轻掺杂半导体材料层的表面上形成导电绝缘栅极层; 从半导体材料层表面的选定部分去除绝缘栅极层; 将第二导电类型的第一掺杂剂注入到半导体材料层的选定部分中，用作掩模的绝缘栅极层和以剂量注入的第一导电类型的第一掺杂剂和适于大量获得的注入能量掺杂区域基本上与绝缘栅极层的边缘对准; 沿相对于与半导体材料层表面正交的方向以规定角度的方向注入第二导电类型的第二掺杂剂，所述绝缘栅极层用作掩模，所述第二掺杂剂以适合的植入能量注入，以获得在绝缘栅极层下延伸的轻掺杂沟道区; 以及将第一导电类型的第三掺杂剂注入到重掺杂区域中，以形成基本上与绝缘栅极层的边缘对准的源极区域。

69. 发明授权

US5985721A Single feature size MOS technology power device 失效
公开(公告)号：US5985721A
公开(公告)日：1999-11-16
申请号：US933505
申请日：1997-09-18
申请人： Ferruccio Frisina , Angelo Magri , Giuseppe Ferla , Richard A. Blanchard
发明人： Ferruccio Frisina , Angelo Magri , Giuseppe Ferla , Richard A. Blanchard
IPC分类号： H01L29/74 , H01L21/331 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/749 , H01L29/78 , H01L21/336
CPC分类号： H01L29/66333 , H01L29/0696 , H01L29/1095 , H01L29/7802 , H01L29/0847
摘要： A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided. The MOS technology power device further includes a plurality of insulating material sidewall spacers disposed above the semiconductor material layer along elongated edges of each elongated window to seal the edges of each elongated window in the insulated gate layer from a source metal layer disposed over the insulated gate layer and the semiconductor material layer. The source metal layer contacts each body region and each source region through each elongated window along the length of the elongated body region.

70. 发明授权

US5981998A Single feature size MOS technology power device 失效
公开(公告)号：US5981998A
公开(公告)日：1999-11-09
申请号：US739465
申请日：1996-10-29
申请人： Ferruccio Frisina , Angelo Magri' , Giuseppe Ferla , Richard A. Blanchard
发明人： Ferruccio Frisina , Angelo Magri' , Giuseppe Ferla , Richard A. Blanchard
IPC分类号： H01L29/74 , H01L21/331 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/749 , H01L29/78 , H01L29/00
CPC分类号： H01L29/66333 , H01L29/0696 , H01L29/1095 , H01L29/7802 , H01L29/0847
摘要： A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided. The MOS technology power device further includes a plurality of insulating material sidewall spacers disposed above the semiconductor material layer along elongated edges of each elongated window to seal the edges of each elongated window in the insulated gate layer from a source metal layer disposed over the insulated gate layer and the semiconductor material layer. The source metal layer contacts each body region and each source region through each elongated window along the length of the elongated body region.

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