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61. 发明申请

US20120298948A1 NANOWIRE FET HAVING INDUCED RADIAL STRAIN 有权
标题翻译：具有诱导径向应变的纳米效应管
公开(公告)号：US20120298948A1
公开(公告)日：2012-11-29
申请号：US13566594
申请日：2012-08-03
申请人： Sarunya Bangsaruntip , Guy Cohen , Conal E. Murray , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy Cohen , Conal E. Murray , Jeffrey W. Sleight
IPC分类号： H01L29/775 , B82Y99/00
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/42392 , H01L29/7845 , H01L29/78696
摘要： An intermediate process device is provided and includes a nanowire connecting first and second silicon-on-insulator (SOI) pads, a gate including a gate conductor surrounding the nanowire and poly-Si surrounding the gate conductor and silicide forming metal disposed to react with the poly-Si to form a fully silicided (FUSI) material to induce radial strain in the nanowire.
摘要翻译：提供了一种中间处理装置，包括连接第一和第二绝缘体上硅（SOI）焊盘的纳米线，包括围绕该纳米线的栅极导体和围绕该栅极导体的多晶硅的栅极以及设置成与该栅极导体反应的硅化物形成金属多晶硅以形成完全硅化（FUSI）材料以在纳米线中诱导径向应变。

62. 发明授权

US08321961B2 Production scale fabrication method for high resolution AFM tips 失效
标题翻译：高分辨率AFM提示的生产规模制作方法
公开(公告)号：US08321961B2
公开(公告)日：2012-11-27
申请号：US12900123
申请日：2010-10-07
申请人： Guy Cohen , Mark C. Reuter , Brent A. Wacaser , Maha M. Khayyat
发明人： Guy Cohen , Mark C. Reuter , Brent A. Wacaser , Maha M. Khayyat
IPC分类号： G01Q60/38 , B82Y99/00 , B82Y40/00
CPC分类号： G01Q70/12 , G01Q60/38
摘要： A method of fabricating high resolution atomic force microscopy (AFM) tips including a single semiconductor nanowire grown at an apex of a semiconductor pyramid of each AFM tip is provided. The semiconductor nanowire that is grown has a controllable diameter and a high aspect ratio, without significant tapering from the tip of the semiconductor nanowire to its base. The method includes providing an AFM probe including a semiconductor cantilever having a semiconductor pyramid extending upward from a surface of said semiconductor cantilever. The semiconductor pyramid has an apex. A patterned oxide layer is formed on the AFM probe. The patterned oxide layer has an opening that exposes the apex of the semiconductor pyramid. A single semiconductor nanowire is grown on the exposed apex of the semiconductor pyramid utilizing a non-oxidized Al seed material as a catalyst for nanowire growth.
摘要翻译：提供了一种制造高分辨率原子力显微镜（AFM）尖端的方法，其包括在每个AFM尖端的半导体金字塔的顶点处生长的单个半导体纳米线。生长的半导体纳米线具有可控直径和高纵横比，而没有从半导体纳米线的尖端到其基底的显着锥形化。该方法包括提供包括半导体悬臂的AFM探针，该半导体悬臂具有从所述半导体悬臂的表面向上延伸的半导体金字塔。半导体金字塔有顶点。在AFM探针上形成图案化的氧化物层。图案化氧化物层具有暴露半导体金字塔的顶点的开口。使用未氧化的Al种子材料作为纳米线生长的催化剂，在半导体金字塔的暴露的顶点上生长单个半导体纳米线。

63. 发明授权

US08241971B2 MOSFET with a nanowire channel and fully silicided (FUSI) wrapped around gate 有权
标题翻译：具有纳米线通道和全硅化物（FUSI）的MOSFET缠绕在栅极上
公开(公告)号：US08241971B2
公开(公告)日：2012-08-14
申请号：US12561694
申请日：2009-09-17
申请人： Sarunya Bangsaruntip , Guy Cohen
发明人： Sarunya Bangsaruntip , Guy Cohen
IPC分类号： H01L21/00
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/0676 , H01L29/42392 , H01L29/4908 , H01L29/66439 , H01L29/66628 , H01L29/775 , H01L29/78696
摘要： Nanowire-channel metal oxide semiconductor field effect transistors (MOSFETs) and techniques for the fabrication thereof are provided. In one aspect, a MOSFET includes a nanowire channel; a fully silicided gate surrounding the nanowire channel; and a raised source and drain connected by the nanowire channel. A method of fabricating a MOSFET is also provided.
摘要翻译：提供纳米线 - 沟道金属氧化物半导体场效应晶体管（MOSFET）及其制造技术。一方面，MOSFET包括纳米线通道; 围绕纳米线通道的完全硅化的栅极; 并且由纳米线通道连接的升高的源极和漏极。还提供了制造MOSFET的方法。

64. 发明申请

US20120161212A1 CONTINUOUS METAL SEMICONDUCTOR ALLOY VIA FOR INTERCONNECTS 有权
标题翻译：连续金属半导体合金通过互连
公开(公告)号：US20120161212A1
公开(公告)日：2012-06-28
申请号：US13405739
申请日：2012-02-27
申请人： Guy Cohen , Christos D. Dimitrakopoulos , Alfred Grill
发明人： Guy Cohen , Christos D. Dimitrakopoulos , Alfred Grill
IPC分类号： H01L29/78 , B82Y99/00
CPC分类号： H01L29/7848 , B82Y10/00 , H01L21/28518 , H01L21/76885 , H01L23/481 , H01L29/665 , H01L29/78 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要： A contact structure is disclosed in which a continuous metal semiconductor alloy is located within a via contained within a dielectric material. The continuous semiconductor metal alloy is in direct contact with an upper metal line of a first metal level located atop the continuous semiconductor metal alloy and at least a surface of each source and drain diffusion region located beneath the continuous metal semiconductor alloy. The continuous metal semiconductor alloy includes a lower portion that is contained within an upper surface of each source and drain region, and a vertical pillar portion extending upward from the lower portion.
摘要翻译：公开了一种接触结构，其中连续的金属半导体合金位于包含在电介质材料内的通孔内。连续半导体金属合金与位于连续半导体金属合金顶部的第一金属水平的上金属线和至少位于连续金属半导体合金下方的源极和漏极扩散区的表面直接接触。连续金属半导体合金包括包含在每个源极和漏极区域的上表面内的下部以及从下部向上延伸的垂直柱部分。

65. 发明申请

US20120033226A1 OPTICS SYMMETRIZATION FOR METROLOGY 有权
标题翻译： OPTICS SYMPETRIZATION FOR METROLOGY
公开(公告)号：US20120033226A1
公开(公告)日：2012-02-09
申请号：US13188623
申请日：2011-07-22
申请人： Amnon Manassen , Daniel Kandel , Moshe Baruch , Joel L. Seligson , Alexander Svizher , Guy Cohen , Efraim Rotem , Ohad Bachar , Daria Negri , Noam Sapiens
发明人： Amnon Manassen , Daniel Kandel , Moshe Baruch , Joel L. Seligson , Alexander Svizher , Guy Cohen , Efraim Rotem , Ohad Bachar , Daria Negri , Noam Sapiens
IPC分类号： G01B9/02 , G01N21/55
CPC分类号： G03F7/70633 , G01N21/55 , G03F7/70616
摘要： The present invention includes an illumination source, at least one illumination symmetrization module (ISM) configured to symmetrize at least a portion of light emanating from the illumination source, a first beam splitter configured to direct a first portion of light processed by the ISM along an object path to a surface of one or more specimens and a second portion of light processed by the ISM along a reference path, and a detector disposed along a primary optical axis, wherein the detector is configured to collect a portion of light reflected from the surface of the one or more specimens.
摘要翻译：本发明包括照明源，至少一个照明对称化模块（ISM），被配置为对来自照明源发出的光的至少一部分进行对称;第一分束器，被配置为将由ISM处理的光的第一部分沿着一个或多个样本的表面的物体路径和沿着基准路径由ISM处理的光的第二部分以及沿着主光轴布置的检测器，其中检测器被配置为收集从表面反射的光的一部分的一个或多个标本。

66. 发明授权

US08008146B2 Different thickness oxide silicon nanowire field effect transistors 失效
标题翻译：不同厚度的氧化硅纳米线场效应晶体管
公开(公告)号：US08008146B2
公开(公告)日：2011-08-30
申请号：US12631148
申请日：2009-12-04
申请人： Sarunya Bangsaruntip , Andres Bryant , Guy Cohen , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Andres Bryant , Guy Cohen , Jeffrey W. Sleight
IPC分类号： H01L21/8238 , H01L29/76
CPC分类号： H01L29/78696 , H01L29/42392
摘要： A method (that produces a structure) patterns at least two wires of semiconductor material such that a first wire of the wires has a larger perimeter than a second wire of the wires. The method performs an oxidation process simultaneously on the wires to form a first gate oxide on the first wire and a second gate oxide on the second wire. The first gate oxide is thicker than the second gate oxide. The method also forms gate conductors over the first gate oxide and the second gate oxide, forms sidewall spacers on the gate conductors, and dopes portions of the first wire and the second wire not covered by the sidewall spacers and the gate conductors to form source and drain regions within the first wire and the second wire.
摘要翻译：产生结构的方法（图案）至少形成两条半导体材料线，使得电线的第一线具有比电线的第二线更大的周长。该方法在导线上同时进行氧化处理，以在第一布线上形成第一栅极氧化物，在第二布线上形成第二栅极氧化物。第一栅极氧化物比第二栅极氧化物厚。该方法还在第一栅极氧化物和第二栅极氧化物上形成栅极导体，在栅极导体上形成侧壁间隔物，以及第一导线和第二导线的掺杂部分未被侧壁间隔物和栅极导体覆盖以形成源极和第一线和第二线内的漏极区。

67. 发明申请

US20090302305A1 SELF-CONSTRAINED ANISOTROPIC GERMANIUM NANOSTRUCTURE FROM ELECTROPLATING 有权
标题翻译：电镀的自约束非均质锗原子纳米结构
公开(公告)号：US20090302305A1
公开(公告)日：2009-12-10
申请号：US12541559
申请日：2009-08-14
申请人： Guy Cohen , Hariklia Deligianni , Qiang Huang , Lubomyr T. Romankiw
发明人： Guy Cohen , Hariklia Deligianni , Qiang Huang , Lubomyr T. Romankiw
IPC分类号： H01L29/12
CPC分类号： C25D3/54 , B82Y10/00 , C25D5/022 , C25D7/123 , H01L21/0237 , H01L21/02532 , H01L21/02603 , H01L21/02628 , H01L21/02639 , Y10S977/762
摘要： A nanostructure comprising germanium, including wires of less than 1 micron in diameter and walls of less than 1 micron in width, in contact with the substrate and extending outward from the substrate is provided along with a method of preparation.
摘要翻译：提供包括锗的纳米结构，其包括直径小于1微米的导线和宽度小于1微米的与基底接触并从基底向外延伸的纳米结构以及制备方法。

68. 发明申请

US20090231915A1 Reading array cell with matched reference cell 有权
标题翻译：读取具有匹配参考单元格的阵列单元
公开(公告)号：US20090231915A1
公开(公告)日：2009-09-17
申请号：US12292654
申请日：2008-11-24
申请人： Eli Lusky , Boaz Eitan , Guy Cohen , Eduardo Maayan
发明人： Eli Lusky , Boaz Eitan , Guy Cohen , Eduardo Maayan
IPC分类号： G11C16/04 , G11C7/02 , G11C16/06 , H01L21/336
CPC分类号： G11C16/3436 , G11C11/5671 , G11C16/0466 , G11C16/28 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , G11C2211/5634
摘要： A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to a multi-bit reference cell, the reference cell comprising a first bit at a first non-ground programmed state and a second bit at a second non-ground programmed state. Compared with the prior art, the present invention may enable achieving an improved sensing accuracy together with improved read disturb immunity.
摘要翻译：一种用于读取非易失性存储器（NVM）单元阵列中的存储器单元的位的方法，所述方法包括提供包括要读取的位和至少一个其他不被读取的位的存储单元，并读取位相对于多位参考单元读取，参考单元包括处于第一非地编程状态的第一位和处于第二非地编程状态的第二位。与现有技术相比，本发明可以实现改进的感测精度以及改进的读取干扰抗扰度。

69. 发明申请

US20080064149A1 STRAINED-CHANNEL FIN FIELD EFFECT TRANSISTOR (FET) WITH A UNIFORM CHANNEL THICKNESS AND SEPARATE GATES 有权
公开(公告)号：US20080064149A1
公开(公告)日：2008-03-13
申请号：US11927893
申请日：2007-10-30
申请人： Guy Cohen
发明人： Guy Cohen
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L21/823412 , H01L21/823487 , H01L21/84 , H01L27/1203 , H01L29/1054 , H01L29/66795 , H01L29/7842 , H01L29/78687 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device (and method for making the same) includes a strained-silicon channel formed adjacent a source and a drain, a first gate formed over a first side of the channel, a second gate formed over a second side of the channel, a first gate dielectric formed between the first gate and the strained-silicon channel, and a second gate dielectric formed between the second gate and the strained-silicon channel. The strained-silicon channel is non-planar.

70. 发明申请

US20080050887A1 METHOD FOR FABRICATING SiGe-ON-INSULATOR (SGOI) AND Ge-ON-INSULATOR (GOI) SUBSTRATES 有权
标题翻译：用于制造SiGe-ON绝缘体（SGOI）和Ge-ON-Insulator（GOI）衬底的方法
公开(公告)号：US20080050887A1
公开(公告)日：2008-02-28
申请号：US11924207
申请日：2007-10-25
申请人： Tze-chiang Chen , Guy Cohen , Alexander Reznicek , Devendra Sadana , Ghavam Shahidi
发明人： Tze-chiang Chen , Guy Cohen , Alexander Reznicek , Devendra Sadana , Ghavam Shahidi
IPC分类号： H01L21/30
CPC分类号： H01L21/76254 , H01L31/02327 , H01L31/028 , H01L31/1812 , Y02E10/547
摘要： A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.
摘要翻译：提供了绝缘体上（锗）绝缘体（GOI）衬底材料的方法，通过该方法生产的GOI衬底材料和至少可以包括本发明的GOI衬底材料的各种结构。 GOI衬底材料至少包括衬底，位于衬底顶部的掩埋绝缘体层，以及位于掩埋绝缘体层顶部的优选纯Ge的Ge含有层。在本发明的GOI基板材料中，Ge含有层也可以称为GOI膜。 GOI膜是可以形成器件的本发明的基底材料的层。

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