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1. 发明授权

US09164397B2 Optics symmetrization for metrology 有权
标题翻译：计量学的光学对称性
公开(公告)号：US09164397B2
公开(公告)日：2015-10-20
申请号：US13188623
申请日：2011-07-22
申请人： Amnon Manassen , Daniel Kandel , Moshe Baruch , Joel L. Seligson , Alexander Svizher , Guy Cohen , Efraim Rotem , Ohad Bachar , Daria Negri , Noam Sapiens
发明人： Amnon Manassen , Daniel Kandel , Moshe Baruch , Joel L. Seligson , Alexander Svizher , Guy Cohen , Efraim Rotem , Ohad Bachar , Daria Negri , Noam Sapiens
IPC分类号： G01B9/02 , G03F7/20 , G01N21/55
CPC分类号： G03F7/70633 , G01N21/55 , G03F7/70616
摘要： The present invention includes an illumination source, at least one illumination symmetrization module (ISM) configured to symmetrize at least a portion of light emanating from the illumination source, a first beam splitter configured to direct a first portion of light processed by the ISM along an object path to a surface of one or more specimens and a second portion of light processed by the ISM along a reference path, and a detector disposed along a primary optical axis, wherein the detector is configured to collect a portion of light reflected from the surface of the one or more specimens.
摘要翻译：本发明包括照明源，至少一个照明对称化模块（ISM），被配置为对来自照明源发出的光的至少一部分进行对称;第一分束器，被配置为将由ISM处理的光的第一部分沿着一个或多个样本的表面的物体路径和沿着基准路径由ISM处理的光的第二部分以及沿着主光轴布置的检测器，其中检测器被配置为收集从表面反射的光的一部分的一个或多个标本。

2. 发明申请

US20120033226A1 OPTICS SYMMETRIZATION FOR METROLOGY 有权
标题翻译： OPTICS SYMPETRIZATION FOR METROLOGY
公开(公告)号：US20120033226A1
公开(公告)日：2012-02-09
申请号：US13188623
申请日：2011-07-22
申请人： Amnon Manassen , Daniel Kandel , Moshe Baruch , Joel L. Seligson , Alexander Svizher , Guy Cohen , Efraim Rotem , Ohad Bachar , Daria Negri , Noam Sapiens
发明人： Amnon Manassen , Daniel Kandel , Moshe Baruch , Joel L. Seligson , Alexander Svizher , Guy Cohen , Efraim Rotem , Ohad Bachar , Daria Negri , Noam Sapiens
IPC分类号： G01B9/02 , G01N21/55
CPC分类号： G03F7/70633 , G01N21/55 , G03F7/70616
摘要： The present invention includes an illumination source, at least one illumination symmetrization module (ISM) configured to symmetrize at least a portion of light emanating from the illumination source, a first beam splitter configured to direct a first portion of light processed by the ISM along an object path to a surface of one or more specimens and a second portion of light processed by the ISM along a reference path, and a detector disposed along a primary optical axis, wherein the detector is configured to collect a portion of light reflected from the surface of the one or more specimens.
摘要翻译：本发明包括照明源，至少一个照明对称化模块（ISM），被配置为对来自照明源发出的光的至少一部分进行对称;第一分束器，被配置为将由ISM处理的光的第一部分沿着一个或多个样本的表面的物体路径和沿着基准路径由ISM处理的光的第二部分以及沿着主光轴布置的检测器，其中检测器被配置为收集从表面反射的光的一部分的一个或多个标本。

3. 发明申请

US20130035888A1 METHOD AND SYSTEM FOR PROVIDING A QUALITY METRIC FOR IMPROVED PROCESS CONTROL 审中-公开
标题翻译：提供改进过程控制质量标准的方法和系统
公开(公告)号：US20130035888A1
公开(公告)日：2013-02-07
申请号：US13508495
申请日：2012-04-04
申请人： Daniel Kandel , Guy Cohen , Dana Klein , Vladimir Levinski , Noam Sapiens , Alex Shulman , Vladimir Kamenetsky , Eran Amit , Irina Vakshtein
发明人： Daniel Kandel , Guy Cohen , Dana Klein , Vladimir Levinski , Noam Sapiens , Alex Shulman , Vladimir Kamenetsky , Eran Amit , Irina Vakshtein
IPC分类号： G01N37/00 , G06F19/00
摘要： The present invention may include acquiring a plurality of overlay metrology measurement signals from a plurality of metrology targets distributed across one or more fields of a wafer of a lot of wafers, determining a plurality of overlay estimates for each of the plurality of overlay metrology measurement signals using a plurality of overlay algorithms, generating a plurality of overlay estimate distributions, and generating a first plurality of quality metrics utilizing the generated plurality of overlay estimate distributions, wherein each quality metric corresponds with one overlay estimate distribution of the generated plurality of overlay estimate distributions, each quality metric a function of a width of a corresponding generated overlay estimate distribution, each quality metric further being a function of asymmetry present in an overlay metrology measurement signal from an associated metrology target.
摘要翻译：本发明可以包括从分布在许多晶片的晶片的一个或多个场上的多个测量目标获取多个覆盖度量测量信号，为多个覆盖度量测量信号中的每一个确定多个重叠估计使用多个覆盖算法，生成多个覆盖估计分布，以及利用所生成的多个覆盖估计分布来生成第一多个质量度量，其中每个质量度量对应于所生成的多个覆盖估计分布的一个覆盖估计分布每个质量度量是对应的生成的重叠估计分布的宽度的函数，每个质量度量还是来自相关度量目标的覆盖度量测量信号中存在的不对称的函数。

4. 发明授权

US11372340B2 Method and system for providing a quality metric for improved process control 有权
公开(公告)号：US11372340B2
公开(公告)日：2022-06-28
申请号：US13508495
申请日：2012-04-04
申请人： Daniel Kandel , Guy Cohen , Dana Klein , Vladimir Levinski , Noam Sapiens , Alex Shulman , Vladimir Kamenetsky , Eran Amit , Irina Vakshtein
发明人： Daniel Kandel , Guy Cohen , Dana Klein , Vladimir Levinski , Noam Sapiens , Alex Shulman , Vladimir Kamenetsky , Eran Amit , Irina Vakshtein
IPC分类号： G03F7/20 , G03F1/48
摘要： The present invention may include acquiring a plurality of overlay metrology measurement signals from a plurality of metrology targets distributed across one or more fields of a wafer of a lot of wafers, determining a plurality of overlay estimates for each of the plurality of overlay metrology measurement signals using a plurality of overlay algorithms, generating a plurality of overlay estimate distributions, and generating a first plurality of quality metrics utilizing the generated plurality of overlay estimate distributions, wherein each quality metric corresponds with one overlay estimate distribution of the generated plurality of overlay estimate distributions, each quality metric a function of a width of a corresponding generated overlay estimate distribution, each quality metric further being a function of asymmetry present in an overlay metrology measurement signal from an associated metrology target.

5. 发明申请

US20120033215A1 MULTI-LAYER OVERLAY METROLOGY TARGET AND COMPLIMENTARY OVERLAY METROLOGY MEASUREMENT SYSTEMS 有权
标题翻译：多层叠加计量目标和综合覆盖度量度测量系统
公开(公告)号：US20120033215A1
公开(公告)日：2012-02-09
申请号：US13186144
申请日：2011-07-19
申请人： Daniel Kandel , Vladimir Levinski , Guy Cohen
发明人： Daniel Kandel , Vladimir Levinski , Guy Cohen
IPC分类号： G01B11/06 , G01J4/00
CPC分类号： G03F7/70633 , G03F7/70683
摘要： A multi-layer overlay target for use in imaging based metrology is disclosed. The overlay target includes a plurality of target structures including three or more target structures, each target structure including a set of two or more pattern elements, wherein the target structures are configured to share a common center of symmetry upon alignment of the target structures, each target structure being invariant to N degree rotation about the common center of symmetry, wherein N is equal to or greater than 180 degrees, wherein each of the two or more pattern elements has an individual center of symmetry, wherein each of the two or more pattern elements of each target structure is invariant to M degree rotation about the individual center of symmetry, wherein M is equal to or greater than 180 degrees.
摘要翻译：公开了一种用于基于成像的计量学的多层覆盖目标。覆盖目标包括包括三个或更多个目标结构的多个目标结构，每个目标结构包括一组两个或多个模式元素，其中目标结构被配置为在目标结构对准时共享公共对称中心，每个目标结构目标结构相对于公共对称中心不变为N度旋转，其中N等于或大于180度，其中两个或更多个图案元素中的每一个具有单独的对称中心，其中两个或更多个图案每个目标结构的元素对于单个对称中心的M度旋转是不变的，其中M等于或大于180度。

6. 发明授权

US09927718B2 Multi-layer overlay metrology target and complimentary overlay metrology measurement systems 有权
公开(公告)号：US09927718B2
公开(公告)日：2018-03-27
申请号：US13186144
申请日：2011-07-19
申请人： Daniel Kandel , Vladimir Levinski , Guy Cohen
发明人： Daniel Kandel , Vladimir Levinski , Guy Cohen
IPC分类号： G01J4/00 , G03F7/20
CPC分类号： G03F7/70633 , G03F7/70683
摘要： A multi-layer overlay target for use in imaging based metrology is disclosed. The overlay target includes a plurality of target structures including three or more target structures, each target structure including a set of two or more pattern elements, wherein the target structures are configured to share a common center of symmetry upon alignment of the target structures, each target structure being invariant to N degree rotation about the common center of symmetry, wherein N is equal to or greater than 180 degrees, wherein each of the two or more pattern elements has an individual center of symmetry, wherein each of the two or more pattern elements of each target structure is invariant to M degree rotation about the individual center of symmetry, wherein M is equal to or greater than 180 degrees.

7. 发明授权

US08936972B2 Epitaxially thickened doped or undoped core nanowire FET structure and method for increasing effective device width 有权
标题翻译：外延增厚的掺杂或未掺杂的核心纳米线FET结构和增加有效器件宽度的方法
公开(公告)号：US08936972B2
公开(公告)日：2015-01-20
申请号：US13596234
申请日：2012-08-28
申请人： Sarunya Bangsaruntip , Guy Cohen , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy Cohen , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L21/84 , H01L29/06
CPC分类号： H01L29/775 , B82Y10/00 , B82Y40/00 , H01L21/02381 , H01L21/02428 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/02639 , H01L29/0673 , H01L29/42392 , H01L29/78696
摘要： Techniques for increasing effective device width of a nanowire FET device are provided. In one aspect, a method of fabricating a FET device is provided. The method includes the following steps. A SOI wafer is provided having an SOI layer over a BOX, wherein the SOI layer is present between a buried nitride layer and a nitride cap. The SOI layer, the buried nitride layer and the nitride cap are etched to form nanowire cores and pads in the SOI layer in a ladder-like configuration. The nanowire cores are suspended over the BOX. Epitaxial sidewalls are formed over the sidewalls of the nanowires cores. The buried nitride layer and the nitride cap are removed from the nanowire cores. A gate stack is formed that surrounds at least a portion of each of the nanowire cores and the epitaxial sidewalls.
摘要翻译：提供了增加纳米线FET器件的有效器件宽度的技术。一方面，提供一种制造FET器件的方法。该方法包括以下步骤。提供了在BOX上具有SOI层的SOI晶片，其中SOI层存在于掩埋氮化物层和氮化物盖之间。蚀刻SOI层，埋入氮化物层和氮化物盖，以形成阶梯状构造的SOI层中的纳米线芯和焊盘。纳米线芯悬挂在BOX上。外延侧壁形成在纳米线芯的侧壁上。从纳米线芯中去除掩埋氮化物层和氮化物盖。形成围绕纳米线芯和外延侧壁中的每一个的至少一部分的栅叠层。

8. 发明申请

US20140075258A1 ITERATIVE RECEIVER LOOP 有权
标题翻译：迭代接收器环路
公开(公告)号：US20140075258A1
公开(公告)日：2014-03-13
申请号：US13612911
申请日：2012-09-13
申请人： Mor Miller , Amit Steinberg , Daniel Wajcer , Dan Peleg , Guy Cohen
发明人： Mor Miller , Amit Steinberg , Daniel Wajcer , Dan Peleg , Guy Cohen
IPC分类号： H03M13/00
CPC分类号： H04L1/005 , H04L1/0047 , H04L1/0057 , H04L27/2655 , H04L27/266 , H04L27/2665 , H04L27/2679 , H04L27/2689 , H04L2001/0093 , H04L2027/0055 , H04L2027/0067
摘要： A method includes receiving a signal, which carries data that is encoded with an Error Correction Code (ECC), and correcting the received signal with an adaptive receiver loop. Soft input metrics for the data are computed over the corrected signal. The ECC is decoded using a decoder, which estimates soft output metrics based on the soft input metrics, by operating the decoder in an alternating pattern of external iterations that update one or more of the soft input metrics based on one or more of the soft output metrics, and internal iterations that update the soft output metrics but not the soft input metrics. The adaptive receiver loop is adjusted in a schedule that is defined relative to the pattern of the external and the internal iterations of the decoder.
摘要翻译：一种方法包括接收携带用纠错码（ECC）编码的数据的信号，并用自适应接收机环路校正接收到的信号。通过校正信号计算数据的软输入度量。使用解码器对ECC进行解码，解码器通过以基于软输出中的一个或多个更新一个或多个软输入度量的外部迭代的交替模式操作解码器来基于软输入度量来估计软输出量度指标和内部迭代更新软输出指标，而不是软输入指标。在相对于解码器的外部和内部迭代的模式定义的调度中调整自适应接收器环路。

9. 发明授权

US08564025B2 Nanowire FET having induced radial strain 有权
标题翻译：纳米线FET引起径向应变
公开(公告)号：US08564025B2
公开(公告)日：2013-10-22
申请号：US13566594
申请日：2012-08-03
申请人： Sarunya Bangsaruntip , Guy Cohen , Conal E. Murray , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy Cohen , Conal E. Murray , Jeffrey W. Sleight
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/42392 , H01L29/7845 , H01L29/78696
摘要： An intermediate process device is provided and includes a nanowire connecting first and second silicon-on-insulator (SOI) pads, a gate including a gate conductor surrounding the nanowire and poly-Si surrounding the gate conductor and silicide forming metal disposed to react with the poly-Si to form a fully silicided (FUSI) material to induce radial strain in the nanowire.
摘要翻译：提供了一种中间处理装置，包括连接第一和第二绝缘体上硅（SOI）焊盘的纳米线，包括围绕该纳米线的栅极导体和围绕该栅极导体的多晶硅的栅极以及设置成与该栅极导体反应的硅化物形成金属多晶硅以形成完全硅化（FUSI）材料以在纳米线中诱导径向应变。

10. 发明授权

US08546269B2 Top-down nanowire thinning processes 失效
标题翻译：自上而下的纳米线稀疏过程
公开(公告)号：US08546269B2
公开(公告)日：2013-10-01
申请号：US12417936
申请日：2009-04-03
申请人： Tymon Barwicz , Guy Cohen , Lidija Sekaric , Jeffrey Sleight
发明人： Tymon Barwicz , Guy Cohen , Lidija Sekaric , Jeffrey Sleight
IPC分类号： H01L21/302 , H01L21/461 , H01L29/06
CPC分类号： H01L21/02238 , B82Y10/00 , B82Y30/00 , H01L21/02255 , H01L21/30604 , H01L29/0665 , H01L29/0676 , H01L29/42392 , H01L29/775 , H01L29/78696
摘要： Techniques for fabricating nanowire-based devices are provided. In one aspect, a method for fabricating a semiconductor device is provided comprising the following steps. A wafer is provided having a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer. Nanowires and pads are etched into the SOI layer to form a ladder-like structure wherein the pads are attached at opposite ends of the nanowires. The BOX layer is undercut beneath the nanowires. The nanowires and pads are contacted with an oxidizing gas to oxidize the silicon in the nanowires and pads under conditions that produce a ratio of a silicon consumption rate by oxidation on the nanowires to a silicon consumption rate by oxidation on the pads of from about 0.75 to about 1.25. An aspect ratio of width to thickness among all of the nanowires may be unified prior to contacting the nanowires and pads with the oxidizing gas.
摘要翻译：提供了制造基于纳米线的器件的技术。一方面，提供一种制造半导体器件的方法，包括以下步骤。提供了在掩埋氧化物（BOX）层上方具有绝缘体上硅（SOI）层的晶片。将纳米线和焊盘蚀刻到SOI层中以形成阶梯状结构，其中焊盘附着在纳米线的相对端。 BOX层在纳米线下面被切下。纳米线和焊盘与氧化气体接触，以在通过氧化在纳米线上产生硅消耗速率与硅消耗速率之比的条件下，在纳米线和焊盘中氧化硅，焊盘上的氧化从约0.75降至约1.25。在使纳米线和焊盘与氧化气体接触之前，可以统一所有纳米线中的宽度与厚度的纵横比。

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