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1. 发明授权

US08248855B2 Method of handling reference cells in NVM arrays 失效
标题翻译：在NVM阵列中处理参考单元的方法
公开(公告)号：US08248855B2
公开(公告)日：2012-08-21
申请号：US12720687
申请日：2010-03-10
申请人： Eli Lusky , Aner Arussi , Amir Gabai
发明人： Eli Lusky , Aner Arussi , Amir Gabai
IPC分类号： G11C11/34
CPC分类号： G11C16/28 , G11C11/5642
摘要： A memory chip includes memory cells storing data to be read, at least one reference cell having a reference cell current level, at least one reference gate voltage memory cell storing a reference gate voltage value and a read circuit to read the memory cells with a fixed gate voltage with respect to at least one reference cell activated at a voltage having its associated stored reference gate voltage value.
摘要翻译：存储器芯片包括存储要读取的数据的存储单元，具有参考单元电流电平的至少一个参考单元，存储参考栅极电压值的至少一个参考栅极电压存储单元和读取电路，以用固定的相对于在具有其相关联的存储的参考栅极电压值的电压下被激活的至少一个参考单元的栅极电压。

2. 发明申请

US20120206962A1 METHOD OF HANDLING REFERENCE CELLS IN NVM ARRAYS 审中-公开
标题翻译：在NVM阵列中处理参考细胞的方法
公开(公告)号：US20120206962A1
公开(公告)日：2012-08-16
申请号：US13438858
申请日：2012-04-04
申请人： Eli LUSKY , Aner ARUSSI , Amir GABAI
发明人： Eli LUSKY , Aner ARUSSI , Amir GABAI
IPC分类号： G11C16/28 , G11C16/04
CPC分类号： G11C16/28 , G11C11/5642
摘要： A memory chip includes memory cells storing data to be read; at least one reference cell having a reference cell current level and a reference gate voltage adjuster to adjust, for each reference cell, a reference gate voltage level to compensate for a shift of the reference cell current level from an original current level.
摘要翻译：存储芯片包括存储要读取的数据的存储单元; 具有参考单元电流电平的至少一个参考单元和参考栅极电压调节器，用于为每个参考单元调整参考栅极电压电平，以补偿参考单元电流电平与原始电流电平的偏移。

3. 发明申请

US20110222338A1 METHOD OF HANDLING REFERENCE CELLS IN NVM ARRAYS 失效
标题翻译：在NVM阵列中处理参考细胞的方法
公开(公告)号：US20110222338A1
公开(公告)日：2011-09-15
申请号：US12720687
申请日：2010-03-10
申请人： ELI LUSKY , Aner Arussi , Amir Gabai
发明人： ELI LUSKY , Aner Arussi , Amir Gabai
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/28 , G11C11/5642
摘要： A memory chip includes memory cells storing data to be read, at least one reference cell having a reference cell current level, at least one reference gate voltage memory cell storing a reference gate voltage value and a read circuit to read the memory cells with a fixed gate voltage with respect to at least one reference cell activated at a voltage having its associated stored reference gate voltage value.
摘要翻译：存储器芯片包括存储要读取的数据的存储单元，具有参考单元电流电平的至少一个参考单元，存储参考栅极电压值的至少一个参考栅极电压存储单元和读取电路，以用固定的相对于在具有其相关联的存储的参考栅极电压值的电压下被激活的至少一个参考单元的栅极电压。

4. 发明授权

US07964459B2 Non-volatile memory structure and method of fabrication 有权
标题翻译：非易失性存储器结构和制造方法
公开(公告)号：US07964459B2
公开(公告)日：2011-06-21
申请号：US12654092
申请日：2009-12-10
申请人： Eli Lusky , Assaf Shappir , Rustom Irani , Boaz Eitan
发明人： Eli Lusky , Assaf Shappir , Rustom Irani , Boaz Eitan
IPC分类号： H01L21/8238
CPC分类号： H01L27/115 , H01L21/28282 , H01L21/32139 , H01L27/11568 , H01L29/66833
摘要： A method for creating a non-volatile memory array includes implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering the substrate, generating increased-width polysilicon columns from the mask columns, generating bit lines in the substrate at least between the increased-width polysilicon columns and depositing oxide at least between the polysilicon columns.
摘要翻译：一种用于创建非易失性存储器阵列的方法包括至少在给定宽度的掩模列之间以及至少穿过覆盖衬底的ONO层之间的衬底中注入口袋植入物，从掩模柱产生增加宽度的多晶硅柱，产生位至少在增宽宽度的多晶硅柱之间并且至少在多晶硅柱之间沉积氧化物的衬底中的线。

5. 发明授权

US07864612B2 Reading array cell with matched reference cell 有权
标题翻译：读取具有匹配参考单元格的阵列单元
公开(公告)号：US07864612B2
公开(公告)日：2011-01-04
申请号：US12292654
申请日：2008-11-24
申请人： Eli Lusky , Boaz Eitan , Guy Cohen , Eduardo Maayan
发明人： Eli Lusky , Boaz Eitan , Guy Cohen , Eduardo Maayan
IPC分类号： G11C7/00
CPC分类号： G11C16/3436 , G11C11/5671 , G11C16/0466 , G11C16/28 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , G11C2211/5634
摘要： A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to a multi-bit reference cell, the reference cell comprising a first bit at a first non-ground programmed state and a second bit at a second non-ground programmed state. Compared with the prior art, the present invention may enable achieving an improved sensing accuracy together with improved read disturb immunity.
摘要翻译：一种用于读取非易失性存储器（NVM）单元阵列中的存储器单元的位的方法，所述方法包括提供包括要读取的位和至少一个其他不被读取的位的存储单元，并读取位相对于多位参考单元读取，参考单元包括处于第一非地编程状态的第一位和处于第二非地编程状态的第二位。与现有技术相比，本发明可以实现改进的感测精度以及改进的读取干扰抗扰度。

6. 发明申请

US20100146239A1 CONTINUOUS ADDRESS SPACE IN NON-VOLATILE-MEMORIES (NVM) USING EFFICIENT EMBEDDED MANAGEMENT OF ARRAY DEFICIENCIES 审中-公开
标题翻译：使用高效嵌入式管理的非易失性存储器（NVM）中的连续地址空间
公开(公告)号：US20100146239A1
公开(公告)日：2010-06-10
申请号：US12330116
申请日：2008-12-08
申请人： Amir GABAI , Yoav Yogev , Dror Avni , Eli Lusky
发明人： Amir GABAI , Yoav Yogev , Dror Avni , Eli Lusky
IPC分类号： G06F12/10 , G06F11/20
CPC分类号： G06F12/0246 , G06F2212/7201 , G06F2212/7202 , G11C29/76
摘要： The invention provides a method of managing bad block in a data storage device having an OTP memory die in order to present a continues address space toward the user, by using some of the OTP memory space for the management and maintaining address replacement table. Fast and efficient programming and writing algorithms are presented.
摘要翻译：本发明提供了一种管理具有OTP存储器管芯的数据存储设备中的坏块的方法，以便通过使用一些OTP存储器空间来管理和维护地址替换表来向用户呈现持续的地址空间。介绍了快速高效的编程和编写算法。

7. 发明申请

US20120095966A1 METHOD FOR USING AN OTP STORAGE DEVICE 审中-公开
标题翻译：使用OTP存储设备的方法
公开(公告)号：US20120095966A1
公开(公告)日：2012-04-19
申请号：US13334284
申请日：2011-12-22
申请人： Yoav Yogev , Eli Lusky
发明人： Yoav Yogev , Eli Lusky
IPC分类号： G06F17/00 , G06F7/00
CPC分类号： G06F12/0238 , G06F3/0679
摘要： The invention provides a method of managing data updates in DOS-based data storage device having an OTP memory die that includes a code region having a first memory capacity and a code region access resolution and a data region having a second memory capacity and a data region access resolution. The second memory capacity is larger than the first memory capacity and the code region access resolution is finer than the data region access resolution. The method includes chronologically writing a log entry in the code region indicating the change in FAT and root directory for each change in user data written in the data region.
摘要翻译：本发明提供了一种在基于DOS的数据存储设备中管理数据更新的方法，该设备具有OTP存储器管芯，其包括具有第一存储器容量和代码区域访问分辨率的代码区域以及具有第二存储器容量的数据区域和数据区域访问分辨率。第二存储器容量大于第一存储容量，并且代码区访问分辨率比数据区访问分辨率更精细。该方法包括按照时间顺序在代码区中写入日志条目，指示在数据区域中写入的用户数据的每个改变的FAT和根目录的变化。

8. 发明授权

US07668017B2 Method of erasing non-volatile memory cells 有权
标题翻译：擦除非易失性存储单元的方法
公开(公告)号：US07668017B2
公开(公告)日：2010-02-23
申请号：US11205716
申请日：2005-08-17
申请人： Eli Lusky , Boaz Eitan
发明人： Eli Lusky , Boaz Eitan
IPC分类号： G11C16/06
CPC分类号： G11C16/16 , G11C16/344 , G11C16/3445
摘要： A method includes determining groups of rows to erase together in order to minimize the margin loss associated with bake after a large number of program and erasure cycles. The method alternatively includes determining groups of rows to erase together to minimize the width of a resultant erase threshold voltage distribution, erasing the groups together, stopping erasure of a group when the group is erase verified and performing the step of erasing on those groups which were not previously erase verified.
摘要翻译：一种方法包括确定要一起擦除的行组，以便在大量程序和擦除循环之后最小化与烘烤相关的裕度损失。该方法或者包括确定一组行以擦除在一起以最小化所得到的擦除阈值电压分布的宽度，将这些组擦除在一起，当组被擦除验证时停止擦除组，并且执行擦除步骤以前没有擦除验证。

9. 发明授权

US07638850B2 Non-volatile memory structure and method of fabrication 有权
标题翻译：非易失性存储器结构和制造方法
公开(公告)号：US07638850B2
公开(公告)日：2009-12-29
申请号：US11440624
申请日：2006-05-24
申请人： Eli Lusky , Assaf Shappir , Rustom Irani , Boaz Eitan
发明人： Eli Lusky , Assaf Shappir , Rustom Irani , Boaz Eitan
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L21/28282 , H01L21/32139 , H01L27/11568 , H01L29/66833
摘要： A method for creating a non-volatile memory array includes implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering the substrate, generating increased-width polysilicon columns from the mask columns, generating bit lines in the substrate at least between the increased-width polysilicon columns and depositing oxide at least between the polysilicon columns.
摘要翻译：一种用于创建非易失性存储器阵列的方法包括至少在给定宽度的掩模列之间以及至少穿过覆盖衬底的ONO层之间的衬底中注入口袋植入物，从掩模柱产生增加宽度的多晶硅柱，产生位至少在增宽宽度的多晶硅柱之间并且至少在多晶硅柱之间沉积氧化物的衬底中的线。

10. 发明申请

US20070041249A1 Method of erasing non-volatile memory cells 有权
标题翻译：擦除非易失性存储单元的方法
公开(公告)号：US20070041249A1
公开(公告)日：2007-02-22
申请号：US11205716
申请日：2005-08-17
申请人： Eli Lusky , Boaz Eitan
发明人： Eli Lusky , Boaz Eitan
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , G11C16/344 , G11C16/3445
摘要： A method includes determining groups of rows to erase together in order to minimize the margin loss associated with bake after a large number of program and erasure cycles. The method alternatively includes determining groups of rows to erase together to minimize the width of a resultant erase threshold voltage distribution, erasing the groups together, stopping erasure of a group when the group is erase verified and performing the step of erasing on those groups which were not previously erase verified.
摘要翻译：一种方法包括确定要一起擦除的行组，以便在大量程序和擦除循环之后最小化与烘烤相关的裕度损失。该方法或者包括确定一组行以擦除在一起以最小化所得到的擦除阈值电压分布的宽度，将这些组擦除在一起，当组被擦除验证时停止擦除组，并且执行擦除步骤以前没有擦除验证。

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