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61. 发明授权

US5346587A Planarization of a gate electrode for improved gate patterning over non-planar active area isolation 失效
标题翻译：用于在非平面有源区隔离上改善栅极图案化的栅电极的平面化
公开(公告)号：US5346587A
公开(公告)日：1994-09-13
申请号：US105276
申请日：1993-08-12
申请人： Trung T. Doan , Charles H. Dennison
发明人： Trung T. Doan , Charles H. Dennison
IPC分类号： H01L21/28 , H01L21/768 , H01L21/306 , B44C1/22 , C03C15/00 , C23F1/00
CPC分类号： H01L21/28123 , H01L21/7684
摘要： The present invention is a process for providing a planarized transistor gate on a non-planar starting substrate, by depositing a layer of planarized conductive polysilicon material overlying neighboring field oxide isolation regions such that the height of the conductive polysilicon material extends above the topology of the field oxide isolation regions; depositing a layer of conductive silicide material superjacent and coextensive the conductive polysilicon material; and then patterning the planarized conductive polysilicon material and the conductive silicide material thereby forming the planarized transistor gate.
摘要翻译：本发明是一种在非平面起始衬底上提供平面化晶体管栅极的方法，通过沉积覆盖相邻场氧化物隔离区域的平坦化导电多晶硅材料层，使得导电多晶硅材料的高度延伸到场氧化物隔离区; 将导电硅化物材料层沉积在导电多晶硅材料上方并共同延伸; 然后对平坦化的导电多晶硅材料和导电硅化物材料进行构图，从而形成平坦化的晶体管栅极。

62. 发明授权

US5320880A Method of providing a silicon film having a roughened outer surface 失效
标题翻译：提供具有粗糙化外表面的硅膜的方法
公开(公告)号：US5320880A
公开(公告)日：1994-06-14
申请号：US155585
申请日：1993-11-18
申请人： Gurtej S. Sandhu , Trung T. Doan
发明人： Gurtej S. Sandhu , Trung T. Doan
IPC分类号： C23C16/24 , C23C16/505 , H01L21/02 , H01L21/205 , B05D3/06 , B05D3/02 , C23C16/00
CPC分类号： H01L28/84 , C23C16/24 , C23C16/505 , H01L21/02381 , H01L21/02532 , H01L21/0262
摘要： A method of providing a silicon film having a roughened outer surface atop a semiconductor wafer comprises: a) placing a semiconductor wafer into a plasma enhanced RF powered chemical vapor deposition reactor; and b) plasma enhanced chemical vapor depositing a layer of silicon over the wafer surface by providing quantities of a silicon source gas, a carrier gas, and TiCl.sub.4 to the reactor, the atomic ratio of the quantities of silicon source gas and TiCl.sub.4 being greater than or equal to 4 at the wafer surface; and by maintaining the reactor at a selected RF power, pressure and temperature; the RF power being supplied at a frequency of at least 5 MHz and preferably at least 10 MHz, the quantities of silicon source gas, RF power, temperature and pressure being effective to produce a predominately silicon film having an outer surface, the quantity of TiCl.sub.4 being effective to induce roughness into the outer silicon surface as compared to an outer silicon surface prepared under identical conditions but for introduction of TiCl.sub.4 but ineffective to produce a predominately titanium silicide film.
摘要翻译：提供在半导体晶片顶部具有粗糙化的外表面的硅膜的方法包括：a）将半导体晶片放置在等离子体增强的RF功率化学气相沉积反应器中; 和b）通过向反应器提供大量的硅源气体，载气和TiCl 4，等离子体增强化学气相沉积在晶片表面上的硅层，硅源气体和TiCl 4的量的原子比大于或在晶片表面等于4; 并通过将反应器维持在选定的RF功率，压力和温度; RF功率以至少5MHz，优选至少10MHz的频率提供，硅源气体的量，RF功率，温度和压力有效地产生主要具有外表面的硅膜，TiCl 4的量与在相同条件下制备的但用于引入TiCl 4但不能产生主要的硅化钛膜的外硅表面相比，有效地将粗糙度引入外硅表面。

63. 发明授权

US5278100A Chemical vapor deposition technique for depositing titanium silicide on semiconductor wafers 失效
标题翻译：用于在半导体晶片上沉积硅化钛的化学气相沉积技术
公开(公告)号：US5278100A
公开(公告)日：1994-01-11
申请号：US789585
申请日：1991-11-08
申请人： Trung T. Doan , Gurtej S. Sandhu
发明人： Trung T. Doan , Gurtej S. Sandhu
IPC分类号： H01L21/205 , H01L21/28 , H01L21/285 , H01L21/768 , H01L21/441
CPC分类号： H01L21/76855 , H01L21/285 , H01L21/28518 , H01L21/76843 , H01L21/76877 , Y10S148/147
摘要： A method of providing a conformal layer of TiSi.sub.x atop a semiconductor wafer within a chemical vapor deposition reactor includes the following steps: a) positioning a wafer within the reactor; b) injecting selected quantities of gaseous Ti(NR.sub.2).sub.4 precursor, gaseous silane and a carrier gas to within the reactor, where R is selected from the group consisting of H and a carbon containing radical, the quantities of Ti(NR.sub.2).sub.4 precursor and silane being provided in a volumetric ratio of Ti(NR.sub.2).sub.4 to silane of from 1:300 to 1:10, the quantity of carrier gas being from about 50 sccm to about 2000 sccm and comprising at least one noble gas; and c) maintaining the reactor at a selected pressure and a selected temperature which are effective for reacting the precursor and silane to deposit a film on the wafer, the film comprising a mixture of TiSi.sub.x and TiN, the selected temperature being from about 100.degree. C. to about 500.degree. C., and the selected pressure being from about 150 mTorr to about 100 Torr.
摘要翻译：在化学气相沉积反应器内提供半导体晶片顶部的TiSix共形层的方法包括以下步骤：a）将晶片定位在反应器内; b）将选定量的气态Ti（NR 2）4前体，气态硅烷和载气注入反应器内，其中R选自H和含碳基团，Ti（NR 2）4前体的量硅烷以Ti（NR 2）4与硅烷的体积比为1:300至1:10，载气量为约50sccm至约2000sccm并包含至少一种惰性气体; 以及c）将所述反应器保持在选择的压力和所选择的温度下，所述选择的温度对于使所述前体和硅烷反应以在所述晶片上沉积膜是有效的，所述膜包含TiSix和TiN的混合物，所述选定温度为约100℃ 至约500℃，并且所选择的压力为约150mTorr至约100Torr。

64. 发明授权

US5252518A Method for forming a mixed phase TiN/TiSi film for semiconductor manufacture using metal organometallic precursors and organic silane 失效
标题翻译：使用金属有机金属前体和有机硅烷形成用于半导体制造的混合TiN / TiSi膜的方法
公开(公告)号：US5252518A
公开(公告)日：1993-10-12
申请号：US845215
申请日：1992-03-03
申请人： Gurtej S. Sandhu , Trung T. Doan
发明人： Gurtej S. Sandhu , Trung T. Doan
IPC分类号： H01L21/285 , H01L21/768 , H01L23/532 , H01L21/441
CPC分类号： H01L23/53257 , H01L21/28518 , H01L21/76889 , H01L2924/0002 , Y10S148/147 , Y10S438/935
摘要： A LPCVD method for depositing a film of TiN on a semiconductor structure includes reacting an organometallic titanium source gas such as TMAT and organic silane as a reactive gas. The deposited film is a mixed phase of TiN and TiSi.sub.2 and is characterized by a low contact resistance, good step coverage and good barrier properties. The reaction is preferably carried out in a cold wall CVD reactor at relatively low temperatures (i.e. 200.degree. C.) and at pressures of from about 0.05 to 30 Torr.
摘要翻译：用于在半导体结构上沉积TiN膜的LPCVD方法包括使诸如TMAT的有机金属钛源气体和有机硅烷作为反应气体反应。沉积膜是TiN和TiSi2的混合相，其特征在于接触电阻低，阶梯覆盖率好，阻隔性好。该反应优选在相对低的温度（即200℃）和约0.05至30托的压力下在冷壁CVD反应器中进行。

65. 发明授权

US5232875A Method and apparatus for improving planarity of chemical-mechanical planarization operations 失效
标题翻译：改善化学机械平面化操作平面性的方法和装置
公开(公告)号：US5232875A
公开(公告)日：1993-08-03
申请号：US961565
申请日：1992-10-15
申请人： Mark E. Tuttle , Trung T. Doan , Angus C. Fox , Gurtej S. Sandhu , Hugh E. Stroupe
发明人： Mark E. Tuttle , Trung T. Doan , Angus C. Fox , Gurtej S. Sandhu , Hugh E. Stroupe
IPC分类号： B24B1/00 , B24B37/10 , H01L21/00 , H01L21/304
CPC分类号： B24B37/102 , H01L21/67023 , Y10S438/959
摘要： A method and apparatus for improving planarity of chemical mechanical planarization of semiconductor wafers. The wafer is affixed to the planar surface of a wafer carrier. A planar platen, on which is mounted a polishing pad, is moved about in a plane parallel to the pad surface with either an orbital, fixed-direction vibratory, or random-direction vibratory motion. In one embodiment of the invention, pressure between the surface of the wafer to be polished and the moving polishing pad is generated by the force of gravity acting on at least the wafer and the carrier; in another it is provided by a mechanical force applied normal to the wafer surface. The polishing pad is wetted with a slurry having abrasive particles suspended in a liquid which may be chemically reactive with respect to at least one material on the wafer.
摘要翻译：一种用于改善半导体晶片的化学机械平面化的平面性的方法和装置。晶片固定在晶片载体的平面上。安装有抛光垫的平面压板在与轨道，固定方向振动或随机振动运动平行的平面中移动。在本发明的一个实施例中，待抛光的晶片的表面与移动的抛光垫之间的压力通过作用于至少晶片和载体的重力产生; 在另一个中，它由通常施加于晶片表面的机械力提供。抛光垫用具有悬浮在液体中的研磨颗粒的浆液润湿，该液体可以相对于晶片上的至少一种材料具有化学反应性。

66. 发明授权

US5132236A Method of semiconductor manufacture using an inverse self-aligned mask 失效
标题翻译：使用逆自对准掩模的半导体制造方法
公开(公告)号：US5132236A
公开(公告)日：1992-07-21
申请号：US738175
申请日：1991-07-30
申请人： Trung T. Doan
发明人： Trung T. Doan
IPC分类号： H01L21/033 , H01L21/266 , H01L21/8238
CPC分类号： H01L21/266 , H01L21/0337 , H01L21/8238 , Y10S148/102
摘要： A process for fabricating a CMOS integrated circuit having both P-channel and N-channel areas in the substrate. The process forms a single self-aligned mask to define the positions of both of the channel areas on the substrate. The process includes: depositing a maskable material on the substrate; photopatterning and etching the maskable material to expose a pattern of areas on the substrate; tailoring the pattern of areas as P-channel or N-channel; depositing a second material over the maskable material and over the tailored areas of the substrate; chemically mechanically polishing (CMP) the second material to an endpoint of the maskable material; selectively etching the maskable material to expose a second pattern of areas on the substrate aligned with the first pattern of areas; and then tailoring the second pattern of areas as P-channel or N-channel.
摘要翻译：一种用于制造在衬底中具有P沟道和N沟道区域的CMOS集成电路的工艺。该过程形成单个自对准掩模以限定衬底上两个通道区域的位置。该方法包括：将可屏蔽材料沉积在基底上; 照相图案化和蚀刻可屏蔽材料以暴露衬底上的区域图案; 将区域的图案定制为P通道或N通道; 将第二材料沉积在所述可屏蔽材料上方和所述基材的所述定制区域上; 将第二材料化学机械抛光（CMP）到可屏蔽材料的端点; 选择性地蚀刻可屏蔽材料以暴露与第一图案区域对准的衬底上的第二图案区域; 然后将第二种区域划分为P信道或N信道。

67. 发明授权

US08097514B2 Method for an integrated circuit contact 失效
标题翻译：集成电路接触方法
公开(公告)号：US08097514B2
公开(公告)日：2012-01-17
申请号：US12565280
申请日：2009-09-23
申请人： Charles H. Dennison , Trung T. Doan
发明人： Charles H. Dennison , Trung T. Doan
IPC分类号： H01L21/336
CPC分类号： H01L21/31144 , H01L21/76807 , H01L21/76808 , H01L21/76829 , Y10S438/95 , Y10S438/97
摘要： A support material for a semiconductor device is processed. An opening having a width is etched into the support material for the semiconductor device using a first etch mask. A portion of the opening is etched using a second etch mask without alignment thereof to the width of the opening.
摘要翻译：对半导体器件的支撑材料进行处理。使用第一蚀刻掩模将具有宽度的开口蚀刻到用于半导体器件的支撑材料中。使用第二蚀刻掩模蚀刻开口的一部分，而不对准开口的宽度。

68. 发明授权

US07927190B2 Retaining ring with shaped surface 有权
公开(公告)号：US07927190B2
公开(公告)日：2011-04-19
申请号：US12049650
申请日：2008-03-17
申请人： Hung Chih Chen , Steven M. Zuniga , Charles C. Garretson , Douglas R. McAllister , Jian Lin , Stacy Meyer , Sidney P. Huey , Jeonghoon Oh , Trung T. Doan , Jeffrey Schmidt , Martin S. Wohlert , Kerry F. Hughes , James C. Wang , Danny Cam Toan Lu , Romain Beau De Lamenie , Venkata R. Balagani , Aden Martin Allen , Michael Jon Fong
发明人： Hung Chih Chen , Steven M. Zuniga , Charles C. Garretson , Douglas R. McAllister , Jian Lin , Stacy Meyer , Sidney P. Huey , Jeonghoon Oh , Trung T. Doan , Jeffrey Schmidt , Martin S. Wohlert , Kerry F. Hughes , James C. Wang , Danny Cam Toan Lu , Romain Beau De Lamenie , Venkata R. Balagani , Aden Martin Allen , Michael Jon Fong
IPC分类号： B24B5/00
CPC分类号： B24B37/32 , Y10T29/49815
摘要： A retaining ring can be shaped by machining or lapping the bottom surface of the ring to form a shaped profile in the bottom surface. The bottom surface of the retaining ring can include flat, sloped and curved portions. The lapping can be performed using a machine that dedicated for use in lapping the bottom surface of retaining rings. During the lapping the ring can be permitted to rotate freely about an axis of the ring. The bottom surface of the retaining ring can have curved or flat portions.

69. 发明授权

US07871934B2 Method for an integrated circuit contact 失效
标题翻译：集成电路接触方法
公开(公告)号：US07871934B2
公开(公告)日：2011-01-18
申请号：US11841906
申请日：2007-08-20
申请人： Charles H. Dennison , Trung T. Doan
发明人： Charles H. Dennison , Trung T. Doan
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/76807 , H01L21/76808 , H01L21/76829 , Y10S438/95 , Y10S438/97
摘要： A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes the steps of: forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated one or more times during the formation of multilevel metal integrated circuits.
摘要翻译：在集成电路和器件的制造中提供用于形成垂直触点的工艺。该过程消除了对精确掩模对准的需要，并允许独立于互连槽的蚀刻来控制接触孔的蚀刻。该方法包括以下步骤：在衬底的表面上形成绝缘层; 在绝缘层的表面上形成蚀刻停止层; 在蚀刻停止层中形成开口; 蚀刻到穿过蚀刻停止层中的开口的第一深度并进入绝缘层以形成互连槽; 在蚀刻停止层和槽中的表面上形成光致抗蚀剂掩模; 并且继续蚀刻通过绝缘层直到到达衬底的表面以形成接触孔。在形成多级金属集成电路期间，可以重复上述过程一次或多次。

70. 发明申请

US20100282164A1 METHODS AND SYSTEMS FOR CONTROLLING TEMPERATURE DURING MICROFEATURE WORKPIECE PROCESSING, E.G., CVD DEPOSITION 有权
标题翻译：微生物加工过程中控制温度的方法和系统，E.G.，CVD沉积
公开(公告)号：US20100282164A1
公开(公告)日：2010-11-11
申请号：US12840153
申请日：2010-07-20
申请人： Kevin L. Beaman , Trung T. Doan , Lyle D. Breiner , Ronald A. Weimer , Er-Xuan Ping , David J. Kubista , Cem Basceri , Lingyi A. Zheng
发明人： Kevin L. Beaman , Trung T. Doan , Lyle D. Breiner , Ronald A. Weimer , Er-Xuan Ping , David J. Kubista , Cem Basceri , Lingyi A. Zheng
IPC分类号： C23C16/00 , B05C11/00
CPC分类号： C23C16/00 , C23C16/46
摘要： The present disclosure provides methods and systems for controlling temperature. The method has particular utility in connection with controlling temperature in a deposition process, e.g., in depositing a heat-reflective material via CVD. One exemplary embodiment provides a method that involves monitoring a first temperature outside the deposition chamber and a second temperature inside the deposition chamber. An internal temperature in the deposition chamber can be increased in accordance with a ramp profile by (a) comparing a control temperature to a target temperature, and (b) selectively delivering heat to the deposition chamber in response to a result of the comparison. The target temperature may be determined in accordance with the ramp profile, but the control temperature in one implementation alternates between the first temperature and the second temperature.
摘要翻译：本公开提供了用于控制温度的方法和系统。该方法在沉积工艺中控制温度，例如通过CVD沉积热反射材料方面具有特别的用途。一个示例性实施例提供了一种方法，其涉及监测沉积室外的第一温度和沉积室内的第二温度。通过（a）将控制温度与目标温度进行比较，可以根据斜坡分布来增加沉积室中的内部温度，以及（b）响应于比较的结果，选择性地将热量输送到沉积室。目标温度可以根据斜坡分布来确定，但是一个实现中的控制温度在第一温度和第二温度之间交替。

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