专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5232875A Method and apparatus for improving planarity of chemical-mechanical planarization operations 失效
标题翻译：改善化学机械平面化操作平面性的方法和装置
公开(公告)号：US5232875A
公开(公告)日：1993-08-03
申请号：US961565
申请日：1992-10-15
申请人： Mark E. Tuttle , Trung T. Doan , Angus C. Fox , Gurtej S. Sandhu , Hugh E. Stroupe
发明人： Mark E. Tuttle , Trung T. Doan , Angus C. Fox , Gurtej S. Sandhu , Hugh E. Stroupe
IPC分类号： B24B1/00 , B24B37/10 , H01L21/00 , H01L21/304
CPC分类号： B24B37/102 , H01L21/67023 , Y10S438/959
摘要： A method and apparatus for improving planarity of chemical mechanical planarization of semiconductor wafers. The wafer is affixed to the planar surface of a wafer carrier. A planar platen, on which is mounted a polishing pad, is moved about in a plane parallel to the pad surface with either an orbital, fixed-direction vibratory, or random-direction vibratory motion. In one embodiment of the invention, pressure between the surface of the wafer to be polished and the moving polishing pad is generated by the force of gravity acting on at least the wafer and the carrier; in another it is provided by a mechanical force applied normal to the wafer surface. The polishing pad is wetted with a slurry having abrasive particles suspended in a liquid which may be chemically reactive with respect to at least one material on the wafer.
摘要翻译：一种用于改善半导体晶片的化学机械平面化的平面性的方法和装置。晶片固定在晶片载体的平面上。安装有抛光垫的平面压板在与轨道，固定方向振动或随机振动运动平行的平面中移动。在本发明的一个实施例中，待抛光的晶片的表面与移动的抛光垫之间的压力通过作用于至少晶片和载体的重力产生; 在另一个中，它由通常施加于晶片表面的机械力提供。抛光垫用具有悬浮在液体中的研磨颗粒的浆液润湿，该液体可以相对于晶片上的至少一种材料具有化学反应性。

2. 发明授权

US5124780A Conductive contact plug and a method of forming a conductive contact plug in an integrated circuit using laser planarization 失效
标题翻译：导电接触插塞和使用激光平面化在集成电路中形成导电接触插塞的方法
公开(公告)号：US5124780A
公开(公告)日：1992-06-23
申请号：US713187
申请日：1991-06-10
申请人： Gurtej S. Sandhu , Chang Yu , Trung T. Doan , Mark E. Tuttle
发明人： Gurtej S. Sandhu , Chang Yu , Trung T. Doan , Mark E. Tuttle
IPC分类号： H01L21/28 , H01L21/321 , H01L21/768 , H01L23/532
CPC分类号： H01L23/53223 , H01L21/32115 , H01L21/7684 , H01L21/76879 , H01L2924/0002
摘要： The invention is a method of forming a conductive contact plug and an interconnect line independent of each other. The contact plug is formed using laser planarization and a blanket etch back. The invention is also the contact plug thus formed. The contact plug and interconnect line may be fabricated with conductive materials having substantially similar methods of deposition. The integrity of the contact plug is enhanced using laser planarization.The process begins with a wafer having a dielectric layer, the upper surface of which has been planarized. A masking step defines a contact hole. An etch creates the contact hole which passes through the dielectric layer to a conductive region where contact is to be made. A first layer of conductive material is then deposited overlying the dielectric layer. A layer of material having an anti-reflective coating (ARC) (or a layer of material having a higher boiling point than the first layer) is deposited overlying the first layer. The ARC enhances the fluidity of the first layer during a subsequent laser planarization. The first layer and ARC overlying the dielectric are then laser planarized. The laser planarization is followed by a blanket etch of the first layer and ARC. The etch forms a contact plug substantially coplanar with the surface of the dielectric layer. At this juncture a second layer of conductive material may be deposited and masked to form interconnect lines for joining contact plugs.
摘要翻译：本发明是形成彼此独立的导电接触插塞和互连线的方法。接触塞是使用激光平面化和毯式回蚀而形成的。本发明也是如此形成的接触塞。接触插塞和互连线可以用具有基本相似的沉积方法的导电材料制成。使用激光平面化增强了接触插塞的完整性。该方法开始于具有介电层的晶片，其上表面已被平坦化。掩模步骤限定接触孔。蚀刻产生穿过介电层的接触孔到要进行接触的导电区域。然后将第一层导电材料沉积在电介质层上。具有抗反射涂层（ARC）（或具有比第一层沸点高的材料层）的材料层沉积在第一层上。 ARC在随后的激光平面化期间增强了第一层的流动性。然后将覆盖电介质的第一层和ARC激光平面化。激光平面化之后是第一层和ARC的毯式蚀刻。蚀刻形成与电介质层的表面基本上共面的接触插塞。在这个时刻，第二层导电材料可以被沉积和掩蔽以形成用于连接接触插塞的互连线。

3. 发明授权

US5202278A Method of forming a capacitor in semiconductor wafer processing 失效
标题翻译：在半导体晶片加工中形成电容器的方法
公开(公告)号：US5202278A
公开(公告)日：1993-04-13
申请号：US757197
申请日：1991-09-10
申请人： Viju K. Mathews , Chang Yu , Mark E. Tuttle , Trung T. Doan
发明人： Viju K. Mathews , Chang Yu , Mark E. Tuttle , Trung T. Doan
IPC分类号： H01L21/02
CPC分类号： H01L28/82 , Y10S438/964
摘要： A method of forming a capacitor in semiconductor water processing comprising the following steps: a) providing a conductively doped first layer of polysilicon atop a silicon wafer to a first thickness; b) depositing an undoped second layer of polysilicon over the conductively doped first layer of polysilicon to a second thickness, the layer of undoped polysilicon being deposited at a deposition temperature of at least 590.degree. and having an upper surface; c) impinging laser energy onto the upper surface of the second polysilicon layer at a laser fluence of 0.3 J/cm.sup.2 or greater to roughen the upper surface and thereby increase the capacitance of the second polysilicon layer; d) patterning and etching the first and second polysilicon layers to define a lower capacitor plate; e) providing a layer of capacitor dielectric atop the roughened second polysilicon layer upper surface; and f) providing a layer of conductive material atop the capacitor dielectric to define an upper capacitor plate.
摘要翻译：一种在半导体水处理中形成电容器的方法，包括以下步骤：a）在硅晶片顶上提供导电掺杂的多晶硅第一层至第一厚度; b）在导电掺杂的第一多晶硅层上沉积未掺杂的第二多晶硅层至第二厚度，所述未掺杂多晶硅层在至少590°的沉积温度下沉积并具有上表面; c）以0.3J / cm 2或更大的激光能量密度将激光能量照射到第二多晶硅层的上表面上以使上表面粗糙化，从而增加第二多晶硅层的电容; d）图案化和蚀刻第一和第二多晶硅层以限定下电容器板; e）在粗糙化的第二多晶硅层上表面的上方提供电容器电介质层; 以及f）在电容器电介质顶部提供导电材料层以限定上电容器板。

4. 发明授权

US5384284A Method to form a low resistant bond pad interconnect 失效
标题翻译：形成低电阻焊盘互连的方法
公开(公告)号：US5384284A
公开(公告)日：1995-01-24
申请号：US130225
申请日：1993-10-01
申请人： Trung T. Doan , Mark E. Tuttle
发明人： Trung T. Doan , Mark E. Tuttle
IPC分类号： H01L21/768 , H01L23/485 , H01L21/44
CPC分类号： H01L21/76838 , H01L24/05 , H01L2224/05073 , H01L2224/05124 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05669 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/14 , Y10S257/915
摘要： The present invention develops a bond pad interconnect in an integrated circuit device, by forming an aluminum pad; bonding a metal layer (such as copper (Cu), nickel (Ni), tungsten (W), gold (Au), silver (Ag) or platinum (Pt)) or a metal alloy (such as titanium nitride) to the aluminum bond pad by chemical vapor deposition or by electroless deposition; and adhering a conductive epoxy film to the metal layer, thereby forming a low resistive bond pad interconnect.
摘要翻译：本发明通过形成铝焊盘来开发集成电路器件中的接合焊盘互连; 将金属层（例如铜（Cu），镍（Ni），钨（W），金（Au），银（Ag）或铂（Pt））或金属合金（例如氮化钛）通过化学气相沉积或通过无电沉积形成键合焊盘; 并且将导电性环氧树脂膜附着在金属层上，从而形成低电阻接合焊盘互连。

5. 发明授权

US5234867A Method for planarizing semiconductor wafers with a non-circular polishing pad 失效
标题翻译：用非圆形抛光垫平面化半导体晶片的方法
公开(公告)号：US5234867A
公开(公告)日：1993-08-10
申请号：US889521
申请日：1992-05-27
申请人： Laurence D. Schultz , Mark E. Tuttle , Trung T. Doan
发明人： Laurence D. Schultz , Mark E. Tuttle , Trung T. Doan
IPC分类号： B24B7/22 , B24B13/01 , B24B37/04 , B24D11/00 , H01L21/304 , H01L21/306 , H01L21/687
CPC分类号： B24B37/04 , B24B37/26 , B24B7/228 , B24D11/00
摘要： An apparatus for planarizing semiconductor wafers in its preferred form includes a rotatable platen for polishing a surface of the semiconductor wafer and a motor for rotating the platen. A non-circular pad is mounted atop the platen to engage and polish the surface of the semiconductor wafer. A polishing head holds the surface of the semiconductor wafer in juxtaposition relative to the non-circular pad. A polishing head displacement mechanism moves the polishing head and semiconductor wafer across and past a peripheral edge of the non-circular pad to effectuate a uniform polish of the semiconductor wafer surface. Also disclosed is a method for planarizing a semiconductor surface using a non-circular polishing pad.
摘要翻译：用于以优选形式平坦化半导体晶片的装置包括用于抛光半导体晶片的表面的可旋转压板和用于旋转压板的电动机。非圆形焊盘安装在压板上方以接合和抛光半导体晶片的表面。抛光头保持半导体晶片的表面相对于非圆形焊盘并置。抛光头位移机构将抛光头和半导体晶片移动并穿过非圆形焊盘的周边边缘，以实现半导体晶片表面的均匀抛光。还公开了使用非圆形抛光垫对半导体表面进行平面化的方法。

6. 发明授权

US5021353A Split-polysilicon CMOS process incorporating self-aligned silicidation of conductive regions 失效
标题翻译：分离多晶硅CMOS工艺结合导电区域的自对准硅化物
公开(公告)号：US5021353A
公开(公告)日：1991-06-04
申请号：US485029
申请日：1990-02-26
申请人： Tyler A. Lowrey , Dermot M. Durcan , Trung T. Doan , Gordon A. Haller , Mark E. Tuttle
发明人： Tyler A. Lowrey , Dermot M. Durcan , Trung T. Doan , Gordon A. Haller , Mark E. Tuttle
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L29/665 , H01L21/823835
摘要： An improved CMOS fabrication process which uses separate masking steps to pattern N-channel and P-channel transistor gates from a single layer of conductively-doped polycrystalline silicon (poly) and incorporates self-aligned salicidation of conductive regions. The object of the improved process is to reduce the cost and improve the reliability, performance and manufacturability of CMOS devices by a process which features a dramatically reduced number of photomasking steps and which further allows self-aligned salicidation of transistor conductive regions. By processing N-channel and P-channel devices separately, the number of photomasking steps required to fabricate complete CMOS circuitry in a single-polysilicon-layer or single-metal layer process can be reduced from eleven to eight. Starting with a substrate of P-type material, N-channel devices are formed first, with unetched poly left in the future P-channel regions until N-channel processing is complete. The improved CMOS process provides the following advantages over conventional process technology: Use of a masked high-energy punch-through implant for N-channel devices is not required; individual optimization of N-channel and P-channel transistors is made possible; a lightly-doped drain (LDD) design for both N-channel and P-channel transistors is readily implemented; source/drain-to-gate offset may be changed independently for N-channel and P-channel devices; and N-channel and P-channel transistors can be independently controlled and optimized for best LDD performance and reliability.
摘要翻译：一种改进的CMOS制造工艺，其使用单独的掩模步骤来从单层导电掺杂多晶硅（poly）中的N沟道和P沟道晶体管栅极图案化，并且引入导电区域的自对准的阳离子化。改进方法的目的是降低成本，并且通过具有显着减少的光掩模步骤数目并进一步允许晶体管导电区域的自对准盐化的方法来降低CMOS器件的可靠性，性能和可制造性。通过分别处理N沟道和P沟道器件，在单多晶硅层或单金属层工艺中制造完整的CMOS电路所需的光掩模步骤的数量可以从11减少到8个。从P型材料的衬底开始，首先形成N沟道器件，在未来的P沟道区域中留下未蚀刻的聚合物，直到N沟道处理完成。与传统工艺技术相比，改进的CMOS工艺提供了以下优点：不需要对N沟道器件使用掩模的高能穿孔注入器; N通道和P沟道晶体管的单独优化成为可能; 容易实现用于N沟道和P沟道晶体管的轻掺杂漏极（LDD）设计; 源/漏 - 门偏移可以针对N沟道和P沟道器件独立地改变; 可以独立控制和优化N沟道和P沟道晶体管，以获得最佳的LDD性能和可靠性。

7. 发明授权

US5421769A Apparatus for planarizing semiconductor wafers, and a polishing pad for a planarization apparatus 失效
标题翻译：用于平坦化半导体晶片的装置和用于平坦化装置的抛光垫
公开(公告)号：US5421769A
公开(公告)日：1995-06-06
申请号：US45509
申请日：1993-04-08
申请人： Laurence D. Schultz , Mark E. Tuttle , Trung T. Doan
发明人： Laurence D. Schultz , Mark E. Tuttle , Trung T. Doan
IPC分类号： B24B7/22 , B24B13/01 , B24B37/04 , B24D11/00 , H01L21/304 , H01L21/306 , H01L21/687
CPC分类号： B24B37/04 , B24B37/26 , B24B7/228 , B24D11/00
摘要： An apparatus for planarizing semiconductor wafers in its preferred form includes a rotatable platen for polishing a surface of the semiconductor wafer and a motor for rotating the platen. A non-circular pad is mounted atop the platen to engage and polish the surface of the semiconductor wafer. A polishing head holds the surface of the semiconductor wafer in juxtaposition relative to the non-circular pad. A polishing head displacement mechanism moves the polishing head and semiconductor wafer across and past a peripheral edge of the non-circular pad to effectuate a uniform polish of the semiconductor wafer surface. Also disclosed is a method for planarizing a semiconductor surface using a non-circular polishing pad.
摘要翻译：用于以优选形式平坦化半导体晶片的装置包括用于抛光半导体晶片的表面的可旋转压板和用于旋转压板的电动机。非圆形焊盘安装在压板上方以接合和抛光半导体晶片的表面。抛光头保持半导体晶片的表面相对于非圆形焊盘并置。抛光头位移机构将抛光头和半导体晶片移动并穿过非圆形焊盘的周边边缘，以实现半导体晶片表面的均匀抛光。还公开了使用非圆形抛光垫对半导体表面进行平面化的方法。

8. 发明授权

US09153614B2 Method and apparatus for lens alignment for optically sensitive devices and systems implementing same 有权
标题翻译：用于光敏设备和实现其的系统的透镜对准的方法和装置
公开(公告)号：US09153614B2
公开(公告)日：2015-10-06
申请号：US11839377
申请日：2007-08-15
申请人： Mark E. Tuttle
发明人： Mark E. Tuttle
IPC分类号： H04N5/225 , H01L27/146 , G02B3/00
CPC分类号： H01L27/14627 , G02B3/0056 , H01L27/14618 , H01L27/14625 , H01L27/14685
摘要： Non-symmetrically located lenses are employed with semiconductor devices comprising optically active regions which are non-symmetrically located on a surface thereof. The optical axes of the lenses are aligned with the centers of the optically active regions. Wafer-level assemblies of semiconductor devices and lenses may be fabricated, mutually secured with the non-symmetrically placed lenses aligned over the non-symmetrically placed optically active regions, and singulated to form packages, such as image sensor packages. Related methods, and systems incorporating devices with non-symmetrically placed optically active regions and aligned lenses are also disclosed.
摘要翻译：使用非对称定位的透镜，其半导体器件包括非对称地位于其表面上的光学活性区域。透镜的光轴与光学活性区域的中心对准。可以制造半导体器件和透镜的晶片级组件，其中非对称放置的透镜在非对称放置的光学有源区域上对准地相互固定，并且被单个化以形成封装，例如图像传感器封装。还公开了相关方法和包括具有非对称放置的光学活性区域和对准透镜的装置的系统。

9. 发明授权

US08624711B2 Radio frequency identification device operating methods, radio frequency identification device configuration methods, and radio frequency identification devices 失效
标题翻译：射频识别装置的操作方法，射频识别装置的配置方法和射频识别装置
公开(公告)号：US08624711B2
公开(公告)日：2014-01-07
申请号：US11968561
申请日：2008-01-02
申请人： Mark E. Tuttle , John R. Tuttle
发明人： Mark E. Tuttle , John R. Tuttle
IPC分类号： H04Q5/22
CPC分类号： H01Q1/2225 , G01S13/767 , G01S13/78 , G06K7/10346 , G06K19/0723 , G06K19/0726 , G06K19/07749 , H01Q1/22 , H01Q7/00
摘要： An adjustable radio frequency data communications device has a monolithic semiconductor integrated circuit with integrated circuitry, interrogation receiving circuitry provided on the monolithic integrated circuit forming at least part of the integrated circuitry and configured to receive an interrogation signal from the interrogator unit, an antenna electrically coupled to the interrogation receiving circuitry and configured to communicate with the remote interrogator unit, a power source electrically coupled to the integrated circuitry and configured to generate operating power for the communications device, and at least one of the antenna and the interrogation receiving circuitry having reconfigurable electrical characteristics, the electrical characteristics being reconfigurable to selectively tune the at least one of the antenna and the interrogation receiving circuitry within a range of tuned and detuned states to realize a desired receiver sensitivity of the communications device. Additionally, a method for tuning receiver sensitivity and/or transmitter sensitivity according to construction of the above device is disclosed.
摘要翻译：一种可调节射频数据通信设备具有集成电路的单片半导体集成电路，在单片集成电路上提供的询问接收电路，其形成集成电路的至少一部分并且被配置为从询问器单元接收询问信号，天线电耦合所述询问接收电路被配置为与所述远程询问器单元通信;电源，其耦合到所述集成电路并且被配置为生成所述通信设备的操作功率，并且所述天线和所述询问接收电路中的至少一个具有可重新配置的电特性，电特性是可重构的，以在调谐和失谐状态的范围内选择性地调谐天线和询问接收电路中的至少一个，以实现通信设备的期望接收机灵敏度 e。此外，公开了根据上述装置的结构来调整接收机灵敏度和/或发射机灵敏度的方法。

10. 再颁专利

USRE44409E1 Method for electronic tracking of units associated with a batch 有权
标题翻译：电子跟踪与批次相关的单元的方法
公开(公告)号：USRE44409E1
公开(公告)日：2013-08-06
申请号：US13269853
申请日：2011-10-10
申请人： Ross S. Dando , Mark E. Tuttle
发明人： Ross S. Dando , Mark E. Tuttle
IPC分类号： G08B13/14
CPC分类号： G06K7/10366 , A22B5/0064 , A22B7/00 , A22B7/007 , A22C17/10 , G06K7/0008 , G06K17/0022 , G06K2017/0045 , G08B13/2434 , G08B13/2462
摘要： In one aspect, the invention encompasses a method for electronic tracking of units originating from a common source which comprises a plurality of units physically joined with one another. A first transponder is physically associated with the common source, and the source is split to separate it into three or more of the units. A second transponder is physically associated with one of the three or more units, and the second transponder sends a code. The code of the second transponder is electrically associated with an identifier of the common source. In a particular aspect, the common source is an animal carcass. A batch comprises separate units of objects that are physically joined together. RFID tags are attached to each of the units and to the batch. The codes stored in the RFID tags are electrically associated with one another in the database.
摘要翻译：一方面，本发明包括用于电子跟踪源自公共源的单元的方法，该方法包括彼此物理连接的多个单元。第一个转发器与公共源物理关联，源被拆分成三个或更多个单元。第二个转发器与三个或更多个单元中的一个物理相关联，第二个应答器发送一个代码。第二应答器的代码与公共源的标识符电连接。在一个特定方面，共同的来源是动物尸体。批次包括物理连接在一起的单独的物体单元。 RFID标签连接到每个单元和批次。存储在RFID标签中的代码在数据库中彼此电联系。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式