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1. 发明授权

US07282440B2 Integrated circuit contact 失效
标题翻译：集成电路接触
公开(公告)号：US07282440B2
公开(公告)日：2007-10-16
申请号：US10136544
申请日：2002-05-01
申请人： Charles H. Dennison , Trung T. Doan
发明人： Charles H. Dennison , Trung T. Doan
IPC分类号： H01L21/4763 , H01L21/461 , H01L21/302
CPC分类号： H01L21/31144 , H01L21/76807 , H01L21/76808 , H01L21/76829 , Y10S438/95 , Y10S438/97
摘要： A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices so manufactured. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated during the formation of multilevel metal integrated circuits.
摘要翻译：提供了在制造集成电路和如此制造的器件的制造中形成垂直触点的工艺。该过程消除了对精确掩模对准的需要，并允许独立于互连槽的蚀刻来控制接触孔的蚀刻。该方法包括在基板的表面上形成绝缘层的步骤; 在绝缘层的表面上形成蚀刻停止层; 在蚀刻停止层中形成开口; 蚀刻到穿过蚀刻停止层中的开口的第一深度并进入绝缘层以形成互连槽; 在蚀刻停止层和槽中的表面上形成光致抗蚀剂掩模; 并且继续蚀刻通过绝缘层直到到达衬底的表面以形成接触孔。在形成多级金属集成电路期间，可以重复上述过程一次或多次。

2. 发明授权

US5397908A Arrays of memory integrated circuitry 失效
标题翻译：存储器集成电路阵列
公开(公告)号：US5397908A
公开(公告)日：1995-03-14
申请号：US164896
申请日：1993-12-09
申请人： Charles H. Dennison , Trung T. Doan
发明人： Charles H. Dennison , Trung T. Doan
IPC分类号： H01L21/76 , H01L21/108 , H01L21/762 , H01L21/8234 , H01L21/8242 , H01L27/108 , H01L29/78 , H01L29/68 , H01L27/12
CPC分类号： H01L27/10852 , H01L21/76224 , H01L21/823481 , Y10S148/05
摘要： A semiconductor processing device isolation method includes: a) providing non-LOCOS insulating device isolation blocks by trench and refill technique on a substrate to define recessed moat volume therebetween; b) providing gate dielectric within the moat volume; c) providing a layer of electrically conductive material over the substrate and gate dielectric to a thickness sufficient to completely fill the moat volume between adjacent isolation blocks; d) chemical-mechanical polishing the layer of electrically conductive material to provide a planarized upper electrically conductive material surface; e) photopatterning and etching the layer of electrically conductive material to provide an electrically conductive runner which overlies a plurality of the isolation blocks and to selectively remove the electrically conductive material from within selected regions of moat volume to define field effect transistor gates within the moat volume; and f) providing conductivity enhancing impurity through the selected regions of moat volume into the substrate to define source/drain regions adjacent the field effect transistor gates. The invention also includes an array of memory integrated circuitry.
摘要翻译：半导体处理器件隔离方法包括：a）通过沟槽和再填充技术在衬底上提供非LOCOS绝缘器件隔离块，以在其间限定凹陷的沟槽体积; b）在护城河容积内提供栅极电介质; c）在衬底和栅极电介质上提供一层导电材料，其厚度足以完全填充相邻隔离块之间的护城河体积; d）化学机械抛光导电材料层以提供平坦化的上导电材料表面; e）对导电材料层进行光图案化和蚀刻，以提供覆盖在多个隔离块上的导电浇道，并且选择性地从导流槽体积的选定区域内去除导电材料，以在护城河体积内限定场效应晶体管栅极 ; 以及f）通过所选择的沟槽体积的区域提供导电性增强杂质到衬底中以限定与场效应晶体管栅极相邻的源极/漏极区域。本发明还包括一组存储器集成电路。

3. 发明授权

US5346587A Planarization of a gate electrode for improved gate patterning over non-planar active area isolation 失效
标题翻译：用于在非平面有源区隔离上改善栅极图案化的栅电极的平面化
公开(公告)号：US5346587A
公开(公告)日：1994-09-13
申请号：US105276
申请日：1993-08-12
申请人： Trung T. Doan , Charles H. Dennison
发明人： Trung T. Doan , Charles H. Dennison
IPC分类号： H01L21/28 , H01L21/768 , H01L21/306 , B44C1/22 , C03C15/00 , C23F1/00
CPC分类号： H01L21/28123 , H01L21/7684
摘要： The present invention is a process for providing a planarized transistor gate on a non-planar starting substrate, by depositing a layer of planarized conductive polysilicon material overlying neighboring field oxide isolation regions such that the height of the conductive polysilicon material extends above the topology of the field oxide isolation regions; depositing a layer of conductive silicide material superjacent and coextensive the conductive polysilicon material; and then patterning the planarized conductive polysilicon material and the conductive silicide material thereby forming the planarized transistor gate.
摘要翻译：本发明是一种在非平面起始衬底上提供平面化晶体管栅极的方法，通过沉积覆盖相邻场氧化物隔离区域的平坦化导电多晶硅材料层，使得导电多晶硅材料的高度延伸到场氧化物隔离区; 将导电硅化物材料层沉积在导电多晶硅材料上方并共同延伸; 然后对平坦化的导电多晶硅材料和导电硅化物材料进行构图，从而形成平坦化的晶体管栅极。

4. 发明授权

US08097514B2 Method for an integrated circuit contact 失效
标题翻译：集成电路接触方法
公开(公告)号：US08097514B2
公开(公告)日：2012-01-17
申请号：US12565280
申请日：2009-09-23
申请人： Charles H. Dennison , Trung T. Doan
发明人： Charles H. Dennison , Trung T. Doan
IPC分类号： H01L21/336
CPC分类号： H01L21/31144 , H01L21/76807 , H01L21/76808 , H01L21/76829 , Y10S438/95 , Y10S438/97
摘要： A support material for a semiconductor device is processed. An opening having a width is etched into the support material for the semiconductor device using a first etch mask. A portion of the opening is etched using a second etch mask without alignment thereof to the width of the opening.
摘要翻译：对半导体器件的支撑材料进行处理。使用第一蚀刻掩模将具有宽度的开口蚀刻到用于半导体器件的支撑材料中。使用第二蚀刻掩模蚀刻开口的一部分，而不对准开口的宽度。

5. 发明授权

US07871934B2 Method for an integrated circuit contact 失效
标题翻译：集成电路接触方法
公开(公告)号：US07871934B2
公开(公告)日：2011-01-18
申请号：US11841906
申请日：2007-08-20
申请人： Charles H. Dennison , Trung T. Doan
发明人： Charles H. Dennison , Trung T. Doan
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/76807 , H01L21/76808 , H01L21/76829 , Y10S438/95 , Y10S438/97
摘要： A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes the steps of: forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated one or more times during the formation of multilevel metal integrated circuits.
摘要翻译：在集成电路和器件的制造中提供用于形成垂直触点的工艺。该过程消除了对精确掩模对准的需要，并允许独立于互连槽的蚀刻来控制接触孔的蚀刻。该方法包括以下步骤：在衬底的表面上形成绝缘层; 在绝缘层的表面上形成蚀刻停止层; 在蚀刻停止层中形成开口; 蚀刻到穿过蚀刻停止层中的开口的第一深度并进入绝缘层以形成互连槽; 在蚀刻停止层和槽中的表面上形成光致抗蚀剂掩模; 并且继续蚀刻通过绝缘层直到到达衬底的表面以形成接触孔。在形成多级金属集成电路期间，可以重复上述过程一次或多次。

6. 发明授权

US06573601B2 Integrated circuit contact 失效
公开(公告)号：US06573601B2
公开(公告)日：2003-06-03
申请号：US10136126
申请日：2002-05-01
申请人： Charles H. Dennison , Trung T. Doan
发明人： Charles H. Dennison , Trung T. Doan
IPC分类号： H01L2348
CPC分类号： H01L21/31144 , H01L21/76807 , H01L21/76808 , H01L21/76829 , Y10S438/95 , Y10S438/97
摘要： A process for forming vertical contacts in the manufacture of integrated circuits, and devices so manufactured. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes the steps of: forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated one or more times during the formation of multilevel metal integrated circuits.

7. 发明授权

US07315082B2 Semiconductor device having integrated circuit contact 失效
标题翻译：具有集成电路接触的半导体器件
公开(公告)号：US07315082B2
公开(公告)日：2008-01-01
申请号：US10443471
申请日：2003-05-22
申请人： Charles H. Dennison , Trung T. Doan
发明人： Charles H. Dennison , Trung T. Doan
IPC分类号： H01L23/48
CPC分类号： H01L21/31144 , H01L21/76807 , H01L21/76808 , H01L21/76829 , Y10S438/95 , Y10S438/97
摘要： A process for forming vertical contacts in the manufacture of integrated circuits, and devices so manufactured, is disclosed. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes the steps of: forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated one or more times during the formation of multilevel metal integrated circuits.
摘要翻译：公开了一种用于在集成电路的制造中形成垂直触点的工艺以及如此制造的器件。该过程消除了对精确掩模对准的需要，并允许独立于互连槽的蚀刻来控制接触孔的蚀刻。该方法包括以下步骤：在衬底的表面上形成绝缘层; 在绝缘层的表面上形成蚀刻停止层; 在蚀刻停止层中形成开口; 蚀刻到穿过蚀刻停止层中的开口的第一深度并进入绝缘层以形成互连槽; 在蚀刻停止层和槽中的表面上形成光致抗蚀剂掩模; 并且继续蚀刻通过绝缘层直到到达衬底的表面以形成接触孔。在形成多级金属集成电路期间，可以重复上述过程一次或多次。

8. 发明授权

US06414392B1 Integrated circuit contact 有权
标题翻译：集成电路接触
公开(公告)号：US06414392B1
公开(公告)日：2002-07-02
申请号：US09569578
申请日：2000-05-10
申请人： Charles H. Dennison , Trung T. Doan
发明人： Charles H. Dennison , Trung T. Doan
IPC分类号： H01L2348
CPC分类号： H01L21/31144 , H01L21/76807 , H01L21/76808 , H01L21/76829 , Y10S438/95 , Y10S438/97
摘要： A process for forming vertical contacts in the manufacture of integrated circuits, and devices so manufactured. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes the steps of: forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated one or more times during the formation of multi-level metal integrated circuits.
摘要翻译：在集成电路的制造中形成垂直触点的工艺以及如此制造的器件。该过程消除了对精确掩模对准的需要，并允许独立于互连槽的蚀刻来控制接触孔的蚀刻。该方法包括以下步骤：在衬底的表面上形成绝缘层; 在绝缘层的表面上形成蚀刻停止层; 在蚀刻停止层中形成开口; 蚀刻到穿过蚀刻停止层中的开口的第一深度并进入绝缘层以形成互连槽; 在蚀刻停止层和槽中的表面上形成光致抗蚀剂掩模; 并且继续蚀刻通过绝缘层直到到达衬底的表面以形成接触孔。在形成多级金属集成电路期间，可以重复上述过程一次或多次。

9. 发明授权

US06221779B1 Self-aligned process for making contacts to silicon substrates during the manufacture of integrated circuits therein 失效
标题翻译：在其中制造集成电路期间与硅衬底接触的自对准工艺
公开(公告)号：US06221779B1
公开(公告)日：2001-04-24
申请号：US09099047
申请日：1998-06-17
申请人： Charles H Dennison , Trung T. Doan
发明人： Charles H Dennison , Trung T. Doan
IPC分类号： H01L21311
CPC分类号： H01L21/31144 , H01L21/76807 , H01L21/76808 , H01L21/76829 , Y10S438/95 , Y10S438/97
摘要： A process for forming vertical contacts in the manufacture of integrated circuits, and devices so manufactured. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes the steps of: forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated one or more times during the formation of multi-level metal integrated circuits.
摘要翻译：在集成电路的制造中形成垂直触点的工艺以及如此制造的器件。该过程消除了对精确掩模对准的需要，并允许独立于互连槽的蚀刻来控制接触孔的蚀刻。该方法包括以下步骤：在衬底的表面上形成绝缘层; 在绝缘层的表面上形成蚀刻停止层; 在蚀刻停止层中形成开口; 蚀刻到穿过蚀刻停止层中的开口的第一深度并进入绝缘层以形成互连槽; 在蚀刻停止层和槽中的表面上形成光致抗蚀剂掩模; 并且继续蚀刻通过绝缘层直到到达衬底的表面以形成接触孔。在形成多级金属集成电路期间，可以重复上述过程一次或多次。

10. 再颁专利

USRE37104E1 Planarization of a gate electrode for improved gate patterning over non-planar active area isolation 失效
标题翻译：用于在非平面有源区隔离上改善栅极图案化的栅电极的平面化
公开(公告)号：USRE37104E1
公开(公告)日：2001-03-20
申请号：US08710287
申请日：1996-09-12
申请人： Trung T. Doan , Charles H. Dennison
发明人： Trung T. Doan , Charles H. Dennison
IPC分类号： H01L21306
CPC分类号： H01L21/28123 , H01L21/7684
摘要： The present invention is a process for providing a planarized transistor gate on a non-planar starting substrate, by depositing a layer of planarized conductive polysilicon material overlying neighboring field oxide isolation regions such that the height of the conductive polysilicon material extends above the topology topography of the field oxide isolation regions; depositing a layer of conductive silicide material superjacent and coextensive the conductive polysilicon material; and then patterning the planarized conductive polysilicon material and the conductive silicide material thereby forming the planarized transistor gate.
摘要翻译：本发明是一种在非平面起始衬底上提供平面化晶体管栅极的方法，通过沉积覆盖相邻场氧化物隔离区域的平坦化导电多晶硅材料层，使得导电多晶硅材料的高度延伸到拓扑场地氧化物隔离区的形貌; 将导电硅化物材料层沉积在导电多晶硅材料上方并共同延伸; 然后对平坦化的导电多晶硅材料和导电硅化物材料进行构图，从而形成平坦化的晶体管栅极。

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