专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明申请

US20080250279A1 Method of Increasing Path Coverage in Transition Test Generation 失效
标题翻译：在过渡测试生成中增加路径覆盖的方法
公开(公告)号：US20080250279A1
公开(公告)日：2008-10-09
申请号：US11696981
申请日：2007-04-05
申请人： Gary D. Grise , David J. Hathaway , Vikram Iyengar
发明人： Gary D. Grise , David J. Hathaway , Vikram Iyengar
IPC分类号： G01R31/28
CPC分类号： G01R31/31715 , G01R31/31707 , G01R31/318328
摘要： A method for automatically generating test patterns for digital logic circuitry using an automatic test pattern generation tool. The method includes generating test patterns and applying faulty behavior to various paths within the digital logic circuitry. As each circuit path is tested, tested circuit nodes along the circuit path are marked as “exercised.” Subsequent test paths are assembled by avoiding marked circuit nodes. In this manner, coverage of paths tested may be increased and many circuit nodes can be tested efficiently.
摘要翻译：一种使用自动测试图案生成工具自动生成数字逻辑电路测试图案的方法。该方法包括生成测试模式并将故障行为应用于数字逻辑电路内的各种路径。随着每个电路路径的测试，沿电路路径的测试电路节点被标记为“行使”。通过避免标记的电路节点组装后续测试路径。以这种方式，可以增加测试路径的覆盖范围，并且可以有效地测试许多电路节点。

52. 发明申请

US20080216036A1 SLACK SENSITIVITY TO PARAMETER VARIATION BASED TIMING ANALYSIS 有权
公开(公告)号：US20080216036A1
公开(公告)日：2008-09-04
申请号：US12122451
申请日：2008-05-16
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Jeffrey H. Oppold , Anthony D. Polson
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Jeffrey H. Oppold , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.

53. 发明授权

US07404163B2 Static timing slacks analysis and modification 有权
标题翻译：静态定时松散分析和修改
公开(公告)号：US07404163B2
公开(公告)日：2008-07-22
申请号：US11277385
申请日：2006-03-24
申请人： Thomas B. Chadwick, Jr. , Margaret R. Charlebois , David J. Hathaway , Jason E. Rotella , Douglas W. Stout , Ivan L. Wemple
发明人： Thomas B. Chadwick, Jr. , Margaret R. Charlebois , David J. Hathaway , Jason E. Rotella , Douglas W. Stout , Ivan L. Wemple
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method, system and computer program product for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply are disclosed. A static timing slack analysis is performed at a selected endpoint in an IC to obtain a candidate timing path leading to the endpoint with a worst static timing slack. A transient static timing slack is determined for the candidate timing path for each clock cycle of a clock signal under the transient power supply. The determined transient static timing slack is used to adjust the timing of the IC and to modify the static timing slack of the candidate timing path.
摘要翻译：公开了一种用于在具有瞬态电源的集成电路（IC）的设计的静态时序分析中分析和修改定时路径的静态定时松弛的方法，系统和计算机程序产品。在IC中的选定端点处执行静态时序松弛分析，以获得以最差的静态时序松弛通向端点的候选定时路径。瞬态电源下的时钟信号的每个时钟周期的候选定时路径确定瞬态静态时序松弛。使用确定的瞬态静态时序松弛来调整IC的定时并修改候选定时路径的静态时序松弛。

54. 发明申请

US20080172638A1 METHOD OF OPTIMIZING HIERARCHICAL VERY LARGE SCALE INTEGRATION (VLSI) DESIGN BY USE OF CLUSTER-BASED LOGIC CELL CLONING 审中-公开
标题翻译：通过使用基于群集的逻辑单元克隆优化分层级非常大规模集成（VLSI）设计的方法
公开(公告)号：US20080172638A1
公开(公告)日：2008-07-17
申请号：US11623122
申请日：2007-01-15
申请人： Michael S. Gray , David J. Hathaway , Jason D. Hibbeler , Robert F. Walker , Xin Yuan
发明人： Michael S. Gray , David J. Hathaway , Jason D. Hibbeler , Robert F. Walker , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method of optimizing hierarchical very large scale integration (VLSI) design by use of cluster-based cell cloning. The method of the present invention provides improved yield or migration by reusing cells in order to reduce the number of unique instances of at least one of the reused cells. The method performs hierarchal optimization on the reduced set of clones (i.e., clusters). The method of the present disclosure includes, but is not limited to, the steps of setting the initial clustering parameters; assembling the physical design from existing reused cells; for each cell type, performing a full cloning operation in order to create a full set of duplicate cells; for each cell type, performing a full optimization of the design; for each cell type, performing an analyses of all cell environments and performing a clustering operation; and analyzing the overall results in order to determine whether the optimization objectives are achieved.
摘要翻译：通过使用基于簇的细胞克隆来优化分级超大规模集成（VLSI）设计的方法。本发明的方法通过重新使用细胞来提供改善的产量或迁移，以减少至少一个重复使用的细胞的唯一实例的数量。该方法对减少的克隆集合（即，簇）执行层次优化。本公开的方法包括但不限于设置初始聚类参数的步骤; 从现有的重复使用的电池组装物理设计; 对于每个单元格类型，执行完全克隆操作以便创建一整套重复的单元格; 对于每个单元格类型，执行设计的全面优化; 对于每个单元类型，执行所有单元环境的分析并执行聚类操作; 并分析总体结果，以确定是否实现优化目标。

55. 发明授权

US07280939B2 System and method of analyzing timing effects of spatial distribution in circuits 有权
标题翻译：分析电路中空间分布的时序效应的系统和方法
公开(公告)号：US07280939B2
公开(公告)日：2007-10-09
申请号：US10709362
申请日：2004-04-29
申请人： David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
发明人： David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
IPC分类号： G06F11/30 , G06F9/45
CPC分类号： G06F17/5031
摘要： Systems and methods are provided for analyzing the timing of circuits, including integrated circuits, by taking into account the location of cells or elements in the paths or logic cones of the circuit. In one embodiment, a bounding region may be defined around cells or elements of interest, and the size of the bounding region may be used to calculate a timing slack variation factor. The size of the bounding region may be adjusted to account for variability in timing delays. In other embodiments, centroids may be calculated using either the location or the delay-weighted location of elements or cells within the path or cone and the centroids used to calculate timing slack variation factor. The timing slack variation factors are used to calculate a new timing slack for the path or logic cone of the circuit.
摘要翻译：提供了系统和方法，用于通过考虑电路的路径或逻辑锥中的单元或元件的位置来分析电路的定时，包括集成电路。在一个实施例中，可以围绕感兴趣的细胞或元件限定边界区域，并且可以使用边界区域的大小来计算定时松弛变化因子。可以调整边界区域的大小以考虑定时延迟的变化。在其他实施例中，可以使用路径或锥体内的元件或单元的位置或延迟加权位置以及用于计算定时松弛变化因子的质心来计算质心。定时松弛变化因子用于计算电路的路径或逻辑锥的新的定时松弛。

56. 发明授权

US07117466B2 System and method for correlated process pessimism removal for static timing analysis 失效
标题翻译：静态时序分析相关过程悲观消除的系统和方法
公开(公告)号：US07117466B2
公开(公告)日：2006-10-03
申请号：US10665273
申请日：2003-09-18
申请人： Kerim Kalafala , Peihua Qi , David J. Hathaway , Alexander J. Suess , Chandramouli Visweswariah
发明人： Kerim Kalafala , Peihua Qi , David J. Hathaway , Alexander J. Suess , Chandramouli Visweswariah
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method of removing pessimism in static timing analysis is described. Delays are expressed as a function of discrete parameter settings allowing for both local and global variation to be taken in to account. Based on a specified target slack, each failing timing test is examined to determine a consistent set of parameter settings which produces the worst possible slack. The analysis is performed on a path basis. By considering only parameters which are in common to a particular data/clock path-pair, the number of process combinations that need to be explored is reduced when compared to analyzing all combinations of the global parameter settings. Further, if parameters are separable and linear, worst-case variable assignments for a particular clock/data path pair can be computed in linear time by independently assigning each parameter value. In addition, if available, the incremental delay change with respect to each physically realizable process variable may be used to project the worst-case variable assignment on a per-path basis without the need for performing explicit corner enumeration.
摘要翻译：描述了静态时序分析中消除悲观情绪的方法。延迟表示为离散参数设置的函数，允许将本地和全局变量都用于账户。根据指定的目标松弛，检查每个失败的定时测试，以确定一组一致的参数设置，从而产生最差的松弛。分析以路径为基础进行。通过仅考虑与特定数据/时钟路径对共同的参数，与分析全局参数设置的所有组合相比，需要探索的进程组合的数量减少。此外，如果参数是可分离的和线性的，则通过独立地分配每个参数值，可以在线性时间内计算特定时钟/数据路径对的最差情况变量分配。另外，如果可用，可以使用相对于每个物理上可实现的过程变量的增量延迟变化来在每个路径基础上投射最坏情况的变量赋值，而不需要执行明确的角点枚举。

57. 发明授权

US07093208B2 Method for tuning a digital design for synthesized random logic circuit macros in a continuous design space with optional insertion of multiple threshold voltage devices 失效
标题翻译：用于在连续设计空间中调整合成随机逻辑电路宏的数字设计的方法，并可选择插入多个阈值电压器件
公开(公告)号：US07093208B2
公开(公告)日：2006-08-15
申请号：US10842589
申请日：2004-05-10
申请人： Patrick M. Williams , Ee K. Cho , David J. Hathaway , Mei-Ting Hsu , Lawrence K. Lange , Gregory A. Northrop , Chandramouli Visweswariah , Cindy ShuiKing Washburn , Jun Zhou
发明人： Patrick M. Williams , Ee K. Cho , David J. Hathaway , Mei-Ting Hsu , Lawrence K. Lange , Gregory A. Northrop , Chandramouli Visweswariah , Cindy ShuiKing Washburn , Jun Zhou
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A Digital Design Method which may be automated is for obtaining timing closure in the design of large, complex, high-performance digital integrated circuits. The methodincludes the use of a tuner on random logic macros that adjusts transistor sizes in a continuous domain. To accommodate this tuning, logic gates are mapped to parameterized cells for the tuning and then back to fixed gates after the tuning. Tuning is constrained in such a way as to minimize “binning errors” when the design is mapped back to fixed cells. Further, the critical sections of the circuit are marked in order to make the optimization more effective and to fit within the problem-size constraints of the tuner. A specially formulated objective function is employed during the tuning to promote faster global timing convergence, despite possibly incorrect initial timing budgets. The specially formulated objective function targets all paths that are failing timing, with appropriate weighting, rather than just targeting the most critical path. Finally, the addition of multiple threshold voltage gates allows for increased performance while limiting leakage power.
摘要翻译：可以自动化的数字设计方法是在大型，复杂，高性能数字集成电路的设计中获得定时关闭。该方法包括在随机逻辑宏中使用调谐器来调整连续域中的晶体管尺寸。为了适应这种调谐，逻辑门被映射到用于调谐的参数化单元，然后在调谐之后返回到固定门。调整受限于将设计映射回固定单元格时最小化“合并错误”。此外，电路的关键部分被标记以便使优化更有效并且适应调谐器的问题尺寸约束。在调整期间采用了特别制定的目标函数，以促进更快的全局时序收敛，尽管可能不正确的初始时间预算。特别制定的目标函数针对所有失败时机的路径，以适当的权重，而不是仅针对最关键的路径。最后，添加多个阈值电压门允许提高性能，同时限制漏电功率。

58. 发明授权

US07089143B2 Method and system for evaluating timing in an integrated circuit 失效
标题翻译：用于评估集成电路中的定时的方法和系统
公开(公告)号：US07089143B2
公开(公告)日：2006-08-08
申请号：US10709361
申请日：2004-04-29
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
IPC分类号： G01M19/00 , G06F9/45
CPC分类号： G01R31/3016
摘要： Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An adjusted timing slack is calculated using the delay contributions of elements having dissimilar delays. In some embodiments, the delay contributions of elements having dissimilar delays are root sum squared. Embodiments of the invention provide methods for reducing the pessimism due to both cell-based and wire-dependent delays. The delays considered in embodiments of the invention may include delays due to the location of elements in a path.
摘要翻译：用于分析集成电路中的定时并减少静态时序分析（STA）中定时松弛计算中的悲观情况的方法。该方法涉及分组和消除在早期和晚期电路路径中具有类似延迟的元件的延迟贡献。使用具有不同延迟的元件的延迟贡献来计算调整的定时松弛。在一些实施例中，具有不同延迟的元件的延迟贡献是根和平方。本发明的实施例提供了用于减少由于基于单元和线依赖的延迟引起的悲观的方法。在本发明的实施例中考虑的延迟可以包括由于路径中的元件的位置而导致的延迟。

59. 发明授权

US07003747B2 Method of achieving timing closure in digital integrated circuits by optimizing individual macros 失效
标题翻译：通过优化单个宏来实现数字集成电路中的时序闭合的方法
公开(公告)号：US07003747B2
公开(公告)日：2006-02-21
申请号：US10435824
申请日：2003-05-12
申请人： Jun Zhou , David J. Hathaway , Chandramouli Visweswariah , Patrick M. Williams
发明人： Jun Zhou , David J. Hathaway , Chandramouli Visweswariah , Patrick M. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/505 , G06F2217/84
摘要： Disclosed is a method for enhanced efficiency and effectiveness in achieving timing closure of large, complex, high-performance digital integrated circuits. Circuit macros are re-optimized and re-tuned in the timing closure loop by means of a reformulated objective function that allows the optimizer to improve the slack of all signals rather than just the most critical one(s). The incentive to improve the timing of a sub-critical signal is a diminishing function of the criticality of the signal. Thus all signals are improved during the optimization, with the highest incentive to improve on the most critical signals, leading to faster and more effective overall timing closure.
摘要翻译：公开了一种用于提高大型，复杂，高性能数字集成电路的定时闭合的效率和有效性的方法。电路宏通过重新配置的目标函数在时序闭合循环中重新优化和重新调整，允许优化器改善所有信号的松弛，而不仅仅是最关键的。改善次临界信号时序的动机是信号临界性的递减函数。因此，在优化期间，所有信号都得到改进，最高激励措施可以改善最关键的信号，从而实现更快更有效的整体时序收敛。

60. 发明授权

US06615395B1 Method for handling coupling effects in static timing analysis 失效
标题翻译：在静态时序分析中处理耦合效应的方法
公开(公告)号：US06615395B1
公开(公告)日：2003-09-02
申请号：US09467208
申请日：1999-12-20
申请人： David J. Hathaway , Chandramouli V. Kashyap , Byron L. Krauter , Sharad Mehrotra , Alexander J. Suess
发明人： David J. Hathaway , Chandramouli V. Kashyap , Byron L. Krauter , Sharad Mehrotra , Alexander J. Suess
IPC分类号： G06F1750
CPC分类号： G06F17/5031
摘要： A method for performing a static timing analysis on an integrated circuit chip or module taking into account the effect of wiring interconnection coupling is described. The wiring interactions are modeled as appropriate equivalent grounded capacitances, allowing traditional delay calculation methods to be applied. The method includes the steps of assigning a pessimistic value to the wiring coupling interaction between nets forming the integrated circuit chip; performing the static timing analysis using computed timing parameters which are a function of net capacitance, the net capacitance being based on the pessimistic value of the coupling interaction between the nets; updating the net capacitance of selected nets based on 1) an overlap between an arrival time window of each of the selected nets and a possible arrival time window of each of the other nets which are coupled to the each of selected nets, and 2) on the slew of each of the selected nets and the slew of each of the other nets which are coupled to the selected nets; and updating the static timing analysis based on the updated net capacitances of the selected nets.
摘要翻译：描述了考虑到布线互连耦合的影响，在集成电路芯片或模块上执行静态时序分析的方法。布线相互作用被建模为适当的等效接地电容，允许应用传统的延迟计算方法。该方法包括以下步骤：为形成集成电路芯片的网络之间的布线耦合交互分配悲观值; 使用作为净电容的函数的计算定时参数来执行静态时序分析，净电容基于网络之间的耦合相互作用的悲观值; 基于以下步骤更新所选网络的净电容：1）每个所选网络的到达时间窗口与耦合到所选网络中的每一个网络的每个其它网络的可能到达时间窗口之间的重叠，以及2）所选择的网络中的每一个的转换以及耦合到所选择的网络的每个其他网络的转换; 以及基于所选网络的更新的净电容来更新静态时序分析。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式