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1. 发明授权

US06615395B1 Method for handling coupling effects in static timing analysis 失效
标题翻译：在静态时序分析中处理耦合效应的方法
公开(公告)号：US06615395B1
公开(公告)日：2003-09-02
申请号：US09467208
申请日：1999-12-20
申请人： David J. Hathaway , Chandramouli V. Kashyap , Byron L. Krauter , Sharad Mehrotra , Alexander J. Suess
发明人： David J. Hathaway , Chandramouli V. Kashyap , Byron L. Krauter , Sharad Mehrotra , Alexander J. Suess
IPC分类号： G06F1750
CPC分类号： G06F17/5031
摘要： A method for performing a static timing analysis on an integrated circuit chip or module taking into account the effect of wiring interconnection coupling is described. The wiring interactions are modeled as appropriate equivalent grounded capacitances, allowing traditional delay calculation methods to be applied. The method includes the steps of assigning a pessimistic value to the wiring coupling interaction between nets forming the integrated circuit chip; performing the static timing analysis using computed timing parameters which are a function of net capacitance, the net capacitance being based on the pessimistic value of the coupling interaction between the nets; updating the net capacitance of selected nets based on 1) an overlap between an arrival time window of each of the selected nets and a possible arrival time window of each of the other nets which are coupled to the each of selected nets, and 2) on the slew of each of the selected nets and the slew of each of the other nets which are coupled to the selected nets; and updating the static timing analysis based on the updated net capacitances of the selected nets.
摘要翻译：描述了考虑到布线互连耦合的影响，在集成电路芯片或模块上执行静态时序分析的方法。布线相互作用被建模为适当的等效接地电容，允许应用传统的延迟计算方法。该方法包括以下步骤：为形成集成电路芯片的网络之间的布线耦合交互分配悲观值; 使用作为净电容的函数的计算定时参数来执行静态时序分析，净电容基于网络之间的耦合相互作用的悲观值; 基于以下步骤更新所选网络的净电容：1）每个所选网络的到达时间窗口与耦合到所选网络中的每一个网络的每个其它网络的可能到达时间窗口之间的重叠，以及2）所选择的网络中的每一个的转换以及耦合到所选择的网络的每个其他网络的转换; 以及基于所选网络的更新的净电容来更新静态时序分析。

2. 发明授权

US08601053B2 Multi-chassis fabric-backplane enterprise servers 有权
标题翻译：多机架式背板企业服务器
公开(公告)号：US08601053B2
公开(公告)日：2013-12-03
申请号：US13007913
申请日：2011-01-17
申请人： Sharad Mehrotra , Nakul Pratap Saraiya , Thomas Dean Lovett , Cosmos Nicolaou , Mangesh Shingane , Yuri Finkelstein , Curtis M. Collins , Geoffrey H. Hanson
发明人： Sharad Mehrotra , Nakul Pratap Saraiya , Thomas Dean Lovett , Cosmos Nicolaou , Mangesh Shingane , Yuri Finkelstein , Curtis M. Collins , Geoffrey H. Hanson
IPC分类号： G06F15/16
CPC分类号： H04L12/4641 , H04L49/357 , H04L49/45 , H04L49/602 , H04L49/70
摘要： Multi-chassis fabric-backplane enterprise servers include a plurality of chassis managed collectively to form one or more provisioned servers. A central client coordinates gathering of provisioning and management information from the chassis, and arranges for distribution of control information to the chassis. One of the chassis may perform as a host or proxy with respect to information and control communication between the client and the chassis. Server provisioning and management information and commands move throughout the chassis via an Open Shortest Path First (OSPF) protocol. Alternatively, the client may establish individual communication with a subset of the chassis, and directly communicate with chassis in the subset. Server provisioning and management information includes events generated when module status changes, such as when a module is inserted and becomes available, and when a module fails and is no longer available. Each chassis includes a switch fabric enabling communication between chassis modules.
摘要翻译：多机架式背板企业服务器包括集体管理的多个机箱，以形成一个或多个配置的服务器。中央客户端协调从机箱收集供应和管理信息，并安排向机箱分配控制信息。其中一个机箱可以作为客户机和机箱之间的信息和控制通信的主机或代理。服务器配置和管理信息和命令通过开放最短路径优先（OSPF）协议在整个机箱中移动。或者，客户端可以建立与机箱的子集的单独通信，并且直接与子集中的机箱进行通信。服务器配置和管理信息包括当模块状态更改时生成的事件，例如模块插入并变为可用时以及模块何时不能使用。每个机架包括一个交换机结构，实现机箱模块之间的通信。

3. 发明授权

US08145824B1 Cell-switched inter-partition communications 有权
标题翻译：单元交换分区间通信
公开(公告)号：US08145824B1
公开(公告)日：2012-03-27
申请号：US12833999
申请日：2010-07-11
申请人： Sharad Mehrotra , Thomas Dean Lovett , Cosmos Nicolaou , Nakul Pratap Saraiya , Shreyas B. Shah
发明人： Sharad Mehrotra , Thomas Dean Lovett , Cosmos Nicolaou , Nakul Pratap Saraiya , Shreyas B. Shah
IPC分类号： G06F13/24
CPC分类号： G06F13/4022 , H04L49/357 , H04L49/45 , H04L49/602 , H04L49/70
摘要： Pluggable modules communicate via a switch fabric dataplane accessible via a backplane. Various embodiments are comprised of varying numbers and arrangements of the pluggable modules in accordance with a system architecture that provides for provisioning virtual servers and clusters of servers from underlying hardware and software resources. The system architecture is a unifying solution for applications requiring a combination of computation and networking performance. Resources may be pooled, scaled, and reclaimed dynamically for new purposes as requirements change, using dynamic reconfiguration of virtual computing and communication hardware and software.
摘要翻译：可插拔模块通过可通过背板访问的交换机结构数据板进行通信。根据提供从底层硬件和软件资源提供虚拟服务器和服务器集群的系统架构，各种实施例包括可插拔模块的不同数量和布置。系统架构是需要组合计算和网络性能的应用程序的统一解决方案。资源可以通过虚拟计算和通信硬件和软件的动态重新配置，为需求变化而动态地为新目的进行池化，缩放和回收。

4. 发明授权

US08001128B2 Selection of a set of optimal n-grams for indexing string data in a DBMS system under space constraints introduced by the system 失效
标题翻译：在系统引入的空间约束下，选择一组用于在DBMS系统中索引字符串数据的最佳n-gram
公开(公告)号：US08001128B2
公开(公告)日：2011-08-16
申请号：US12264899
申请日：2008-11-04
申请人： Vahit Hakan Hacigumus , Balakrishna Raghavendra Iyer , Sharad Mehrotra
发明人： Vahit Hakan Hacigumus , Balakrishna Raghavendra Iyer , Sharad Mehrotra
IPC分类号： G06F7/00 , G06F17/30
CPC分类号： G06F17/30619 , G06F17/30625 , Y10S707/99932 , Y10S707/99933 , Y10S707/99934 , Y10S707/99935 , Y10S707/99936 , Y10S707/99937 , Y10S707/99942 , Y10S707/99943
摘要： The present invention provides a computer-readable medium and system for selecting a set of n-grams for indexing string data in a DBMS system. Aspects of the invention include providing a set of candidate n-grams, each n-gram comprising a sequence of characters; identifying sample queries having character strings containing the candidate n-grams; and based on the set of candidate n-grams, the sample queries, database records, and an n-gram space constraint, automatically selecting, given the space constraint, a minimal set of an n-grams from the set of candidate n-grams that minimizes the number of false hits for the set of sample queries had the sample queries been executed against the database records.
摘要翻译：本发明提供了一种用于在DBMS系统中选择用于索引字符串数据的一组n-gram的计算机可读介质和系统。本发明的方面包括提供一组候选n克，每个n-gram包括一系列字符; 识别具有包含候选n-gram的字符串的样本查询; 并且基于候选n-gram的集合，样本查询，数据库记录和n-gram空间约束，给定空间约束，从候选n-gram集合中自动选择n-gram的最小集合这可以最小化针对数据库记录执行样本查询的一组样本查询的假命中数。

5. 发明授权

US07757033B1 Data exchanges among SMP physical partitions and I/O interfaces enterprise servers 有权
标题翻译： SMP物理分区和I / O接口企业服务器之间的数据交换
公开(公告)号：US07757033B1
公开(公告)日：2010-07-13
申请号：US10889468
申请日：2004-07-12
申请人： Sharad Mehrotra , Thomas Dean Lovett , Cosmos Nicolaou , Nakul Pratap Saraiya , Shreyas B. Shah
发明人： Sharad Mehrotra , Thomas Dean Lovett , Cosmos Nicolaou , Nakul Pratap Saraiya , Shreyas B. Shah
IPC分类号： G06F13/24
CPC分类号： G06F13/4022 , H04L49/357 , H04L49/45 , H04L49/602 , H04L49/70
摘要： Pluggable modules communicate via a switch fabric dataplane accessible via a backplane. Various embodiments are comprised of varying numbers and arrangements of the pluggable modules in accordance with a system architecture that provides for provisioning virtual servers and clusters of servers from underlying hardware and software resources. The system architecture is a unifying solution for applications requiring a combination of computation and networking performance. Resources may be pooled, scaled, and reclaimed dynamically for new purposes as requirements change, using dynamic reconfiguration of virtual computing and communication hardware and software.
摘要翻译：可插拔模块通过可通过背板访问的交换机结构数据板进行通信。根据提供从底层硬件和软件资源提供虚拟服务器和服务器集群的系统架构，各种实施例包括可插拔模块的不同数量和布置。系统架构是需要组合计算和网络性能的应用程序的统一解决方案。资源可以通过虚拟计算和通信硬件和软件的动态重新配置，为需求变化而动态地为新目的进行池化，缩放和回收。

6. 发明申请

US20090254875A1 PROACTIVE ROUTING SYSTEM AND METHOD 审中-公开
标题翻译：有效的路由系统和方法
公开(公告)号：US20090254875A1
公开(公告)日：2009-10-08
申请号：US12062394
申请日：2008-04-03
申请人： Sharad Mehrotra , Parsotam T. Patel , Viktor Lapinskii
发明人： Sharad Mehrotra , Parsotam T. Patel , Viktor Lapinskii
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： There is provided a proactive routing system and method. In some embodiments, the method includes determining slack for a net in a netlist, applying a routing condition to the net, calculating an extra delay related to the routing condition, determining a criticality of the net considering the extra delay and the determined slack, and setting a soft constraint based at least partially on the criticality.
摘要翻译：提供了主动的路由系统和方法。在一些实施例中，该方法包括确定网表中的网络的松弛度，向网络应用路由条件，计算与路由条件相关的额外延迟，考虑额外的延迟和确定的松弛来确定网络的关键性，以及至少部分地基于关键性设置软约束。

7. 发明申请

US20080184187A1 Enhanced Routing Grid System and Method 审中-公开
标题翻译：增强路由网格系统和方法
公开(公告)号：US20080184187A1
公开(公告)日：2008-07-31
申请号：US12062363
申请日：2008-04-03
申请人： Sharad Mehrotra , Parsotam T. Patel , Joe T. Rahmeh , Jeannette N. Sutherland
发明人： Sharad Mehrotra , Parsotam T. Patel , Joe T. Rahmeh , Jeannette N. Sutherland
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Routing systems and methods are provided having various strategies for optimizing and evaluating possible routes for netlist connections. In one embodiment, a data structure or matrix provides cost related data weighted to evaluate the impact proposed a connection or segment will have upon an attribute of interest such as, for example, speed, manufacturability or noise tolerance. This cost information can be related to terrain costs as well as shape costs to provide multidimensional cost information for connections. Processing such higher information cost data is made more efficient with an additive process that is less demanding than a computationally intensive iterative multiplication process. Various methods are also disclosed for shifting and adjusting routing grids to improve use of available space or reduce run time in routing. In another embodiment, a parallel processing scheme is used to process multiple regions on multiple processors simultaneously without creating conflicts, that could arise, for example, when two processors try to route a trace on the same gridpoint.
摘要翻译：提供了路由系统和方法，其具有用于优化和评估网表连接的可能路由的各种策略。在一个实施例中，数据结构或矩阵提供加权的成本相关数据，以评估连接或分段将对感兴趣的属性（例如速度，可制造性或噪声容限）提出的影响。该成本信息可以与地形成本以及形状成本相关联，以提供用于连接的多维成本信息。使用比计算密集型迭代乘法过程要求低的加法过程，处理这种更高信息成本数据变得更有效。还公开了用于移动和调整路由网格以改进对可用空间的使用或减少路由中的运行时间的各种方法。在另一个实施例中，使用并行处理方案来同时处理多个处理器上的多个区域而不会产生冲突，例如当两个处理器尝试在同一网格点上路由跟踪时可能出现冲突。

8. 发明申请

US20080059935A1 Enhanced Routing Grid System And Method 审中-公开
标题翻译：增强路由网格系统和方法
公开(公告)号：US20080059935A1
公开(公告)日：2008-03-06
申请号：US11934543
申请日：2007-11-02
申请人： Sharad Mehrotra , Parsotam Patel , Joe Rahmeh , Jeannette Sutherland
发明人： Sharad Mehrotra , Parsotam Patel , Joe Rahmeh , Jeannette Sutherland
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Routing systems and methods are provided having various strategies for optimizing and evaluating routes for netlist connections. In one embodiment, a data structure or matrix provides cost related data weighted to evaluate the impact proposed a connection or segment will have upon an attribute of interest such as, for example, speed, manufacturability or noise tolerance. This cost information can be related to terrain costs as well as shape costs to provide multidimensional cost information for connections. Processing such higher information cost data is made more efficient with an additive process that is less demanding than a computationally intensive iterative multiplication process. Various methods are also disclosed for shifting and adjusting routine grids to improve use of available space or reduce run time in routing. In another embodiment, a parallel processing scheme is used to process multiple regions on multiple processors simultaneously without creating conflicts, that could arise, for example, when two processors try to route a trace on the same gridpoint.
摘要翻译：提供了路由系统和方法，其具有用于优化和评估网表连接的路由的各种策略。在一个实施例中，数据结构或矩阵提供加权的成本相关数据，以评估连接或分段将对感兴趣的属性（例如速度，可制造性或噪声容限）提出的影响。该成本信息可以与地形成本以及形状成本相关联，以提供用于连接的多维成本信息。使用比计算密集型迭代乘法过程要求低的加法过程，处理这种更高信息成本数据变得更有效。还公开了用于移动和调整例程网格的各种方法，以改善可用空间的使用或减少路由中的运行时间。在另一个实施例中，使用并行处理方案来同时处理多个处理器上的多个区域而不会产生冲突，例如当两个处理器尝试在同一网格点上路由跟踪时可能出现冲突。

9. 发明授权

US06154812A Method for inhibiting thrashing in a multi-level non-blocking cache system 失效
标题翻译：在多级非阻塞缓存系统中抑制抖动的方法
公开(公告)号：US06154812A
公开(公告)日：2000-11-28
申请号：US881725
申请日：1997-06-25
申请人： Ricky C. Hetherington , Sharad Mehrotra , Ramesh Panwar
发明人： Ricky C. Hetherington , Sharad Mehrotra , Ramesh Panwar
IPC分类号： G06F12/08
CPC分类号： G06F12/0897
摘要： A data cache unit associated with a processor, the data cache unit including a first non-blocking cache receiving a data access from a device in the processor. A second non-blocking cache is coupled to the first non-blocking cache to service misses in the first non-blocking cache. A data return path coupled to the second non-blocking cache couples data returning from the second non-blocking cache to both the first non-blocking cache and the device generating the access to the first non-blocking cache.
摘要翻译：与处理器相关联的数据高速缓存单元，所述数据高速缓存单元包括从所述处理器中的设备接收数据访问的第一非阻塞缓存。第二非阻塞高速缓存耦合到第一非阻塞高速缓存以服务第一非阻塞高速缓存中的未命中。耦合到第二非阻塞缓存的数据返回路径将从第二非阻塞高速缓存返回的数据与第一非阻塞高速缓存和产生对第一非阻塞高速缓存的访问的设备耦合。

10. 发明授权

US6086238A Method and system for shape processing within an integrated circuit layout for parasitic capacitance estimation 失效
标题翻译：用于寄生电容估计的集成电路布局中的形状处理方法和系统
公开(公告)号：US6086238A
公开(公告)日：2000-07-11
申请号：US726721
申请日：1996-10-07
申请人： Sharad Mehrotra , Paul Gerard Villarrubia , David James Widiger
发明人： Sharad Mehrotra , Paul Gerard Villarrubia , David James Widiger
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method and system for shape processing within an integrated circuit layout for parasitic capacitance estimation is disclosed. In accordance with the method and system of the present invention, a set of coordinates of an overlapping region formed by at least one interconnect is first identified. Subsequently, each metal layer present within the overlapping region is classified. Each interconnect edge present on each side of the overlapping region is then determined. Finally, a neighbor in a direction perpendicular to each side of the overlapping region is determined. By so doing, the parasitic capacitance between the overlapping region and its determined neighbors can be evaluated.
摘要翻译：公开了一种用于寄生电容估计的集成电路布局内的形状处理方法和系统。根据本发明的方法和系统，首先确定由至少一个互连形成的重叠区域的一组坐标。随后，重叠区域内存在的各金属层被分类。然后确定存在于重叠区域的每一侧上的每个互连边缘。最后，确定在与重叠区域的每一侧垂直的方向上的邻居。通过这样做，可以评估重叠区域与其确定的邻居之间的寄生电容。

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