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1. 发明申请

US20080172638A1 METHOD OF OPTIMIZING HIERARCHICAL VERY LARGE SCALE INTEGRATION (VLSI) DESIGN BY USE OF CLUSTER-BASED LOGIC CELL CLONING 审中-公开
标题翻译：通过使用基于群集的逻辑单元克隆优化分层级非常大规模集成（VLSI）设计的方法
公开(公告)号：US20080172638A1
公开(公告)日：2008-07-17
申请号：US11623122
申请日：2007-01-15
申请人： Michael S. Gray , David J. Hathaway , Jason D. Hibbeler , Robert F. Walker , Xin Yuan
发明人： Michael S. Gray , David J. Hathaway , Jason D. Hibbeler , Robert F. Walker , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method of optimizing hierarchical very large scale integration (VLSI) design by use of cluster-based cell cloning. The method of the present invention provides improved yield or migration by reusing cells in order to reduce the number of unique instances of at least one of the reused cells. The method performs hierarchal optimization on the reduced set of clones (i.e., clusters). The method of the present disclosure includes, but is not limited to, the steps of setting the initial clustering parameters; assembling the physical design from existing reused cells; for each cell type, performing a full cloning operation in order to create a full set of duplicate cells; for each cell type, performing a full optimization of the design; for each cell type, performing an analyses of all cell environments and performing a clustering operation; and analyzing the overall results in order to determine whether the optimization objectives are achieved.
摘要翻译：通过使用基于簇的细胞克隆来优化分级超大规模集成（VLSI）设计的方法。本发明的方法通过重新使用细胞来提供改善的产量或迁移，以减少至少一个重复使用的细胞的唯一实例的数量。该方法对减少的克隆集合（即，簇）执行层次优化。本公开的方法包括但不限于设置初始聚类参数的步骤; 从现有的重复使用的电池组装物理设计; 对于每个单元格类型，执行完全克隆操作以便创建一整套重复的单元格; 对于每个单元格类型，执行设计的全面优化; 对于每个单元类型，执行所有单元环境的分析并执行聚类操作; 并分析总体结果，以确定是否实现优化目标。

2. 发明授权

US07735042B2 Context aware sub-circuit layout modification 失效
标题翻译：上下文感知子电路布局修改
公开(公告)号：US07735042B2
公开(公告)日：2010-06-08
申请号：US11831998
申请日：2007-08-01
申请人： Michael S. Gray , Matthew T. Guzowski , Jason D. Hibbeler , Kevin W. McCullen , Robert F. Walker , Xin Yuan
发明人： Michael S. Gray , Matthew T. Guzowski , Jason D. Hibbeler , Kevin W. McCullen , Robert F. Walker , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method, system and program product for context aware sub-circuit layout modification are disclosed. The method may include defining at least one context for the sub-circuit for each circuit that uses the sub-circuit; in the case that a plurality of contexts are defined, minimizing a number of contexts for the sub-circuit by combining contexts into at least one stage; placing each stage into a staged layout; and modifying the sub-circuit by modifying the staged layout.
摘要翻译：公开了一种用于上下文感知子电路布局修改的方法，系统和程序产品。该方法可以包括为使用子电路的每个电路定义用于子电路的至少一个上下文; 在定义多个上下文的情况下，通过将上下文合并到至少一个级中来最小化子电路的上下文数量; 将每个阶段放置在分阶段布局中; 并通过修改分段布局修改子电路。

3. 发明申请

US20090037850A1 POLYGONAL AREA DESIGN RULE CORRECTION METHOD FOR VLSI LAYOUTS 审中-公开
标题翻译：用于VLSI LAYOUTS的多边形设计规则校正方法
公开(公告)号：US20090037850A1
公开(公告)日：2009-02-05
申请号：US11831990
申请日：2007-08-01
申请人： Michael S. Gray , Matthew T. Guzowski , Jason D. Hibbeler , Robert F. Walker , Xin Yuan
发明人： Michael S. Gray , Matthew T. Guzowski , Jason D. Hibbeler , Robert F. Walker , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method of polygonal area design rule correction for use in an electronic design automation tool for governing integrated circuit (IC) design layouts using one-dimensional (1-D) optimization, with steps of analyzing IC design layout data to identify violating polygons, partitioning violating polygons into rectangles in a direction of optimization, formulating an area constraint for each violating polygon to formulate a global linear programming (LP) problem that includes each constraint for each violating polygon and solving the global LP problem to obtain a real-valued solution. A next LP problem is created for each area constraint, and solved. The creating a next and solving the next LP problem and solving are repeated until the last “next LP problem” is solved using constraints and objectives representing sums or differences of no more than two optimization variables.
摘要翻译：一种多边形区域设计规则校正方法，用于电子设计自动化工具，用于使用一维（1-D）优化来管理集成电路（IC）设计布局，并分析IC设计布局数据以识别违反多边形，划分在优化方向上将多边形侵入矩形，为每个违规多边形制定面积约束以制定全局线性规划（LP）问题，其包括每个违反多边形的每个约束，并解决全局LP问题以获得实值解。为每个区域约束创建下一个LP问题，并解决。重复创建下一个LP并解决下一个LP问题和解决问题，直到最后的“下一个LP问题”使用表示不超过两个优化变量的和或差的约束和目标来解决。

4. 发明申请

US20090037851A1 CONTEXT AWARE SUB-CIRCUIT LAYOUT MODIFICATION 失效
标题翻译：背景知识子电路布局修改
公开(公告)号：US20090037851A1
公开(公告)日：2009-02-05
申请号：US11831998
申请日：2007-08-01
申请人： Michael S. Gray , Matthew T. Guzowski , Jason D. Hibbeler , Kevin W. McCullen , Robert F. Walker , Xin Yuan
发明人： Michael S. Gray , Matthew T. Guzowski , Jason D. Hibbeler , Kevin W. McCullen , Robert F. Walker , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method, system and program product for context aware sub-circuit layout modification are disclosed. The method may include defining at least one context for the sub-circuit for each circuit that uses the sub-circuit; in the case that a plurality of contexts are defined, minimizing a number of contexts for the sub-circuit by combining contexts into at least one stage; placing each stage into a staged layout; and modifying the sub-circuit by modifying the staged layout.
摘要翻译：公开了一种用于上下文感知子电路布局修改的方法，系统和程序产品。该方法可以包括为使用子电路的每个电路定义用于子电路的至少一个上下文; 在定义多个上下文的情况下，通过将上下文合并到至少一个级中来最小化子电路的上下文数量; 将每个阶段放置在分阶段布局中; 并通过修改分段布局修改子电路。

5. 发明授权

US07484197B2 Minimum layout perturbation-based artwork legalization with grid constraints for hierarchical designs 失效
标题翻译：最小布局扰动为基础的艺术品合法化与层次设计的网格约束
公开(公告)号：US07484197B2
公开(公告)日：2009-01-27
申请号：US11279758
申请日：2006-04-14
申请人： Robert J. Allen , Michael S. Gray , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani R. Narayan , Robert F. Walker , Xin Yuan
发明人： Robert J. Allen , Michael S. Gray , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani R. Narayan , Robert F. Walker , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method comprises extracting a hierarchical grid constraint set and modeling one or more critical objects of at least one cell as a variable set. The method further comprises solving a linear programming problem based on the hierarchical grid constraint set with the variable set to provide initial locations of the critical objects of the at least one cell and determining target on-grid locations of the one or more critical objects in the at least one cell using the results of the linear programming solution.
摘要翻译：一种方法包括提取分级网格约束集合并将至少一个小区的一个或多个关键对象建模为变量集。该方法还包括基于具有变量集合的分级网格约束集来解决线性规划问题，以提供至少一个小区的关键对象的初始位置并且确定所述至少一个小区中的一个或多个关键对象的目标并网位置使用线性规划解决方案的结果的至少一个小区。

6. 发明授权

US07062729B2 Method and system for obtaining a feasible integer solution from a half-integer solution in hierarchical circuit layout optimization 有权
标题翻译：在分层电路布局优化中从半整数解求解可行整数解的方法和系统
公开(公告)号：US07062729B2
公开(公告)日：2006-06-13
申请号：US10946677
申请日：2004-09-22
申请人： Michael S. Gray , Jason D. Hibbeler , Gustavo E. Tellez , Robert F. Walker
发明人： Michael S. Gray , Jason D. Hibbeler , Gustavo E. Tellez , Robert F. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method (300) and system (500) for optimizing a circuit layout based on layout constraints (308) and objectives (312). The method includes solving a linear program so as to obtain a rational solution whose variables are either whole or half integer. The tight constraints and objectives involving variables whose solution are a half integer are reduced to a 2-SAT problem, which is analyzed to determine its satisfiability. If the 2-SAT problem is not satisfiable, one or more objectives are removed so as to make the 2-SAT problem satisfiable. Any half-integer results of the linear program are rounded according to the truth assignment that satisfies the 2-SAT problem. The rounded results are used to create the circuit layout.
摘要翻译：一种用于基于布局约束（308）和目标（312）优化电路布局的方法（300）和系统（500）。该方法包括求解线性程序，以获得变量为整数或整数的理性解。解决方案为半整数的变量的严格约束和目标简化为2-SAT问题，进行分析以确定其可满足性。如果2-SAT问题不可满足，则删除一个或多个目标，以使2-SAT问题满足。线性程序的任何半整数结果根据满足2-SAT问题的真值赋值进行舍入。圆形的结果用于创建电路布局。

7. 发明授权

US07865848B2 Layout optimization using parameterized cells 有权
标题翻译：使用参数化单元格进行布局优化
公开(公告)号：US07865848B2
公开(公告)日：2011-01-04
申请号：US11846017
申请日：2007-08-28
申请人： Veit Gernhoefer , Michael S. Gray , Matthew T. Guzowski , Jason D. Hibbeler , Stephen L. Runyon , Robert F. Walker , Bruce C. Wheeler
发明人： Veit Gernhoefer , Michael S. Gray , Matthew T. Guzowski , Jason D. Hibbeler , Stephen L. Runyon , Robert F. Walker , Bruce C. Wheeler
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of layout optimization containing parameterized cells includes reading a physical design containing parameterized cells, creating a new version for each of usage of a given parameterized cell. The method optimizes physical design shapes of each new version of the parameterized cell by assigning variables to parameters of the parameterized cell according to a desired objective. Then, the method updates the parameters of each new version of the parameterized cell and replaces each new version of the parameterized cell with an instance of the parameterized cell having updated parameters. The method can optionally adjust physical design shapes based on constraints related to the parameters.
摘要翻译：包含参数化单元格的布局优化方法包括读取包含参数化单元格的物理设计，为给定参数化单元格的每个使用创建新版本。该方法通过根据期望的目标将参数分配给参数化单元的参数来优化每个新版本的参数化单元的物理设计形状。然后，该方法更新参数化单元的每个新版本的参数，并用具有更新参数的参数化单元的实例替换参数化单元的每个新版本。该方法可以基于与参数相关的约束来可选地调整物理设计形状。

8. 发明申请

US20090064061A1 Layout Optimization Using Parameterized Cells 有权
标题翻译：使用参数化单元格的布局优化
公开(公告)号：US20090064061A1
公开(公告)日：2009-03-05
申请号：US11846017
申请日：2007-08-28
申请人： Veit Gernhoefer , Michael S. Gray , Matthew T. Guzowski , Jason D. Hibbeler , Stephen L. Runyon , Robert F. Walker , Bruce C. Wheeler
发明人： Veit Gernhoefer , Michael S. Gray , Matthew T. Guzowski , Jason D. Hibbeler , Stephen L. Runyon , Robert F. Walker , Bruce C. Wheeler
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of layout optimization containing parameterized cells includes reading a physical design containing parameterized cells, creating a new version for each of usage of a given parameterized cell. The method optimizes physical design shapes of each new version of the parameterized cell by assigning variables to parameters of the parameterized cell according to a desired objective. Then, the method updates the parameters of each new version of the parameterized cell and replaces each new version of the parameterized cell with an instance of the parameterized cell having updated parameters. The method can optionally adjust physical design shapes based on constraints related to the parameters.
摘要翻译：包含参数化单元格的布局优化方法包括读取包含参数化单元格的物理设计，为给定参数化单元格的每个使用创建新版本。该方法通过根据期望的目标将参数分配给参数化单元的参数来优化每个新版本的参数化单元的物理设计形状。然后，该方法更新参数化单元的每个新版本的参数，并用具有更新参数的参数化单元的实例替换参数化单元的每个新版本。该方法可以基于与参数相关的约束来可选地调整物理设计形状。

9. 发明授权

US07120887B2 Cloned and original circuit shape merging 失效
标题翻译：克隆和原始电路形状合并
公开(公告)号：US07120887B2
公开(公告)日：2006-10-10
申请号：US10707845
申请日：2004-01-16
申请人： Henry A. Bonges, III , Michael S. Gray , Jason D. Hibbeler , Kevin W. McCullen , Robert F. Walker
发明人： Henry A. Bonges, III , Michael S. Gray , Jason D. Hibbeler , Kevin W. McCullen , Robert F. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method, system and program product for merging cloned and original circuit shapes such that a union thereof does not include a notch. The invention determines, for a cell including an original circuit shape and at least one overlapping clone of the original circuit shape, whether each clone corner point of each overlapping clone is within a threshold distance of a corresponding original corner point of the original circuit shape; and generates, in the case that each clone corner point of each overlapping clone circuit shape is within a threshold distance, a union of each overlapping clone and the original circuit shape such that the union does not contain a notch. The union is generated using a point code that sets a new position for a union corner point to remove a notch based on the original shape's direction and the edge orientations previous to and next to the corner point.
摘要翻译：用于合并克隆和原始电路形状的方法，系统和程序产品，使得其联合不包括缺口。本发明对于包括原始电路形状的单元和原始电路形状的至少一个重叠克隆来确定每个重叠克隆的每个克隆角点是否处于原始电路形状的相应原始角点的阈值距离内; 并且在每个重叠克隆电路形状的每个克隆角点处于阈值距离内的情况下，生成每个重叠克隆的结合和原始电路形状，使得联合不包含凹口。联合是使用点代码生成的，该点代码为联合角点设置新位置，以根据原始形状的方向和角点之前和之后的边缘方向去除凹口。

10. 发明授权

US07260790B2 Integrated circuit yield enhancement using Voronoi diagrams 有权
标题翻译：使用Voronoi图的集成电路产量增强
公开(公告)号：US07260790B2
公开(公告)日：2007-08-21
申请号：US10709292
申请日：2004-04-27
申请人： Robert J. Allen , Michael S. Gray , Jason D. Hibbeler , Mervyn Yee-Min Tan , Robert F. Walker
发明人： Robert J. Allen , Michael S. Gray , Jason D. Hibbeler , Mervyn Yee-Min Tan , Robert F. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method of calculating critical area in an integrated circuit design, said method comprising: inputting an integrated circuit design; associating variables with the positions of edges in said integrated circuit design; and associating cost functions of said variables with spacing between said edges in said integrated circuit design; wherein said cost functions calculate critical area contributions as the positions and length of said edges in said integrated circuit design change, and wherein said critical area contributions comprise a measure of electrical fault characteristics of said spacing between said edges in said integrated circuit design.
摘要翻译：一种在集成电路设计中计算临界面积的方法，所述方法包括：输入集成电路设计; 将变量与所述集成电路设计中的边缘的位置相关联; 以及将所述变量的成本函数与所述集成电路设计中的所述边缘之间的间隔相关联; 其中当所述集成电路设计中的所述边缘的位置和长度改变时，所述成本函数计算临界面积贡献，并且其中所述临界区域贡献包括所述集成电路设计中所述边缘之间的所述间隔的电气故障特征的量度。

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