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1. 发明申请

US20080216036A1 SLACK SENSITIVITY TO PARAMETER VARIATION BASED TIMING ANALYSIS 有权
公开(公告)号：US20080216036A1
公开(公告)日：2008-09-04
申请号：US12122451
申请日：2008-05-16
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Jeffrey H. Oppold , Anthony D. Polson
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Jeffrey H. Oppold , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.

2. 发明申请

US20090144024A1 Method and Structure for Screening NFET-to-PFET Device Performance Offsets Within a CMOS Process 有权
标题翻译：在CMOS工艺中筛选NFET至PFET器件性能偏移的方法和结构
公开(公告)号：US20090144024A1
公开(公告)日：2009-06-04
申请号：US11949066
申请日：2007-12-03
申请人： Jeffrey H. Oppold
发明人： Jeffrey H. Oppold
IPC分类号： G21C17/00
CPC分类号： H01L22/34
摘要： A method of screening on-chip variation in NFET-to-PFET device performance for as-manufactured integrated circuits (ICs) made using a CMOS process. The method includes defining an acceptable frequency- or period-based NFET-to-PFET device performance envelope by simulating a pair of ring oscillators, one of which contains only NFET transistors and the other of which contains only PFET transistors. The ring oscillators are then fabricated into each as-manufactured ICs. At screening time, the ring oscillators in each fabricated IC are tested to measure their frequencies (periods). These frequencies (periods) are then compared to the performance envelope to determine whether the NFET-to-PFET device performance of the corresponding IC is acceptable or not.
摘要翻译：筛选使用CMOS工艺制造的制造集成电路（IC）的NFET至PFET器件性能的片上变化的方法。该方法包括通过模拟一对环形振荡器来定义可接受的基于频率或周期的NFET至PFET器件性能包络，其中一个环形振荡器仅包含NFET晶体管，另一个仅包含PFET晶体管。然后将环形振荡器制造成每个制造的IC。在筛选时间，测试每个制造的IC中的环形振荡器以测量它们的频率（周期）。然后将这些频率（周期）与性能包络进行比较，以确定相应IC的NFET至PFET器件性能是否可接受。

3. 发明授权

US07401307B2 Slack sensitivity to parameter variation based timing analysis 有权
标题翻译：对基于参数变化的时序分析的松弛敏感性
公开(公告)号：US07401307B2
公开(公告)日：2008-07-15
申请号：US10904309
申请日：2004-11-03
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Jeffrey H. Oppold , Anthony D. Polson
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Jeffrey H. Oppold , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.
摘要翻译：公开了一种用于改进IC设计的方法，系统和程序产品，其优先考虑根据其故障概率导致校正的松弛故障系数。通过确定的一组独立参数，当参数变化时，通过注意时序上的差异，通常在端点松弛时，对每个参数执行灵敏度分析。对于每个独立参数重复此步骤。然后从参考松弛和每个定时端点的松弛的灵敏度计算失效系数，并且确定至少一个定时端点是否失败阈值测试。然后将失败的定时终点根据其故障系数进行优先级修改。所需的总运行次数是一次运行，用作参考运行，每个参数再运行一次运行。

4. 发明授权

US06420746B1 Three device DRAM cell with integrated capacitor and local interconnect 失效
标题翻译：具有集成电容器和局部互连的三器件DRAM单元
公开(公告)号：US06420746B1
公开(公告)日：2002-07-16
申请号：US09182857
申请日：1998-10-29
申请人： John A. Bracchitta , Randy W. Mann , Jeffrey H. Oppold
发明人： John A. Bracchitta , Randy W. Mann , Jeffrey H. Oppold
IPC分类号： H01L27108
CPC分类号： H01L27/108 , H01L21/76895 , H01L28/40
摘要： A semiconductor integrated circuit memory cell, including at least three transistors and a capacitor to form a DRAM. The memory cell is fabricated on a semiconductor substrate including impurity regions, and using two semiconductor films, with dielectric films between the semiconductor films. The capacitor contains two electrodes. A substrate impurity region forms one of the electrodes; the other electrode is a semiconductor film which connects the gate of one device to an impurity region of another. The method for manufacturing the above-described integrated circuit, which may be used for the manufacture of similar circuits, is also disclosed.
摘要翻译：一种半导体集成电路存储单元，包括至少三个晶体管和用于形成DRAM的电容器。存储单元制造在包括杂质区域的半导体衬底上，并且在半导体膜之间使用两个半导体膜和介电膜。电容器包含两个电极。衬底杂质区形成电极之一; 另一个电极是将一个器件的栅极连接到另一个器件的杂质区域的半导体膜。还公开了可用于制造类似电路的上述集成电路的制造方法。

5. 发明授权

US08196088B2 Method and structure for screening NFET-to-PFET device performance offsets within a CMOS process 有权
标题翻译：在CMOS工艺中屏蔽NFET至PFET器件性能偏移的方法和结构
公开(公告)号：US08196088B2
公开(公告)日：2012-06-05
申请号：US11949066
申请日：2007-12-03
申请人： Jeffrey H. Oppold
发明人： Jeffrey H. Oppold
IPC分类号： G06F11/22 , G06F17/50
CPC分类号： H01L22/34
摘要： A method of screening on-chip variation in NFET-to-PFET device performance for as-manufactured integrated circuits (ICs) made using a CMOS process. The method includes defining an acceptable frequency- or period-based NFET-to-PFET device performance envelope by simulating a pair of ring oscillators, one of which contains only NFET transistors and the other of which contains only PFET transistors. The ring oscillators are then fabricated into each as-manufactured ICs. At screening time, the ring oscillators in each fabricated IC are tested to measure their frequencies (periods). These frequencies (periods) are then compared to the performance envelope to determine whether the NFET-to-PFET device performance of the corresponding IC is acceptable or not.
摘要翻译：筛选使用CMOS工艺制造的制造集成电路（IC）的NFET至PFET器件性能的片上变化的方法。该方法包括通过模拟一对环形振荡器来定义可接受的基于频率或周期的NFET至PFET器件性能包络，其中一个环形振荡器仅包含NFET晶体管，另一个仅包含PFET晶体管。然后将环形振荡器制造成每个制造的IC。在筛选时间，测试每个制造的IC中的环形振荡器以测量它们的频率（周期）。然后将这些频率（周期）与性能包络进行比较，以确定相应IC的NFET至PFET器件性能是否可接受。

6. 发明申请

US20100174503A1 Monitoring NFET/PFET Skew in Complementary Metal Oxide Semiconductor Devices 审中-公开
标题翻译：监测互补金属氧化物半导体器件中的NFET / PFET偏移
公开(公告)号：US20100174503A1
公开(公告)日：2010-07-08
申请号：US12349698
申请日：2009-01-07
申请人： Bruce Balch , Anthony Wayne Fazekas , Mark C.H. Lamorey , Jeffrey H. Oppold , Joseph James Oler, JR. , Chirstopher Daniel Parkinson
发明人： Bruce Balch , Anthony Wayne Fazekas , Mark C.H. Lamorey , Jeffrey H. Oppold , Joseph James Oler, JR. , Chirstopher Daniel Parkinson
IPC分类号： G01R29/02 , G21C17/00 , H03K3/03
CPC分类号： G01R31/2621 , G01R31/2648 , H01L22/34
摘要： An apparatus for directly measuring performance offset of NFET transistors with respect to PFET transistors in CMOS device processing includes a ring oscillator whose frequency is used to measure random across chip variations, as well as correlated across chip variations; a balanced inverter having a input driven by the ring oscillator, wherein the balanced inverter is designed to be formed such that a current drive capability of one or more NFET devices of the inverter is substantially equal to a current drive capability of one or more PFET devices of the inverter at a given operating temperature; and a capacitor coupled to an output of the inverter, with a voltage across the capacitor indicative of whether a skew exists between NFET device performance and PFET device performance.
摘要翻译：在CMOS器件处理中用于直接测量NFET晶体管相对于PFET晶体管的性能偏移的装置包括一个环形振荡器，其频率用于测量随机跨越芯片变化以及跨芯片变化的相关性; 具有由环形振荡器驱动的输入的平衡逆变器，其中平衡逆变器被设计成形成为使得逆变器的一个或多个NFET器件的电流驱动能力基本上等于一个或多个PFET器件的电流驱动能力在给定的工作温度下; 以及耦合到反相器的输出的电容器，电容器两端的电压指示在NFET器件性能和PFET器件性能之间是否存在偏斜。

7. 发明申请

US20090140245A1 Structure for a Method and Structure for Screening NFET-to-PFET Device Performance Offsets Within a CMOS Process 审中-公开
标题翻译：在CMOS工艺中筛选NFET至PFET器件性能偏移的方法和结构的结构
公开(公告)号：US20090140245A1
公开(公告)日：2009-06-04
申请号：US12128273
申请日：2008-05-28
申请人： Jeffrey H. Oppold
发明人： Jeffrey H. Oppold
IPC分类号： H01L27/092
CPC分类号： H01L27/092 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A design structure of a method of screening on-chip variation in NFET-to-PFET device performance for as-manufactured integrated circuits (ICs) made using a CMOS process. The method includes defining an acceptable frequency- or period-NFET-to-PFET device performance envelope by simulating a pair of ring oscillators, one of which contains only NFET transistors and the other of which contains only PFET transistors. The ring oscillators are then fabricated into each as-manufactured ICs. At screening time, the ring oscillators in each fabricated IC are tested to measure their frequencies (periods). These frequencies (periods) are then compared to the performance envelope to determine whether the NFET-to-PFET device performance of the corresponding IC is acceptable or not.
摘要翻译：一种筛选使用CMOS工艺制造的制造集成电路（IC）的NFET至PFET器件性能的片上变化的方法的设计结构。该方法包括通过模拟一对环形振荡器来定义可接受的频率或周期NFET至PFET器件性能包络，其中一个环形振荡器仅包含NFET晶体管，而另一个只包含PFET晶体管。然后将环形振荡器制造成每个制造的IC。在筛选时间，测试每个制造的IC中的环形振荡器以测量它们的频率（周期）。然后将这些频率（周期）与性能包络进行比较，以确定相应IC的NFET至PFET器件性能是否可接受。

8. 发明授权

US06917221B2 Method and apparatus for enhancing the soft error rate immunity of dynamic logic circuits 失效
标题翻译：提高动态逻辑电路的软错误率抗扰度的方法和装置
公开(公告)号：US06917221B2
公开(公告)日：2005-07-12
申请号：US10249642
申请日：2003-04-28
申请人： Kerry Bernstein , Stephen V. Kosonocky , Randy W. Mann , Jeffrey H. Oppold
发明人： Kerry Bernstein , Stephen V. Kosonocky , Randy W. Mann , Jeffrey H. Oppold
IPC分类号： G06F11/00 , H03K19/017 , H03K19/094
CPC分类号： H03K19/01728
摘要： An apparatus and method for selectively enhancing the soft error rate (SER) immunity of a dynamic logic circuit. The apparatus includes a bootstrap capacitor coupled to a precharge input signal and a dynamic node of the dynamic logic circuit, and a device, such as an FET, for selectively connecting the bootstrap capacitor to the dynamic node.
摘要翻译：一种用于选择性地增强动态逻辑电路的软错误率（SER）抗扰度的装置和方法。该装置包括耦合到预充电输入信号和动态逻辑电路的动态节点的自举电容器，以及用于选择性地将自举电容器连接到动态节点的诸如FET的装置。

9. 发明授权

US07870525B2 Slack sensitivity to parameter variation based timing analysis 有权
标题翻译：对基于参数变化的时序分析的松弛敏感性
公开(公告)号：US07870525B2
公开(公告)日：2011-01-11
申请号：US12122451
申请日：2008-05-16
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Jeffrey H. Oppold , Anthony D. Polson
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Jeffrey H. Oppold , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.
摘要翻译：公开了一种用于改进IC设计的方法，系统和程序产品，其优先考虑根据其故障概率导致校正的松弛故障系数。通过确定的一组独立参数，当参数变化时，通过注意时序上的差异，通常在端点松弛时，对每个参数执行灵敏度分析。对于每个独立参数重复此步骤。然后从参考松弛和每个定时端点的松弛的灵敏度计算失效系数，并且确定至少一个定时端点是否失败阈值测试。然后将失败的定时终点根据其故障系数进行优先级修改。所需的总运行次数是一次运行，用作参考运行，每个参数再运行一次运行。

10. 发明授权

US07716616B2 Slack sensitivity to parameter variation based timing analysis 失效
标题翻译：对基于参数变化的时序分析的松弛敏感性
公开(公告)号：US07716616B2
公开(公告)日：2010-05-11
申请号：US11930924
申请日：2007-10-31
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Jeffrey H. Oppold , Anthony D. Polson
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Jeffrey H. Oppold , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.
摘要翻译：公开了一种用于改进IC设计的方法，系统和程序产品，其优先考虑根据其故障概率导致校正的松弛故障系数。通过确定的一组独立参数，当参数变化时，通过注意时序上的差异，通常在端点松弛时，对每个参数执行灵敏度分析。对于每个独立参数重复此步骤。然后从参考松弛和每个定时端点的松弛的灵敏度计算失效系数，并且确定至少一个定时端点是否失败阈值测试。然后将失败的定时终点根据其故障系数进行优先级修改。所需的总运行次数是一次运行，用作参考运行，每个参数再运行一次运行。

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