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1. 发明授权

US07093208B2 Method for tuning a digital design for synthesized random logic circuit macros in a continuous design space with optional insertion of multiple threshold voltage devices 失效
标题翻译：用于在连续设计空间中调整合成随机逻辑电路宏的数字设计的方法，并可选择插入多个阈值电压器件
公开(公告)号：US07093208B2
公开(公告)日：2006-08-15
申请号：US10842589
申请日：2004-05-10
申请人： Patrick M. Williams , Ee K. Cho , David J. Hathaway , Mei-Ting Hsu , Lawrence K. Lange , Gregory A. Northrop , Chandramouli Visweswariah , Cindy ShuiKing Washburn , Jun Zhou
发明人： Patrick M. Williams , Ee K. Cho , David J. Hathaway , Mei-Ting Hsu , Lawrence K. Lange , Gregory A. Northrop , Chandramouli Visweswariah , Cindy ShuiKing Washburn , Jun Zhou
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A Digital Design Method which may be automated is for obtaining timing closure in the design of large, complex, high-performance digital integrated circuits. The methodincludes the use of a tuner on random logic macros that adjusts transistor sizes in a continuous domain. To accommodate this tuning, logic gates are mapped to parameterized cells for the tuning and then back to fixed gates after the tuning. Tuning is constrained in such a way as to minimize “binning errors” when the design is mapped back to fixed cells. Further, the critical sections of the circuit are marked in order to make the optimization more effective and to fit within the problem-size constraints of the tuner. A specially formulated objective function is employed during the tuning to promote faster global timing convergence, despite possibly incorrect initial timing budgets. The specially formulated objective function targets all paths that are failing timing, with appropriate weighting, rather than just targeting the most critical path. Finally, the addition of multiple threshold voltage gates allows for increased performance while limiting leakage power.
摘要翻译：可以自动化的数字设计方法是在大型，复杂，高性能数字集成电路的设计中获得定时关闭。该方法包括在随机逻辑宏中使用调谐器来调整连续域中的晶体管尺寸。为了适应这种调谐，逻辑门被映射到用于调谐的参数化单元，然后在调谐之后返回到固定门。调整受限于将设计映射回固定单元格时最小化“合并错误”。此外，电路的关键部分被标记以便使优化更有效并且适应调谐器的问题尺寸约束。在调整期间采用了特别制定的目标函数，以促进更快的全局时序收敛，尽管可能不正确的初始时间预算。特别制定的目标函数针对所有失败时机的路径，以适当的权重，而不是仅针对最关键的路径。最后，添加多个阈值电压门允许提高性能，同时限制漏电功率。

2. 发明授权

US07743355B2 Method of achieving timing closure in digital integrated circuits by optimizing individual macros 失效
标题翻译：通过优化单个宏来实现数字集成电路中的时序闭合的方法
公开(公告)号：US07743355B2
公开(公告)日：2010-06-22
申请号：US11942034
申请日：2007-11-19
申请人： Jun Zhou , David J. Hathaway , Chandramouli Visweswariah , Patrick M. Williams
发明人： Jun Zhou , David J. Hathaway , Chandramouli Visweswariah , Patrick M. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/505 , G06F2217/84
摘要： Disclosed is a method for enhanced efficiency and effectiveness in achieving closure of large, complex, high-performance digital integrated circuits. Circuit macros are re-optimized and re-tuned in the timing closure loop by means of a reformulated objective function that allows the optimizer to improve the slack of all signals rather than just the most critical one(s). The incentive to improve the timing of a sub-critical signal is a diminishing function of the criticality of the signal. Thus all signals are improved during the optimization, with the highest incentive to improve on the most critical signals, leading to faster and more effective overall timing closure.
摘要翻译：公开了一种用于提高大型，复杂，高性能数字集成电路闭合的效率和有效性的方法。电路宏通过重新配置的目标函数在时序闭合循环中重新优化和重新调整，允许优化器改善所有信号的松弛，而不仅仅是最关键的。改善次临界信号时序的动机是信号临界性的递减函数。因此，在优化期间，所有信号都得到改进，最高激励措施可以改善最关键的信号，从而实现更快更有效的整体时序收敛。

3. 发明授权

US07003747B2 Method of achieving timing closure in digital integrated circuits by optimizing individual macros 失效
标题翻译：通过优化单个宏来实现数字集成电路中的时序闭合的方法
公开(公告)号：US07003747B2
公开(公告)日：2006-02-21
申请号：US10435824
申请日：2003-05-12
申请人： Jun Zhou , David J. Hathaway , Chandramouli Visweswariah , Patrick M. Williams
发明人： Jun Zhou , David J. Hathaway , Chandramouli Visweswariah , Patrick M. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/505 , G06F2217/84
摘要： Disclosed is a method for enhanced efficiency and effectiveness in achieving timing closure of large, complex, high-performance digital integrated circuits. Circuit macros are re-optimized and re-tuned in the timing closure loop by means of a reformulated objective function that allows the optimizer to improve the slack of all signals rather than just the most critical one(s). The incentive to improve the timing of a sub-critical signal is a diminishing function of the criticality of the signal. Thus all signals are improved during the optimization, with the highest incentive to improve on the most critical signals, leading to faster and more effective overall timing closure.
摘要翻译：公开了一种用于提高大型，复杂，高性能数字集成电路的定时闭合的效率和有效性的方法。电路宏通过重新配置的目标函数在时序闭合循环中重新优化和重新调整，允许优化器改善所有信号的松弛，而不仅仅是最关键的。改善次临界信号时序的动机是信号临界性的递减函数。因此，在优化期间，所有信号都得到改进，最高激励措施可以改善最关键的信号，从而实现更快更有效的整体时序收敛。

4. 发明授权

US07010763B2 Method of optimizing and analyzing selected portions of a digital integrated circuit 有权
标题翻译：优化和分析数字集成电路的选定部分的方法
公开(公告)号：US07010763B2
公开(公告)日：2006-03-07
申请号：US10436213
申请日：2003-05-12
申请人： David J. Hathaway , Lawrence Kenneth Lange , Chandramouli Visweswariah , Patrick M. Williams
发明人： David J. Hathaway , Lawrence Kenneth Lange , Chandramouli Visweswariah , Patrick M. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Disclosed is a method for achieving timing closure in the design of a digital integrated circuit or system by selecting portions of the circuit or system to be optimized and portions of the circuit or system in which the effects of such optimization are to be analyzed during the optimization process. Optimized portions will include gates whose design parameters are to be changed, a first analyzed portion includes gates whose delays and edge slews are to be recomputed, and a second analyzed portion includes gates whose ATs and RATs are to be recomputed during optimization. Constraints are imposed at selected boundaries between these portions to prevent unwanted propagation of timing information and to ensure the validity of timing values used during optimization. Through this selection, the size of the problem posed to the underlying optimization method will be reduced, allowing larger circuits or systems to be optimized and allowing optimization to be performed more quickly.
摘要翻译：公开了一种在数字集成电路或系统的设计中实现定时闭合的方法，通过选择要优化的电路或系统的部分以及在优化期间分析这种优化的影响的电路或系统的部分处理。优化部分将包括其设计参数将被改变的门，第一分析部分包括要重新计算其延迟和边缘电压的门，并且第二分析部分包括在优化期间重新计算其AT和RAT的门。在这些部分之间的选定边界施加约束，以防止定时信息的不期望的传播，并确保优化期间使用的定时值的有效性。通过这种选择，将降低对基础优化方法造成的问题的大小，从而允许更大的电路或系统被优化，并允许更快地执行优化。

5. 发明授权

US07325210B2 Hybrid linear wire model approach to tuning transistor widths of circuits with RC interconnect 有权
标题翻译：混合线性线模型方法来调整具有RC互连的电路的晶体管宽度
公开(公告)号：US07325210B2
公开(公告)日：2008-01-29
申请号：US11077043
申请日：2005-03-10
申请人： Vasant Rao , Cindy Washburn , Jun Zhou , Jeffrey P. Soreff , Patrick M. Williams , David J. Hathaway
发明人： Vasant Rao , Cindy Washburn , Jun Zhou , Jeffrey P. Soreff , Patrick M. Williams , David J. Hathaway
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031 , G06F17/5068
摘要： A hybrid linear wire model for tuning the transistor widths of circuits linked by RC interconnects is described. The method uses two embedded simulators during the tuning process on netlists that contain resistors (Rs). A Timing oriented simulator is used only for timing purposes on the original netlist that includes all the Rs. A Gradient oriented simulator is then run only on the modified netlist with all Rs shorted and within the iterative loop of the tuner to compute gradients. The present hybrid method achieves a significant improvement in computational speed. The Timing oriented simulator is fast and accurate for only timing netlists with Rs, but cannot compute gradients efficiently. The Gradient oriented simulator computes gradients efficiently but cannot do so in the presence of Rs. To prevent “de-tuning” that typically occurs when all Rs are shorted, ‘wire-adjusts’ are provided that make the initial timing results using the Gradient oriented simulator on the shorted netlist match the timing results using Timing oriented simulator on the original netlist. This permits the optimizer sense initially the correct set of critical timing paths, and more significantly, it permits the wire-adjusts keep track of the changing transistor widths to guide the optimizer during the iterations until convergence is achieved.
摘要翻译：描述了用于调谐由RC互连链接的电路的晶体管宽度的混合线性线模型。在调谐过程中，该方法使用两个嵌入式模拟器，其中包含电阻（Rs）。面向计时的模拟器仅用于包含所有Rs的原始网表的时序目的。然后，一个面向梯度的模拟器仅在修改后的网表上运行，所有的Rs都已经短路，并在调谐器的迭代循环内计算梯度。目前的混合方法实现了计算速度的显着提高。面向时序的模拟器只需要具有Rs的时间网络列表即可快速准确，但无法有效地计算渐变。梯度导向模拟器有效地计算梯度，但在Rs的存在下不能这样做。为了防止所有Rs短路时通常发生的“去调谐”，提供“线调整”，使得在短路网表上使用面向梯度的模拟器的初始定时结果与使用定时模型的原始网表上的定时结果相匹配。这允许优化器最初感测正确的关键定时路径集合，并且更重要的是，它允许线路调整跟踪改变的晶体管宽度，以在迭代期间引导优化器直到实现收敛。

6. 发明申请

US20080250370A1 REPRESENTING AND PROPAGATING A VARIATIONAL VOLTAGE WAVEFORM IN STATISTICAL STATIC TIMING ANALYSIS OF DIGITAL CIRCUITS 有权
标题翻译：在数字电路的统计静态时序分析中代表和传播变量电压波形
公开(公告)号：US20080250370A1
公开(公告)日：2008-10-09
申请号：US11733058
申请日：2007-04-09
申请人： Soroush Abbaspour , David J. Hathaway , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Soroush Abbaspour , David J. Hathaway , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： An approach that represents and propagates a variational voltage waveform in statistical static timing analysis of digital circuits is described. In one embodiment, there is a statistical static timing analysis tool for analyzing digital circuit designs. The statistical static timing analysis tool includes a variational waveform modeling component that is configured to generate a variational waveform model that approximate arbitrary waveform transformations of waveforms at nodes of a digital circuit. The variational waveform model transforms a nominal waveform into a perturbed waveform in accordance with a plurality of waveform transformation operators that account for variations that occur between the nominal waveform and the perturbed waveform. A variational waveform propagating component is configured to propagate variational waveforms through a timing arc from at least one input to at least one output of the digital circuit in accordance with the variational waveform model.
摘要翻译：描述了在数字电路的统计静态时序分析中表示和传播变化电压波形的方法。在一个实施例中，存在用于分析数字电路设计的统计静态时序分析工具。统计静态时序分析工具包括变分波形建模组件，其被配置为生成近似波形在数字电路节点处的任意波形变换的变分波形模型。变分波形模型根据考虑在标称波形和扰动波形之间出现的变化的多个波形变换算子将标称波形变换为扰动波形。变分波形传播分量被配置为根据变化波形模型将变化波形传播通过定时弧从数字电路的至少一个输入到至少一个输出。

7. 发明授权

US08056035B2 Method and system for analyzing cross-talk coupling noise events in block-based statistical static timing 有权
标题翻译：在基于块的统计静态时序中分析串扰耦合噪声事件的方法和系统
公开(公告)号：US08056035B2
公开(公告)日：2011-11-08
申请号：US12132636
申请日：2008-06-04
申请人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Gregory M. Schaeffer , Chandramouli Visweswariah
发明人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Gregory M. Schaeffer , Chandramouli Visweswariah
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/82
摘要： A method of performing statistical timing analysis of a logic design, including effects of signal coupling, includes performing a deterministic analysis to determine deterministic coupling information for at least one aggressor/victim net pair of the logic design. Additionally, the method includes performing a statistical timing analysis in which the deterministic coupling information for the at least one aggressor/victim net pair is combined with statistical values of the statistical timing analysis to determine a statistical effective capacitance of a victim of the aggressor/victim net pair. Furthermore, the method includes using the statistical effective capacitance to determine timing data used in the statistical timing analysis.
摘要翻译：执行包括信号耦合效应的逻辑设计的统计定时分析的方法包括执行确定性分析以确定逻辑设计的至少一个攻击者/受害者网对的确定性耦合信息。另外，该方法包括执行统计时序分析，其中至少一个攻击者/受害者网络对的确定性耦合信息与统计时间分析的统计值相结合，以确定攻击者/受害者的受害者的统计有效电容净对。此外，该方法包括使用统计有效电容来确定在统计时序分析中使用的定时数据。

8. 发明申请

US20090307645A1 METHOD AND SYSTEM FOR ANALYZING CROSS-TALK COUPLING NOISE EVENTS IN BLOCK-BASED STATISTICAL STATIC TIMING 有权
标题翻译：基于块状统计静态时序分析交叉口耦合噪声事件的方法与系统
公开(公告)号：US20090307645A1
公开(公告)日：2009-12-10
申请号：US12132636
申请日：2008-06-04
申请人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Gregory M. Schaeffer , Chandramouli Visweswariah
发明人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Gregory M. Schaeffer , Chandramouli Visweswariah
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/82
摘要： A method of performing statistical timing analysis of a logic design, including effects of signal coupling, includes performing a deterministic analysis to determine deterministic coupling information for at least one aggressor/victim net pair of the logic design. Additionally, the method includes performing a statistical timing analysis in which the deterministic coupling information for the at least one aggressor/victim net pair is combined with statistical values of the statistical timing analysis to determine a statistical effective capacitance of a victim of the aggressor/victim net pair. Furthermore, the method includes using the statistical effective capacitance to determine timing data used in the statistical timing analysis.
摘要翻译：执行包括信号耦合效应的逻辑设计的统计定时分析的方法包括执行确定性分析以确定逻辑设计的至少一个攻击者/受害者网对的确定性耦合信息。另外，该方法包括执行统计时序分析，其中至少一个攻击者/受害者网络对的确定性耦合信息与统计时间分析的统计值相结合，以确定攻击者/受害者的受害者的统计有效电容净对。此外，该方法包括使用统计有效电容来确定在统计时序分析中使用的定时数据。

9. 发明申请

US20120124534A1 System and Method for Performing Static Timing Analysis in the Presence of Correlations Between Asserted Arrival Times 失效
标题翻译：在断定到达时间之间相关性的情况下执行静态时序分析的系统和方法
公开(公告)号：US20120124534A1
公开(公告)日：2012-05-17
申请号：US12944059
申请日：2010-11-11
申请人： Kerim Kalafala , Jennifer E. Basile , David J. Hathaway , Jeffrey G. Hemmett , Peihua Qi , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
发明人： Kerim Kalafala , Jennifer E. Basile , David J. Hathaway , Jeffrey G. Hemmett , Peihua Qi , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F2217/84
摘要： A method of applying common path credit in a static timing analysis in the presence of correlations between asserted arrival times, comprising the steps of using a computer, identifying one or more pairs of asserted arrival times for which one or more correlations exist; propagating to each of the one or more pairs of asserted arrival times a timing value dependent on the one or more correlations; and performing a subsequent common path pessimism removal analysis for at least one test during which a timing value dependent on the one or more correlations between asserted arrival times is used to compute an adjusted test slack.
摘要翻译：一种在断言到达时间之间的相关性存在的静态时序分析中应用公共路径信用的方法，包括以下步骤：使用计算机识别存在一个或多个相关性的一个或多个断言到达时间对; 将所述一个或多个断言到达时间对中的每一个传播到取决于所述一个或多个相关性的定时值; 以及对至少一个测试执行随后的公共路径悲观消除分析，在该测试期间，使用取决于所述到达时间之间的一个或多个相关性的定时值来计算经调整的测试松弛。

10. 发明授权

US07117466B2 System and method for correlated process pessimism removal for static timing analysis 失效
标题翻译：静态时序分析相关过程悲观消除的系统和方法
公开(公告)号：US07117466B2
公开(公告)日：2006-10-03
申请号：US10665273
申请日：2003-09-18
申请人： Kerim Kalafala , Peihua Qi , David J. Hathaway , Alexander J. Suess , Chandramouli Visweswariah
发明人： Kerim Kalafala , Peihua Qi , David J. Hathaway , Alexander J. Suess , Chandramouli Visweswariah
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method of removing pessimism in static timing analysis is described. Delays are expressed as a function of discrete parameter settings allowing for both local and global variation to be taken in to account. Based on a specified target slack, each failing timing test is examined to determine a consistent set of parameter settings which produces the worst possible slack. The analysis is performed on a path basis. By considering only parameters which are in common to a particular data/clock path-pair, the number of process combinations that need to be explored is reduced when compared to analyzing all combinations of the global parameter settings. Further, if parameters are separable and linear, worst-case variable assignments for a particular clock/data path pair can be computed in linear time by independently assigning each parameter value. In addition, if available, the incremental delay change with respect to each physically realizable process variable may be used to project the worst-case variable assignment on a per-path basis without the need for performing explicit corner enumeration.
摘要翻译：描述了静态时序分析中消除悲观情绪的方法。延迟表示为离散参数设置的函数，允许将本地和全局变量都用于账户。根据指定的目标松弛，检查每个失败的定时测试，以确定一组一致的参数设置，从而产生最差的松弛。分析以路径为基础进行。通过仅考虑与特定数据/时钟路径对共同的参数，与分析全局参数设置的所有组合相比，需要探索的进程组合的数量减少。此外，如果参数是可分离的和线性的，则通过独立地分配每个参数值，可以在线性时间内计算特定时钟/数据路径对的最差情况变量分配。另外，如果可用，可以使用相对于每个物理上可实现的过程变量的增量延迟变化来在每个路径基础上投射最坏情况的变量赋值，而不需要执行明确的角点枚举。

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