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51. 发明专利

JPH08241968A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH08241968A
公开(公告)日：1996-09-17
申请号：JP6404596
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： H01L21/76 , H01L21/8242 , H01L27/08 , H01L27/108 , H01L29/78
摘要： PURPOSE: To obtain a semiconductor integrated circuit device which enhances the junction breakdown strength of a substrate to an element and which reduces a leakage current amount at the junction part of the substrate to the element by a method wherein an active region is not arranged in the boundary region between a first channel stopper region and a second channel stopper region. CONSTITUTION: In a DRAM, a memory cell and an n-channel MISFET in a peripheral circuit are arranged respectively on main faces inside respective different active regions in a p-type well region which is prescribed by a p-type channel stopper region formed on the main face of an inactive region in the p-type well region. Here, a p-type channel stopper region 25A which surrounds the circumference of the memory cell and an n-channel stopper region 24 in the peripheral circuit are constituted independently in separate manufacturing processes. Then, an active region Act such as the memory cell, the n-channel MISFET or the like in the peripheral circuit are not arranged in the boundary region between the p-type channel stopper region 25A and the n-type channel region 24.

52. 发明专利

JPH02299267A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH02299267A
公开(公告)日：1990-12-11
申请号：JP12078089
申请日：1989-05-15
申请人： HITACHI LTD
发明人： OWADA NOBUO , KASAHARA OSAMU , ASANO ISAMU , TAMARU TAKESHI
IPC分类号： H01L29/73 , H01L21/28 , H01L21/331 , H01L29/40 , H01L29/732
摘要： PURPOSE:To enable the miniaturization of a bipolar LSI and to enable it to operate at a high speed by a method wherein an opening is provided to a part of an element isolation insulating film adjacent to the base diffusion layer of the bipolar transistor to form a collector lifting layer. CONSTITUTION:An opening is provided to an element isolation insulating film 6 in contact with insulating films 15 and 10 and a base diffusion layer 8 through etching to form a contact hole 16c whose base reaches to a collector buried layer 2, and then a collector lifting layer 19 is formed by filling a tungsten film into the contact hole 18c. A barrier metal layer 20 and an aluminum film 21 are successively deposited thereon, which is etched to form a base electrode 22, an emitter electrode 23, and a collector electrode 24. In this case, the space between the base diffusion layer 8 and the collector lifting layer 19 can be made small and the collector lifting layer 19 small in resistance can be obtained. By this setup, a bipolar transistor of this design can be miniaturized and made to operate at a high speed.

53. 发明专利

JPH0236534A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0236534A
公开(公告)日：1990-02-06
申请号：JP18560188
申请日：1988-07-27
申请人： HITACHI LTD
发明人： HINODE KENJI , HONMA YOSHIO , ASANO ISAMU
IPC分类号： H01L21/3205 , H01L23/52
摘要： PURPOSE:To prevent the disconnection due to any stress from occurring by a method wherein a wiring is formed to make at least one part of the sectional shape of the wiring take either recession or projection shape. CONSTITUTION:An Al wiring pattern 3 is formed on an Si substrate 1 whereon a surface oxide film 2 is formed and successively the Al wiring 3 is coated with an insulating film 4. The Al wiring 3 is etched away in a mixed gas of CHCl3 gas and Cl2 gas using a photoresist mask while the slope of the side to be formed is made gradually more gentle taking a recessed shape by increasing the ratio of CHCl3 gas in parallel with the advancement of the etching process, that is, the etching requirements are gradually changed in proportion to the advancement of the etching process. Thus, not only the gas composition and the flow rate but also the substrate bias amount etc., in the etching process can be controlled to be changed to make the semiconductor device take the same processing shape as that mentioned so far. The insulating film 4 is a silicon nitride film under the stress of around 0.3GPa formed by plasma CVD process with a compressive stress laid thereon.

54. 发明专利

JPS634063A BIAS SPUTTERING DEVICE 失效
公开(公告)号：JPS634063A
公开(公告)日：1988-01-09
申请号：JP14690886
申请日：1986-06-25
申请人： HITACHI LTD
发明人： TSUNEOKA MASATOSHI , HORIUCHI MITSUAKI , AKIMORI HIROYUKI , ASANO ISAMU , OWADA NOBUO
IPC分类号： H01L21/285 , C23C14/34
摘要： PURPOSE:To form a film having good quality and excellent adhesiveness without increasing a bias voltage by controlling the amt. of the ions to be generated from an ion generating source by the quantity of substrate current at the time of forming the film of a target material on a substrate by a bias sputtering method. CONSTITUTION:The inside of a vacuum vessel 1 is evacuated to a vacuum and gaseous Ar is introduced from a gas source 6 into the vessel. While an upper electrode 2 mounted with an Si wafer W as the substrate is heated by a heater 12, electric power is impressed from a negative power source 5 to a lower electrode 3. Electric power is simultaneously impressed to the upper electrode 2 as well from a negative power source 4 to set the same at a required bias. Plasma is generated between the two electrodes 2 and 3 and Al particles from the Al target T on the lower electrode 3 are deposited on the wafer W by the effect thereof. The current of the upper electrode 2 is measured by an ammeter 10 and is inputted to a controller 11 which feeds the current back to an ion generator 14 such as ECR to control the ion quantity near the upper electrode. The film having the good adhesiveness to the pattern having a large aspect ratio as well is thus formed while the bias of the upper electrode 2 is held constant.

55. 发明专利

JP2006203255A Method of manufacturing semiconductor integrated circuit device 审中-公开
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：JP2006203255A
公开(公告)日：2006-08-03
申请号：JP2006111935
申请日：2006-04-14
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： ASANO ISAMU , NAKAMURA YOSHITAKA , OJI YUZURU , SAITO TATSUYUKI , YUNOGAMI TAKASHI
IPC分类号： H01L27/108 , H01L21/768 , H01L21/8242 , H01L29/423 , H01L29/49
摘要： PROBLEM TO BE SOLVED: To promote miniaturization of a DRAM having a capacitive element in which a film consisting primarily of a platinum group metal and a conductive oxide of a platinum group alloy or a platinum group metal is used for an electrode material. SOLUTION: After trenches 44 are formed in a silicon oxide film 43, a Pt film 45 is formed inside the trench 44 by an electrolytic plating method in which a conductive base film 42 previously formed at the underlayer of the silicon oxide film 43 serves as a cathode electrode. After that, the silicon oxide film 43 is removed by etching, and then the conductive base film 42 is dry etched using the Pt film 45 as a mask, thereby forming a lower electrode of a capacitive element composed of the Pt film 45 and the conductive base film 42 remained under thereof. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题为了促进具有电容元件的DRAM的小型化，其中主要由铂族金属和铂族合金或铂族金属的导电氧化物组成的膜用于电极材料。解决方案：在氧化硅膜43中形成沟槽44之后，通过电解电镀法在沟槽44内形成Pt膜45，其中预先形成在氧化硅膜43的底层上的导电基膜42 用作阴极电极。之后，通过蚀刻除去氧化硅膜43，然后使用Pt膜45作为掩模对导电性基底膜42进行干法蚀刻，由此形成由Pt膜45和导电性的电极构成的电容性元件的下部电极基膜42保留在其下。版权所有（C）2006，JPO＆NCIPI

56. 发明专利

JP2003224203A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS FABRICATING METHOD 审中-公开
公开(公告)号：JP2003224203A
公开(公告)日：2003-08-08
申请号：JP2002019159
申请日：2002-01-28
申请人： HITACHI LTD , NEC CORP , NEC ELECTRONICS CORP
发明人： NAKAMURA YOSHITAKA , ASANO ISAMU , IIJIMA SHINPEI , HIRATANI MASAHIKO , SAKUMA HIROSHI
IPC分类号： H01L21/02 , H01L21/314 , H01L21/316 , H01L21/8242 , H01L21/8246 , H01L27/108 , H01L27/115
摘要： PROBLEM TO BE SOLVED: To enhance the characteristics of a semiconductor integrated circuit device by reducing the leak current of a capacitor element employed in a DRAM memory cell, or the like. SOLUTION: A capacitor element C for storing information connected with an MISFET Qs for transferring information in a memory cell forming region through plugs 20 and 39 is fabricated by forming a lower electrode 43a of an Ru film in the hole 42 of a silicon oxide film 41, depositing a tantalum oxide film on the lower electrode 43a and subjecting it to first heat treatment in an oxidizing atmosphere at a temperature high enough to repair oxygen defects but having no effect on the material underlying the tantalum oxide film, and to second heat treatment in an inert atmosphere at a temperature (not higher than 650°C) not crystallizing the tantalum oxide completely but higher than the temperature of subsequent process, and then forming an upper electrode 4c of a multilayer film of an Ru film and a W film on a capacitor insulation film 44b of the tantalum oxide. COPYRIGHT: (C)2003,JPO

57. 发明专利

JP2002217386A METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002217386A
公开(公告)日：2002-08-02
申请号：JP2001011098
申请日：2001-01-19
申请人： HITACHI LTD
发明人： ASANO ISAMU , IIJIMA SHINPEI , NAKAMURA YOSHITAKA
IPC分类号： H01L27/108 , H01L21/8242
摘要： PROBLEM TO BE SOLVED: To enhance the production yield of a semiconductor device by preventing the exfoliation of a platinum-group metal film constituting the lower- part electrode of a support-shaped or crown-shaped capacitive element. SOLUTION: An Ru film 40 constituting the lower-part electrode 41 is deposited at the inside of a groove 38 formed in a silicon oxide film 37. At this time, a first tantalum oxide film 39 is formed in advance on the sidewall of the groove 38. Then, the bonding strength of the Ru film 40 to a substrate (the silicon oxide film 37) is enhanced.

58. 发明专利

JP2001250925A SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JP2001250925A
公开(公告)日：2001-09-14
申请号：JP2000063735
申请日：2000-03-08
申请人： HITACHI LTD
发明人： MORIYA HIROSHI , IWASAKI TOMIO , OTA HIROYUKI , IIJIMA SHINPEI , ASANO ISAMU , OJI YUZURU , NAKAMURA YOSHITAKA
IPC分类号： H01L27/10 , H01L21/02 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To improve the coherency between a capacity electrode made of ruthenium, platinum, and the like and an insulating film in a semiconductor device having a capacitor for accumulating information. SOLUTION: This semiconductor device is equipped with a capacitor for accumulating information that has a first capacity electrode 15, an oxide film 16 for dielectrics, a second capacity electrode 17, and insulating films 12a and 18 using silicon as a main constituent element. The first and second capacity electrodes use one kind of element that is selected from a group including at least rhodium, ruthenium, iridium, osmium and platinum as the main constituent element, and are formed by a material configuration containing one kind of element that is selected from a group including at least palladium, nickel, cobalt, and titanium as additional elements.

59. 发明专利

JP2001094068A SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 失效
公开(公告)号：JP2001094068A
公开(公告)日：2001-04-06
申请号：JP26500399
申请日：1999-09-20
申请人： HITACHI LTD
发明人： OTA HIROYUKI , KUMAGAI YUKIHIRO , OJI YUZURU , ASANO ISAMU
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To obtain a semiconductor device which prevents the structure of a capacitor from becoming complicated, even when the semiconudctor device is integrated highly by a method where the permittivity of a BST thin film is increased. SOLUTION: A thin film, which has a compressive film stress is formed in the upper part of a BST thin film, tensile stress is loaded inside the BST thin film, and thereby, the permittivity of the BST thin film is enhanced.

60. 发明专利

JP2000315778A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JP2000315778A
公开(公告)日：2000-11-14
申请号：JP12392799
申请日：1999-04-30
申请人： HITACHI LTD
发明人： ASANO ISAMU , NAKAMURA YOSHITAKA , OJI YUZURU , SAITO TATSUYUKI , YUNOGAMI TAKASHI
IPC分类号： H01L27/04 , H01L21/02 , H01L21/28 , H01L21/288 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To promote miniaturization of dynamic random access memory(DRAM) having a capacitive element using as an electrode material a film containing a platinum group metal, a platinum group alloy or a conductive oxide of the platinum group metal as a main component. SOLUTION: Grooves 44 are made in on a silicon oxide film 43, and then a Pt film 45 is formed within the grooves 44 by electroplating for forming a conductive underlying film 42 previously formed on a lower layer of the film 43 as a cathode electrode. Thereafter, the film 32 is etched and removed, and thereafter the underlying film 42 is subjected to a dry etching process with use of the Pt film 45 as a mask, thus forming a lower electrode of a capacitive element with use of the Pt film 45 and the conductive underlying film 42 remaining thereunder.

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