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1. 发明专利

JP2004247559A Semiconductor device and method for manufacturing the same 审中-公开
公开(公告)号：JP2004247559A
公开(公告)日：2004-09-02
申请号：JP2003036459
申请日：2003-02-14
申请人： Elpida Memory Inc , Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： NAKAMURA YOSHITAKA , GOSHIMA HIDEKAZU , ASANO ISAMU , HORIKAWA TSUGUHIRO , KUROKI KEIJI , SAKUMA HIROSHI , KOYANAGI KENICHI , KAWAGOE TAKESHI
IPC分类号： H01L21/8242 , H01L21/02 , H01L21/768 , H01L27/108 , H01L29/76
CPC分类号： H01L28/65 , H01L21/7687 , H01L27/10814 , H01L27/10852
摘要： PROBLEM TO BE SOLVED: To provide an MIM type capacitor where only the bottom of a lower electrode is thick, and to provide a method for manufacturing the capacitor while reducing the number of processes and securing a margin at a joint. SOLUTION: This semiconductor device is composed of an MISFET for memory cell selection formed on one main surface of a semiconductor substrate, and a memory cell having a capacitor element composed of the lower electrode 41 electrically connected with the source or drain of the MISFET for memory selection at the bottom via a first metal layer and an upper electrode 61 formed at the top of the lower electrode 41 via a capacitor insulation film 51. The film thickness at the bottom of the lower electrode 41 is made to be ≥30 nm. Only the bottom of the capacitor is made to be thick by applying the sputtering of a high ionization rate and high directivity such as a PCM method to the forming of the lower electrode 41. COPYRIGHT: (C)2004,JPO&NCIPI

2. 发明专利

JP2002217388A METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002217388A
公开(公告)日：2002-08-02
申请号：JP2001011100
申请日：2001-01-19
申请人： HITACHI LTD
发明人： ASANO ISAMU
IPC分类号： H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a technique which can enhance the yield of a semiconductor device comprising a capacitor in a three-dimensional shape. SOLUTION: An insulating film 44 is deposited on the upper layer of an upper-part electrode 42 to be thicker than the height of capacitors C, the surface of the insulating film 44 is flattened by a CMP method, and the upper layer of the insulating film 44 is coated with a resist film. Consequently, the film thickness of the resist film becomes uniform over the whole face of a pattern. Even when an exposure and developing treatment is executed, a resist pattern 45 does not become thin in the boundary region between a memory array and a peripheral circuit, and it is possible to prevent the capacitors C from being shaved by a dry etching operation in the outermost circumferential part of the memory array.

3. 发明专利

JP2002083940A SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
公开(公告)号：JP2002083940A
公开(公告)日：2002-03-22
申请号：JP2000271893
申请日：2000-09-07
申请人： HITACHI LTD
发明人： IIJIMA SHINPEI , MATSUI YUICHI , ASANO ISAMU
IPC分类号： H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To increase the reliability of a semiconductor device by preventing increase in leakage current of a capacitive element having an MIM structure. SOLUTION: The semiconductor device comprises a capacitive element having a metal film for an electrode. The capacitive element consists of a first capacitive element formed with a metal electrode which is in contact with an insulation film, and a second capacitive element formed with a metal electrode which is in contact with a barrier film. The metal electrode of the second capacitive element is formed thickner than that of the first capacitive element. A method of fabricating the capacitive element comprises a process of forming a metal film which becomes a lower electrode in the bottom of the capacitive element; a process of forming the insulation film; a process of forming a hole in the insulation film to expose the surface of the metal film; and a process of forming a metal film which becomes a lower electrode on the side wall and bottom face of the hole. By these processes, the lower electrode of the capacitive element is formed thicker in the bottom than in the side wall.

4. 发明专利

JP2001036042A DIELECTRIC ELEMENT, ITS MANUFACTURE, AND SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2001036042A
公开(公告)日：2001-02-09
申请号：JP21024199
申请日：1999-07-26
申请人： HITACHI LTD
发明人： NAMATAME TOSHIHIDE , FUJIWARA TETSUO , SUZUKI TAKAAKI , MURATA YASUHIKO , HIGASHIYAMA KAZUHISA , ASANO ISAMU , ANDO TOSHIO
IPC分类号： H01L27/108 , H01L21/8242
摘要： PROBLEM TO BE SOLVED: To obtain a dielectric element of a high degree of integration with a large surface area by adopting metal or conductive oxide containing minute irregularities for the lower electrode of a capacitor of three-dimensional structure. SOLUTION: A dielectric element comprises an upper electrode 19, a dielectric 18, and a lower electrode 17 three-dimensionally structured. The lower electrode 17 is formed of a film of ruthenium, Pt, Ir, or the like having distributed minute irregularities, several nanometers, on a lower substrate 11 of three-dimensional structure, by organic metal chemical vapor growth using β-diketone complex. The lower electrode 17 is of two-layered structure and comprises minute irregularities and a layer formed thereon. Thus the surface area of a dielectric 18 can be increased by the irregularities on the lower electrode 17, and a dielectric element with a high degree of integration can be manufactured. Therefore, a dielectric element which is of three-dimensional structure in high-aspect ratio, has an increased surface area and a high degree of integration, and soundly operates can be formed and obtained.

5. 发明专利

JP2000208511A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2000208511A
公开(公告)日：2000-07-28
申请号：JP610899
申请日：1999-01-13
申请人： HITACHI LTD
发明人： IWASAKI TOMIO , MIURA HIDEO , ASANO ISAMU
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/768 , H01L23/48 , H01L23/532 , H01L29/40
摘要： PROBLEM TO BE SOLVED: To suppress diffusion of copper atoms and to prevent peeling in the interface of a copper film and a first conductive film by using a material whose difference of a grating constant with copper is small as a first conductor film material. SOLUTION: An insulating film 13 formed of a silicon oxide film and the like is formed on a whole face at the upper part of a MOS transistor. A plug formed of a main conductor film 15 coating adjacent conductor films 14a and 14b being first conductor films for diffusion prevention is formed in a contact hole formed in the insulating film 13 and it is connected to diffusion layers 2-5. When a copper film is used as the main conductor film 15, the adjacent conductor films 14a and 14b use one type among rhodium, ruthenium, iridium, osmium or white gold, whose lattice constant with the copper film is small, as a material. Thus, peeling at an interface between the copper film and the adjacent conductor films 14a and 14b can be prevented.

6. 发明专利

JPH11204753A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH11204753A
公开(公告)日：1999-07-30
申请号：JP34882397
申请日：1997-12-18
申请人： HITACHI LTD
发明人： NAKAMURA YOSHITAKA , ASANO ISAMU , KAWAKITA KEIZO , YAMADA SATORU
IPC分类号： H01L21/768 , H01L21/8242 , H01L23/522 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To facilitate boring of connection holes for connecting different wiring layers and burying a conductor film. SOLUTION: At peripheral circuit regions of DRAM, connection holes for electrically connecting a first layer wiring 14 and a second layer wiring 26 are twice bored to form connection holes 17a, 17b, and, after forming the connection holes 17a, 17b, plugs 18a, 25a are formed in the respective connection holes 17a, 17b.

7. 发明专利

JPH1126719A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH1126719A
公开(公告)日：1999-01-29
申请号：JP17370097
申请日：1997-06-30
申请人： HITACHI LTD
发明人： ASANO ISAMU , KAWAKITA KEIZO , YAMADA SATORU , IMAI AKIRA , NAKAMURA YOSHITAKA
IPC分类号： H01L27/08 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To prevent such a defect that an insulating film on a sidewall of a groove of a large area formed in a thick insulating film is peeled off. SOLUTION: After a SOG film 57 having a sufficient thickness to fill a groove 55 and a slot 59 formed in a silicon oxide film 53 is deposited, the SOG film 57 is etched back to expose a polycrystalline silicon film 56 for a lower electrode. Then, this polycrystalline silicon film 56 is etched back to leave only the groove 55 and the slot 59. At this point, an upper part of a groove 80 of a large area is covered with a photoresist film 81, thus preventing the SOG film 57 inside of the groove 80 from being etched back.

8. 发明专利

JPH1126717A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH1126717A
公开(公告)日：1999-01-29
申请号：JP17336997
申请日：1997-06-30
申请人： HITACHI LTD
发明人： YOSHIDA MAKOTO , KAWAKITA KEIZO , KUMAUCHI TAKAHIRO , YAMADA SATORU , NAKAMURA YOSHITAKA , ASANO ISAMU , TADAKI YOSHITAKA
IPC分类号： H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To shorten the period for development by forming the lower electrode having a crown structure in consideration of the embedding limit of an upper electrode, the resolution limit of photolithography technology and the minimum processing dimension. SOLUTION: The lower electrode having a crown structure is considered as the lower electrode which does not use a rough-surface conducting film, as the lower electrode which uses the rough-surface conducting film only for an inner film, as the lower electrode which uses the rough-surface conducting film only for an outer wall, and as the lower electrode which uses the rough-surface conducting film for both the inner wall and the outer wall. When the defective operation of an information storing capacitor element caused by the insufficient deposition of the conducting film of the upper electrode is caused by the inner short circuit and the occurrence of the leakage of the stored electric charge caused by the insufficient outer space between the lower electrodes is caused by the outer short circuit, the limited value of the inner short circuit and the limited value of the outer short circuit are obtained by computation. The photo-lithography limits of a concave crown and a convex crown are obtained by computation. The limits are corrected by the minimum processing dimension. The optimum height of the lower electrode and the inner space are indicated with thick solid lines.

9. 发明专利

JPH1126716A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH1126716A
公开(公告)日：1999-01-29
申请号：JP17336897
申请日：1997-06-30
申请人： HITACHI LTD
发明人： ASAKURA HISAO , ASANO ISAMU , TADAKI YOSHITAKA , KAWAKITA KEIZO , KAJITANI KAZUHIKO , NAKAMURA MASAYUKI , NAGAI AKIRA
IPC分类号： H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To restrain the flow of an F-N current in a gate insulating film of a MIS transistor constituting a DRAM, and improve the driving capability of a predetermined MIS transistor constituting the DRAM. SOLUTION: A DRAM constituted by a MOSFET Q for memory cell selection and a capacitor C connected in series with the MOSFET Q is provided on a semiconductor substrate 1, and a method of applying a negative bias voltage to a word line when the MOSFET Q for memory cell selection is off is employed. In this case the thickness of a gate insulating film 5i of a MOSFET which includes the MOSFET Q for memory cell selection and requires a relatively high driving voltage is made greater than the thickness of gate insulating films 8i, 10i of MOSFETs Qn, Qp which require a relatively high current driving capability.

10. 发明专利

JPH1126715A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH1126715A
公开(公告)日：1999-01-29
申请号：JP17336797
申请日：1997-06-30
申请人： HITACHI LTD
发明人： ASANO ISAMU , KAWAKITA KEIZO , NAKAMURA YOSHITAKA , YAMADA SATORU
IPC分类号： H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To improve the work precision of a through-hole connecting an upper electrode of an information storage capacitance element arranged on an upper part of a MISFET for memory cell selection and a wiring for power supply, without increasing the chip size. SOLUTION: By depositing, in a peripheral circuit region of a DRAM, a thick silicon oxide film (53) having a thickness equivalent to the height of an information storage capacitance element C of a memory cell, a step between a memory array and the peripheral circuit region is eliminated and a boundary portion between the memory array and the peripheral circuit region is made plane. Through a through-hole 74 formed directly above a slot 55a formed in the plane boundary portion, a third wiring 78 for power supply and an upper electrode of the information storage capacitance element C are electrically connected with each other.

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