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51. 发明授权

US5017990A Raised base bipolar transistor structure and its method of fabrication 失效
标题翻译：基极双极晶体管结构及其制作方法
公开(公告)号：US5017990A
公开(公告)日：1991-05-21
申请号：US445251
申请日：1989-12-01
申请人： Tze-Chiang Chen , Ching-Te Kent Chuang , Guann-Pyng Li , Tak Hung Ning
发明人： Tze-Chiang Chen , Ching-Te Kent Chuang , Guann-Pyng Li , Tak Hung Ning
IPC分类号： H01L29/73 , H01L21/331 , H01L29/10 , H01L29/732
CPC分类号： H01L29/66287 , H01L29/1004 , H01L29/732
摘要： The invention relates to a bipolar transistor structure which includes a layer of semiconductor material having a single crystal raised base, a single crystal or polycrystalline emitter and adjacent polycrystalline regions which provide an electrical connection to the emitter. The invention also relates to the method of fabricating such a structure and includes the step of depositing a conformal layer of semiconductor material of one conductivity type over a region of opposite conductivity and over insulation such that single crystal and polycrystalline regions form over single crystal material and insulation, respectively. In a subsequent step, a layer of opposite conductivity type semiconductor material is deposited on the first layer forming single crystal or polycrystalline material over single crystal and polycrystalline material over polycrystalline. Then, in a final step, the structure is subjected to an out-diffusion step which simultaneously forms a single crystal emitter region of opposite conductivity type, a p-n junction in the one conductivity type single crystal region and regions of opposite conductivity type which act as an interconnection to the emitter region.

52. 发明授权

US09059245B2 Semiconductor-on-insulator (SOI) substrates with ultra-thin SOI layers and buried oxides 有权
标题翻译：具有超薄SOI层和掩埋氧化物的绝缘体上半导体（SOI）衬底
公开(公告)号：US09059245B2
公开(公告)日：2015-06-16
申请号：US13483781
申请日：2012-05-30
申请人： Tze-Chiang Chen , Joel P. de Souza , Devendra K. Sadana , Ghavam G. Shahidi
发明人： Tze-Chiang Chen , Joel P. de Souza , Devendra K. Sadana , Ghavam G. Shahidi
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76243
摘要： Semiconductor-on-insulator (SOI) substrates including a buried oxide (BOX) layer having a thickness of less than 300 Å are provided. The (SOI) substrates having the thin BOX layer are provided using a method including a step in which oxygen ions are implanted at high substrate temperatures (greater than 600° C.), and at a low implant energy (less than 40 keV). An anneal step in an oxidizing atmosphere follows the implant step and is performed at a temperature less than 1250° C. The anneal step in oxygen containing atmosphere converts the region containing implanted oxygen atoms formed by the implant step into a BOX having a thickness of less than 300 Å. In some instances, the top semiconductor layer of the SOI substrate has a thickness of less than 300 Å.
摘要翻译：提供了包括厚度小于300埃的掩埋氧化物（BOX）层的绝缘体上半导体（SOI）衬底。使用包括以高衬底温度（大于600℃）和低注入能量（小于40keV）注入氧离子的步骤的方法提供具有薄BOX层的（SOI）衬底。氧化气氛中的退火步骤遵循注入步骤，并且在低于1250℃的温度下进行。含氧气氛中的退火步骤将包含由注入步骤形成的注入的氧原子的区域转换成厚度较小的BOX 比300Å。在一些情况下，SOI衬底的顶部半导体层具有小于300埃的厚度。

53. 发明申请

US20130320483A1 SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATES WITH ULTRA-THIN SOI LAYERS AND BURIED OXIDES 有权
标题翻译：半导体绝缘体（SOI）衬底，具有超薄SOI层和铜氧化物
公开(公告)号：US20130320483A1
公开(公告)日：2013-12-05
申请号：US13483781
申请日：2012-05-30
申请人： Tze-Chiang Chen , Joel P. de Souza , Devendra K. Sadana , Ghavam G. Shahidi
发明人： Tze-Chiang Chen , Joel P. de Souza , Devendra K. Sadana , Ghavam G. Shahidi
IPC分类号： H01L21/762 , H01L29/02
CPC分类号： H01L21/76243
摘要： Semiconductor-on-insulator (SOI) substrates including a buried oxide (BOX) layer having a thickness of less than 300 Å are provided. The (SOI) substrates having the thin BOX layer are provided using a method including a step in which oxygen ions are implanted at high substrate temperatures (greater than 600° C.), and at a low implant energy (less than 40 keV). An anneal step in an oxidizing atmosphere follows the implant step and is performed at a temperature less than 1250° C. The anneal step in oxygen containing atmosphere converts the region containing implanted oxygen atoms formed by the implant step into a BOX having a thickness of less than 300 Å. In some instances, the top semiconductor layer of the SOI substrate has a thickness of less than 300 Å.
摘要翻译：提供了包括厚度小于300埃的掩埋氧化物（BOX）层的绝缘体上半导体（SOI）衬底。使用包括以高衬底温度（大于600℃）和低注入能量（小于40keV）注入氧离子的步骤的方法提供具有薄BOX层的（SOI）衬底。氧化气氛中的退火步骤遵循注入步骤，并且在低于1250℃的温度下进行。含氧气氛中的退火步骤将包含由注入步骤形成的注入的氧原子的区域转换成厚度较小的BOX 比300Å。在一些情况下，SOI衬底的顶部半导体层具有小于300埃的厚度。

54. 发明授权

US07790592B2 Method to fabricate metal gate high-k devices 失效
标题翻译：制造金属栅极高k器件的方法
公开(公告)号：US07790592B2
公开(公告)日：2010-09-07
申请号：US11927749
申请日：2007-10-30
申请人： Tze-Chiang Chen , Bruce B. Doris , Vijay Narayanan , Vamsi Paruchuri
发明人： Tze-Chiang Chen , Bruce B. Doris , Vijay Narayanan , Vamsi Paruchuri
IPC分类号： H01L21/3205 , H01L21/4763 , H01L21/477 , H01L27/088
CPC分类号： H01L21/823842 , H01L21/28079 , H01L21/823857 , H01L21/823878 , H01L29/517
摘要： Disclosed is a method to fabricate a semiconductor device, and a device fabricated in accordance with the method. The method includes providing a substrate comprised of silicon; performing a shallow trench isolation process to delineate nFET and pFET active areas and, within each active area, forming a gate structure over a surface of the substrate, the gate structure comprising in order from the surface of the substrate, a layer of high dielectric constant oxide, a layer comprised of a metal, a layer comprised of amorphous silicon, and a layer comprised of polycrystalline silicon. The layer comprised of amorphous silicon is provided to substantially prevent regrowth of the high dielectric constant oxide layer in a vertical direction during at least a deposition and processing of the polycrystalline silicon layer and/or metal layer.
摘要翻译：公开了一种制造半导体器件的方法，以及根据该方法制造的器件。该方法包括提供由硅构成的衬底; 执行浅沟槽隔离工艺以描绘nFET和pFET有源区域，并且在每个有源区域内，在衬底的表面上形成栅极结构，所述栅极结构从衬底的表面依次包括高介电常数氧化物，由金属构成的层，由非晶硅构成的层以及由多晶硅构成的层。提供由非晶硅组成的层，以至少在多晶硅层和/或金属层的沉积和加工过程中基本上防止高介电常数氧化物层在垂直方向上的再生长。

55. 发明申请

US20100112800A1 CMOS STRUCTURE AND METHOD FOR FABRICATION THEREOF USING MULTIPLE CRYSTALLOGRAPHIC ORIENTATIONS AND GATE MATERIALS 有权
标题翻译： CMOS结构及其使用多种晶体取向和栅极材料制造的方法
公开(公告)号：US20100112800A1
公开(公告)日：2010-05-06
申请号：US12683535
申请日：2010-01-07
申请人： Tze-Chiang Chen , Meikei Ieong , Rajarao Jammy , Mukesh V. Khare , Chun-yung Sung , Richard Wise , Hongwen Yan , Ying Zhang
发明人： Tze-Chiang Chen , Meikei Ieong , Rajarao Jammy , Mukesh V. Khare , Chun-yung Sung , Richard Wise , Hongwen Yan , Ying Zhang
IPC分类号： H01L21/28
CPC分类号： H01L21/28079 , H01L21/823807 , H01L21/823842 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/6659
摘要： Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.
摘要翻译：制造CMOS结构的方法使用位于半导体衬底的第一取向区域上方的第一栅极堆叠。第二栅极材料层位于第一栅极叠层上方和半导体衬底的横向相邻的第二取向区域上。平坦化层位于第二栅极材料层上。平面化层和第二栅极材料层被非选择性蚀刻以形成近似第一栅极堆叠的高度的第二栅极堆叠。也可以在第一栅极叠层上形成蚀刻停止层。所得到的CMOS结构可以包括不同的栅极电介质，金属栅极和硅栅极。

56. 发明申请

US20100041221A1 HIGH PERFORMANCE CMOS CIRCUITS, AND METHODS FOR FABRICATING SAME 有权
标题翻译：高性能CMOS电路及其制造方法
公开(公告)号：US20100041221A1
公开(公告)日：2010-02-18
申请号：US12541562
申请日：2009-08-14
申请人： John C. Arnold , Glenn A. Biery , Alessandro C. Callegari , Tze-Chiang Chen , Michael P. Chudzik , Bruce B. Doris , Michael A. Gribelyuk , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Joseph S. Newbury , Vamsi K. Paruchuri , Michelle L. Steen
发明人： John C. Arnold , Glenn A. Biery , Alessandro C. Callegari , Tze-Chiang Chen , Michael P. Chudzik , Bruce B. Doris , Michael A. Gribelyuk , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Joseph S. Newbury , Vamsi K. Paruchuri , Michelle L. Steen
IPC分类号： H01L21/28
CPC分类号： H01L21/823857 , H01L21/823842
摘要： The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer, a metallic gate conductor, and a silicon-containing gate conductor. The second gate stack is located over a second device region (e.g., a p-FET device region) in the semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor. The first and second gate stacks can be formed over the semiconductor substrate in an integrated manner by various methods of the present invention.
摘要翻译：本发明涉及互补金属氧化物半导体（CMOS）电路，其各自包含至少第一和第二栅极堆叠。第一栅极堆叠位于半导体衬底中的第一器件区域（例如，n-FET器件区域）上，并且至少从底部至顶部包括栅极介电层，金属栅极导体和含硅的门导体。第二栅极堆叠位于半导体衬底中的第二器件区域（例如，p-FET器件区域）上，并且至少包括从栅极电介质层和含硅栅极导体的底部到顶部。可以通过本发明的各种方法以集成的方式在半导体衬底上形成第一和第二栅极叠层。

57. 发明授权

US07498235B2 Method for fabricating SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) substrates 有权
标题翻译：用于制造绝缘体上硅（SGOI）和绝缘体上（GeI）绝缘体（GOI）基板的方法
公开(公告)号：US07498235B2
公开(公告)日：2009-03-03
申请号：US11924207
申请日：2007-10-25
申请人： Tze-chiang Chen , Guy M. Cohen , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
发明人： Tze-chiang Chen , Guy M. Cohen , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
IPC分类号： H01L21/30
CPC分类号： H01L21/76254 , H01L31/02327 , H01L31/028 , H01L31/1812 , Y02E10/547
摘要： A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.
摘要翻译：提供了绝缘体上（锗）绝缘体（GOI）衬底材料的方法，通过该方法生产的GOI衬底材料和至少可以包括本发明的GOI衬底材料的各种结构。 GOI衬底材料至少包括衬底，位于衬底顶部的掩埋绝缘体层，以及位于掩埋绝缘体层顶部的优选纯Ge的Ge含有层。在本发明的GOI基板材料中，Ge含有层也可以称为GOI膜。 GOI膜是可以形成器件的本发明的基底材料的层。

58. 发明申请

US20080241369A1 METHOD OF FABRICATING A MAGNETIC SHIFT REGISTER 有权
标题翻译：制造磁性移位寄存器的方法
公开(公告)号：US20080241369A1
公开(公告)日：2008-10-02
申请号：US12114636
申请日：2008-05-02
申请人： Tze-chiang Chen , Stuart S.P. Parkin
发明人： Tze-chiang Chen , Stuart S.P. Parkin
IPC分类号： B05D5/12
CPC分类号： H01L29/82 , G11C11/14 , G11C19/02 , G11C19/0808 , G11C19/0841
摘要： A magnetic data track used in a magnetic shift register memory system may be fabricated by forming a multilayered stack of alternating dielectric and/or silicon layers. A trench is etched in the multi-layer stack structure. A selective etching process is used to corrugate the walls of trench. A seed layer is applied to the walls and bottom of the trench; the seed layer is covered with a magnetic layer. The trench is filled with an insulating material. A patterned layer is applied and portions of insulating material exposed by the pattern are removed, forming holes. Magnetic material and seed layer exposed in holes is selectively removed. The holes are filled with insulating material and connecting leads are attached to data tracks.
摘要翻译：用于磁移位寄存器存储器系统的磁数据磁道可以通过形成交替的电介质层和/或硅层的多层叠层来制造。在多层堆叠结构中蚀刻沟槽。使用选择性蚀刻工艺来使沟槽的壁波纹化。种子层施加到沟槽的壁和底部; 种子层被磁性层覆盖。沟槽填充绝缘材料。施加图案层，去除由图案露出的部分绝缘材料，形成孔。选择性地除去暴露在孔中的磁性材料和种子层。孔中填充绝缘材料，连接引线连接到数据轨道。

59. 发明申请

US20080050887A1 METHOD FOR FABRICATING SiGe-ON-INSULATOR (SGOI) AND Ge-ON-INSULATOR (GOI) SUBSTRATES 有权
标题翻译：用于制造SiGe-ON绝缘体（SGOI）和Ge-ON-Insulator（GOI）衬底的方法
公开(公告)号：US20080050887A1
公开(公告)日：2008-02-28
申请号：US11924207
申请日：2007-10-25
申请人： Tze-chiang Chen , Guy Cohen , Alexander Reznicek , Devendra Sadana , Ghavam Shahidi
发明人： Tze-chiang Chen , Guy Cohen , Alexander Reznicek , Devendra Sadana , Ghavam Shahidi
IPC分类号： H01L21/30
CPC分类号： H01L21/76254 , H01L31/02327 , H01L31/028 , H01L31/1812 , Y02E10/547
摘要： A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.
摘要翻译：提供了绝缘体上（锗）绝缘体（GOI）衬底材料的方法，通过该方法生产的GOI衬底材料和至少可以包括本发明的GOI衬底材料的各种结构。 GOI衬底材料至少包括衬底，位于衬底顶部的掩埋绝缘体层，以及位于掩埋绝缘体层顶部的优选纯Ge的Ge含有层。在本发明的GOI基板材料中，Ge含有层也可以称为GOI膜。 GOI膜是可以形成器件的本发明的基底材料的层。

60. 发明申请

US20070152276A1 High performance CMOS circuits, and methods for fabricating the same 审中-公开
标题翻译：高性能CMOS电路及其制造方法
公开(公告)号：US20070152276A1
公开(公告)日：2007-07-05
申请号：US11323578
申请日：2005-12-30
申请人： John Arnold , Glenn Biery , Alessandro Callegari , Tze-Chiang Chen , Michael Chudzik , Bruce Doris , Michael Gribelyuk , Young-Hee Kim , Barry Linder , Vijay Narayanan , Joseph Newbury , Vamsi Paruchuri , Michelle Steen
发明人： John Arnold , Glenn Biery , Alessandro Callegari , Tze-Chiang Chen , Michael Chudzik , Bruce Doris , Michael Gribelyuk , Young-Hee Kim , Barry Linder , Vijay Narayanan , Joseph Newbury , Vamsi Paruchuri , Michelle Steen
IPC分类号： H01L29/94
CPC分类号： H01L21/823857 , H01L21/823842
摘要： The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer, a metallic gate conductor, and a silicon-containing gate conductor. The second gate stack is located over a second device region (e.g., a p-FET device region) in the semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor. The first and second gate stacks can be formed over the semiconductor substrate in an integrated manner by various methods of the present invention.
摘要翻译：本发明涉及互补金属氧化物半导体（CMOS）电路，其各自包含至少第一和第二栅极堆叠。第一栅极堆叠位于半导体衬底中的第一器件区域（例如，n-FET器件区域）上，并且至少从底部至顶部包括栅极介电层，金属栅极导体和含硅的门导体。第二栅极堆叠位于半导体衬底中的第二器件区域（例如，p-FET器件区域）上，并且至少包括从栅极电介质层和含硅栅极导体的底部到顶部。可以通过本发明的各种方法以集成的方式在半导体衬底上形成第一和第二栅极叠层。

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