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41. 发明申请

US20050124120A1 Method and circuit for multiplying signals with a transistor having more than one independent gate structure 失效
公开(公告)号：US20050124120A1
公开(公告)日：2005-06-09
申请号：US10728621
申请日：2003-12-05
申请人： Yang Du , Leo Mathew
发明人： Yang Du , Leo Mathew
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/84 , H01L29/423 , H01L29/786 , H01L29/80 , H01L21/3205 , H01L21/4763 , H01L31/112
CPC分类号： H01L29/42384 , H01L21/823437 , H01L21/84 , H01L29/66818 , H01L29/785
摘要： A double gate semiconductor device (2006) is used beneficially as a multiplier (2000). The double gate semiconductor device (2006) has a lateral fin (105) as the channel region with the gates formed opposite each other on both sides of the fin. The lateral positioning of the fin provides symmetry between the two gates. To increase drive current, multiple transistors are easily connected in parallel by having a continuous fin structure (2106) with alternating source/drain terminals (2120, 2122, 2124, 2126) in which the sources are connected together and the drains are connected together. Gates (2116, 2110) are positioned between each pair of adjacent source/drain terminals and electrically connected together. The multiplier (2000) may also be used as a mixer and further as a phase detector.

42. 发明申请

US20120045866A1 METHOD OF FORMING AN ELECTRONIC DEVICE USING A SEPARATION TECHNIQUE 审中-公开
标题翻译：使用分离技术形成电子设备的方法
公开(公告)号：US20120045866A1
公开(公告)日：2012-02-23
申请号：US13287932
申请日：2011-11-02
申请人： Leo Mathew , Dharmesh Jawarani
发明人： Leo Mathew , Dharmesh Jawarani
IPC分类号： H01L21/762
CPC分类号： H01L31/1804 , H01L31/1896 , Y02E10/547 , Y02P70/521
摘要： A method of forming an electronic device can include forming a patterned layer adjacent to a side of a substrate including a semiconductor material. The method can also include separating a semiconductor layer and the patterned layer from the substrate, wherein the semiconductor layer is a portion of the substrate.
摘要翻译：形成电子器件的方法可以包括形成与包括半导体材料的衬底的一侧相邻的图案化层。该方法还可以包括从衬底分离半导体层和图案化层，其中半导体层是衬底的一部分。

43. 发明授权

US07829447B2 Semiconductor structure pattern formation 有权
标题翻译：半导体结构图形形成
公开(公告)号：US07829447B2
公开(公告)日：2010-11-09
申请号：US11419304
申请日：2006-05-19
申请人： Leo Mathew , Rode R. Mora , Tab A. Stephens , Tien Ying Luo
发明人： Leo Mathew , Rode R. Mora , Tab A. Stephens , Tien Ying Luo
IPC分类号： H01L21/22 , H01L21/38
CPC分类号： H01L29/785 , H01L29/66795 , Y10S438/942
摘要： Forming structures such as fins in a semiconductor layer according to a pattern formed by oxidizing a sidewall of a layer of oxidizable material. In one embodiment, source/drain pattern structures and a fin pattern structures are patterned in the oxidizable layer. The fin pattern structure is then masked from an oxidation process that grows oxide on the sidewalls of the channel pattern structure and the top surface of the source/drain pattern structures. The remaining oxidizable material of the channel pattern structure is subsequently removed leaving a hole between two portions of the oxide layer. These two portions are used in one embodiment as a mask for patterning the semiconductor layer to form two fins. This patterning also leaves the source/drain structures connected to the fins.
摘要翻译：根据通过氧化可氧化材料层的侧壁形成的图案在半导体层中形成诸如翅片的结构。在一个实施例中，在可氧化层中图案化源极/漏极图案结构和鳍状图案结构。然后从在沟道图案结构的侧壁和源极/漏极图案结构的顶表面上生长氧化物的氧化过程掩蔽鳍状图案结构。随后去除沟道图案结构的剩余可氧化材料，留下氧化物层的两个部分之间的孔。这两个部分在一个实施例中用作用于图案化半导体层以形成两个散热片的掩模。该图案化还使得源极/漏极结构连接到鳍片。

44. 发明授权

US07803670B2 Twisted dual-substrate orientation (DSO) substrates 有权
标题翻译：扭转双基板取向（DSO）底物
公开(公告)号：US07803670B2
公开(公告)日：2010-09-28
申请号：US11458902
申请日：2006-07-20
申请人： Ted R. White , Leo Mathew , Bich-Yen Nguyen , Zhonghai Shi , Voon-Yew Thean , Mariam G. Sadaka
发明人： Ted R. White , Leo Mathew , Bich-Yen Nguyen , Zhonghai Shi , Voon-Yew Thean , Mariam G. Sadaka
IPC分类号： H01L21/00
CPC分类号： H01L21/845 , H01L21/76264 , H01L27/1203 , H01L27/1207 , H01L27/1211 , H01L29/045 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要： A semiconductor process and apparatus provide a dual or hybrid substrate by forming a second semiconductor layer (214) that is isolated from, and crystallographically rotated with respect to, an underlying first semiconductor layer (212) by a buried insulator layer (213); forming an STI region (218) in the second semiconductor layer (214) and buried insulator layer (213); exposing the first semiconductor layer (212) in a first area (219) of a STI region (218); epitaxially growing a first epitaxial semiconductor layer (220) from the exposed first semiconductor layer (212); and selectively etching the first epitaxial semiconductor layer (220) and the second semiconductor layer (214) to form CMOS FinFET channel regions (e.g., 223) and planar channel regions (e.g., 224) from the first epitaxial semiconductor layer (220) and the second semiconductor layer (214).
摘要翻译：半导体工艺和装置通过形成第二半导体层（214）提供双或混合衬底，所述第二半导体层通过掩埋绝缘体层与基底第一半导体层隔离并且相对于下面的第一半导体层进行晶体学旋转; 在第二半导体层（214）和掩埋绝缘体层（213）中形成STI区（218）; 在STI区域（218）的第一区域（219）中暴露所述第一半导体层（212）; 从所述暴露的第一半导体层（212）外延生长第一外延半导体层（220）; 以及选择性地蚀刻所述第一外延半导体层（220）和所述第二半导体层（214）以形成来自所述第一外延半导体层（220）的CMOS FinFET沟道区域（例如，223）和平面沟道区域（例如，224）第二半导体层（214）。

45. 发明授权

US07754560B2 Integrated circuit using FinFETs and having a static random access memory (SRAM) 有权
标题翻译：使用FinFET并具有静态随机存取存储器（SRAM）的集成电路
公开(公告)号：US07754560B2
公开(公告)日：2010-07-13
申请号：US11328779
申请日：2006-01-10
申请人： James D. Burnett , Leo Mathew , Byoung W. Min
发明人： James D. Burnett , Leo Mathew , Byoung W. Min
IPC分类号： H01L21/8244 , H01L29/78
CPC分类号： H01L27/1108 , H01L27/1203 , H01L27/1207 , H01L27/1211 , H01L29/045 , H01L29/66795 , H01L29/785
摘要： An integrated circuit includes a logic circuit and a memory cell. The logic circuit includes a P-channel transistor, and the memory cell includes a P-channel transistor. The P-channel transistor of the logic circuit includes a channel region. The channel region has a portion located along a sidewall of a semiconductor structure having a surface orientation of (110). The portion of the channel region located along the sidewall has a first vertical dimension that is greater than a vertical dimension of any portion of the channel region of the P-channel transistor of the memory cell located along a sidewall of a semiconductor structure having a surface orientation of (110).
摘要翻译：集成电路包括逻辑电路和存储单元。逻辑电路包括P沟道晶体管，并且存储单元包括P沟道晶体管。逻辑电路的P沟道晶体管包括沟道区。沟道区具有位于具有（110）表面取向的半导体结构的侧壁的部分。位于沿着侧壁的通道区域的部分具有第一垂直尺寸，其大于沿着具有表面的半导体结构的侧壁的存储单元的P沟道晶体管的沟道区的任何部分的垂直尺寸（110）的方向。

46. 发明授权

US07585735B2 Asymmetric spacers and asymmetric source/drain extension layers 有权
标题翻译：非对称隔离层和不对称源极/漏极延伸层
公开(公告)号：US07585735B2
公开(公告)日：2009-09-08
申请号：US11047946
申请日：2005-02-01
申请人： Leo Mathew , Yang Du , Bich-Yen Nguyen , Voon-Yew Thean
发明人： Leo Mathew , Yang Du , Bich-Yen Nguyen , Voon-Yew Thean
IPC分类号： H01L21/8234
CPC分类号： H01L29/4983 , H01L29/165 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66628 , H01L29/66659 , H01L29/7843
摘要： A method of forming a semiconductor device is provided in which a substrate (102) is provided which has a gate dielectric layer (106) disposed thereon, and a gate electrode (116) having first and second sidewalls is formed over the gate dielectric layer. First (146) and second (150) extension spacer structures are formed adjacent the first and second sidewalls, respectively. In the resulting device: (a) the first and second extension spacer structures have different dimensions; (b) the first and second extension spacer structures comprise first and second distinct materials; (c) the device has asymmetric source/drain extensions (162); and/or (d) the device has an oxide layer (160) disposed between the first extension spacer structure and the gate electrode, and either (i) the device has no dielectric layer disposed between the second extension spacer structure and the gate electrode, or (ii) the device has a second dielectric layer disposed between the second extension spacer structure and the gate electrode, and the first dielectric layer is substantially thicker than the second dielectric layer.
摘要翻译：提供一种形成半导体器件的方法，其中设置有其上设置有栅介质层（106）的衬底（102），并且在栅极介电层上形成具有第一和第二侧壁的栅电极（116）。分别在第一和第二侧壁附近形成第一（146）和第二（150）延伸间隔结构。在所得装置中：（a）第一和第二延伸间隔结构具有不同的尺寸; （b）第一和第二延伸间隔结构包括第一和第二不同材料; （c）该器件具有不对称的源极/漏极延伸部分（162）; 和/或（d）所述器件具有设置在所述第一延伸间隔物结构和所述栅电极之间的氧化物层（160），以及（i）所述器件在所述第二延伸间隔物结构和所述栅电极之间没有设置介电层，或者（ii）该器件具有设置在第二延伸间隔物结构和栅极之间的第二介电层，并且第一介电层基本上比第二介电层更厚。

47. 发明授权

US07566623B2 Electronic device including a semiconductor fin having a plurality of gate electrodes and a process for forming the electronic device 有权
标题翻译：形成包括具有多个栅电极的半导体鳍片的电子器件的工艺
公开(公告)号：US07566623B2
公开(公告)日：2009-07-28
申请号：US11670833
申请日：2007-02-02
申请人： Leo Mathew , Brian J. Goolsby , Tab A. Stephens
发明人： Leo Mathew , Brian J. Goolsby , Tab A. Stephens
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： An electronic device can include a semiconductor fin with a first gate electrode adjacent to a first wall, and a second gate electrode adjacent to a second wall. In one embodiment, a conductive member can be formed overlying the semiconductor fin, and a portion of the conductive member can be reacted to form the first and second gate electrodes. In another embodiment, a patterned masking layer can be formed including a masking member over a gate electrode layer, and portion of the masking member overlying the semiconductor fin can be removed. In still another embodiment, a first fin-type transistor structure can include the semiconductor fin, the first and second gate electrodes, and a first insulating cap. The electronic device can also include a second fin-type transistor structure having a second insulating cap thicker than the first insulating cap.
摘要翻译：电子设备可以包括具有与第一壁相邻的第一栅电极和与第二壁相邻的第二栅电极的半导体鳍。在一个实施例中，可以形成覆盖半导体鳍片的导电构件，并且导电构件的一部分可以反应以形成第一和第二栅电极。在另一个实施例中，可以形成图案化掩模层，其包括在栅极电极层上的掩模构件，并且可以去除覆盖在半导体鳍片上的掩蔽构件的部分。在另一个实施例中，第一鳍式晶体管结构可以包括半导体鳍片，第一和第二栅电极以及第一绝缘帽。电子器件还可以包括具有比第一绝缘盖更厚的第二绝缘帽的第二鳍式晶体管结构。

48. 发明授权

US07494832B2 Semiconductor optical devices and method for forming 失效
标题翻译：半导体光学器件及其形成方法
公开(公告)号：US07494832B2
公开(公告)日：2009-02-24
申请号：US11465402
申请日：2006-08-17
申请人： Leo Mathew , Yang Du , Voon-Yew Thean
发明人： Leo Mathew , Yang Du , Voon-Yew Thean
IPC分类号： H01L21/00
CPC分类号： H01S5/0262 , B82Y20/00 , H01L27/14643 , H01L27/14687 , H01L29/66803 , H01L29/785 , H01L31/0384 , H01L31/105 , H01L33/08 , H01L33/18 , H01L33/24 , H01S3/169 , H01S5/0261 , H01S5/0421 , H01S5/0425 , H01S5/2205 , H01S5/304 , Y10S977/95
摘要： A semiconductor optical device includes an insulating layer, a photoelectric region formed on the insulating layer, a first electrode having a first conductivity type formed on the insulating layer and contacting a first side of the photoelectric region, and a second electrode having a second conductivity type formed on the insulating layer and contacting a second side of the photoelectric region. The photoelectric region may include nanoclusters or porous silicon such that the device operates as a light emitting device. Alternatively, the photoelectric region may include an intrinsic semiconductor material such that the device operates as a light sensing device. The semiconductor optical device may be further characterized as a vertical optical device. In one embodiment, different types of optical devices, including light emitting and light sensing devices, may be integrated together. The optical devices may also be integrated with other types of semiconductor devices, such as vertical field-effect transistors.
摘要翻译：半导体光学器件包括绝缘层，形成在绝缘层上的光电区域，形成在绝缘层上并与光电区域的第一侧接触的具有第一导电类型的第一电极和具有第二导电类型的第二电极形成在绝缘层上并与光电区域的第二面接触。光电区域可以包括纳米团簇或多孔硅，使得该器件作为发光器件工作。或者，光电区域可以包括本征半导体材料，使得该器件作为光感测装置工作。半导体光学器件可以被进一步表征为垂直光学器件。在一个实施例中，包括发光和光感测装置的不同类型的光学装置可以集成在一起。光学器件还可以与诸如垂直场效应晶体管的其它类型的半导体器件集成。

49. 发明申请

US20090039420A1 FINFET MEMORY CELL HAVING A FLOATING GATE AND METHOD THEREFOR 有权
标题翻译：具有浮动门的FINFET存储单元及其方法
公开(公告)号：US20090039420A1
公开(公告)日：2009-02-12
申请号：US11835548
申请日：2007-08-08
申请人： Vishal P. Trivedi , Leo Mathew
发明人： Vishal P. Trivedi , Leo Mathew
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/28273 , H01L29/66795 , H01L29/66825 , H01L29/785 , H01L29/7881
摘要： A fin field effect transistor (FinFET) memory cell and method of formation has a substrate for providing mechanical support. A first dielectric layer overlies the substrate. A fin structure overlies the dielectric layer and has a first current electrode and a second current electrode separated by a channel. A floating gate has a vertical portion that is adjacent to and electrically insulated from a side of the channel and has a horizontal portion overlying the first dielectric layer and extending laterally away from the channel. The floating gate stores electrical charge. A second dielectric layer is adjacent the floating gate. A control gate adjacent the second dielectric layer and physically separated from the floating gate by the second dielectric layer. The “L-shape” of the floating gate enhances capacitive coupling ratio between the control gate and the floating gate.
摘要翻译：鳍状场效应晶体管（FinFET）存储单元和形成方法具有用于提供机械支撑的基板。第一电介质层覆盖在衬底上。翅片结构覆盖在电介质层上，并具有由通道分开的第一电流电极和第二电流电极。浮动栅极具有与沟道的一侧相邻且电绝缘的垂直部分，并且具有覆盖第一介电层并横向延伸离开通道的水平部分。浮动门存储电荷。第二电介质层与浮动栅极相邻。与第二电介质层相邻并且通过第二电介质层物理地与浮置栅极隔离的控制栅极。浮栅的“L”形增加了控制栅和浮栅之间的电容耦合比。

50. 发明申请

US20080274600A1 Method to improve source/drain parasitics in vertical devices 有权
标题翻译：在垂直设备中改善源极/漏极寄生效应的方法
公开(公告)号：US20080274600A1
公开(公告)日：2008-11-06
申请号：US11800204
申请日：2007-05-04
申请人： Leo Mathew , John J. Hackenberg , David C. Sing , Tab A. Stephens , Daniel G. Tekleab , Vishal P. Trivedi
发明人： Leo Mathew , John J. Hackenberg , David C. Sing , Tab A. Stephens , Daniel G. Tekleab , Vishal P. Trivedi
IPC分类号： H01L21/00
CPC分类号： H01L21/26586 , H01L21/26513 , H01L21/2658 , H01L29/66803 , H01L29/785
摘要： A method for making a transistor is provided which comprises (a) providing a semiconductor structure having a gate (211) overlying a semiconductor layer (203), and having at least one spacer structure (213) disposed adjacent to said gate; (b) removing a portion of the semiconductor structure adjacent to the spacer structure, thereby exposing a portion (215) of the semiconductor structure which underlies the spacer structure; and (c) subjecting the exposed portion of the semiconductor structure to an angled implant (253, 254).
摘要翻译：提供一种制造晶体管的方法，其包括：（a）提供半导体结构，所述半导体结构具有覆盖半导体层（203）的栅极（211），并且具有邻近所述栅极设置的至少一个间隔结构（213）（b）去除与间隔结构相邻的半导体结构的一部分，从而暴露位于间隔结构下面的半导体结构的部分（215）; 和（c）将半导体结构的暴露部分经受成角度的植入物（253,254）。

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