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1. 发明申请

US20080274600A1 Method to improve source/drain parasitics in vertical devices 有权
标题翻译：在垂直设备中改善源极/漏极寄生效应的方法
公开(公告)号：US20080274600A1
公开(公告)日：2008-11-06
申请号：US11800204
申请日：2007-05-04
申请人： Leo Mathew , John J. Hackenberg , David C. Sing , Tab A. Stephens , Daniel G. Tekleab , Vishal P. Trivedi
发明人： Leo Mathew , John J. Hackenberg , David C. Sing , Tab A. Stephens , Daniel G. Tekleab , Vishal P. Trivedi
IPC分类号： H01L21/00
CPC分类号： H01L21/26586 , H01L21/26513 , H01L21/2658 , H01L29/66803 , H01L29/785
摘要： A method for making a transistor is provided which comprises (a) providing a semiconductor structure having a gate (211) overlying a semiconductor layer (203), and having at least one spacer structure (213) disposed adjacent to said gate; (b) removing a portion of the semiconductor structure adjacent to the spacer structure, thereby exposing a portion (215) of the semiconductor structure which underlies the spacer structure; and (c) subjecting the exposed portion of the semiconductor structure to an angled implant (253, 254).
摘要翻译：提供一种制造晶体管的方法，其包括：（a）提供半导体结构，所述半导体结构具有覆盖半导体层（203）的栅极（211），并且具有邻近所述栅极设置的至少一个间隔结构（213）（b）去除与间隔结构相邻的半导体结构的一部分，从而暴露位于间隔结构下面的半导体结构的部分（215）; 和（c）将半导体结构的暴露部分经受成角度的植入物（253,254）。

2. 发明申请

US20080173957A1 METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING A SYMMETRIC DIELECTRIC REGIONS AND STRUCTURE THEREOF 审中-公开
标题翻译：形成具有对称电介质区域的半导体器件及其结构的方法
公开(公告)号：US20080173957A1
公开(公告)日：2008-07-24
申请号：US11848612
申请日：2007-08-31
申请人： Leo Mathew , Venkat R. Kolagunta , David C. Sing
发明人： Leo Mathew , Venkat R. Kolagunta , David C. Sing
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/26506 , H01L21/26586 , H01L29/1083 , H01L29/665 , H01L29/6656 , H01L29/66659 , H01L29/7835 , H01L29/785 , H01L29/78624 , H01L2924/0002 , Y10S438/981 , H01L2924/00
摘要： A method for forming a semiconductor device including forming a semiconductor substrate; forming a gate electrode over the semiconductor substrate having a first side and a second side, and forming a gate dielectric under the gate electrode. The gate dielectric has a first area under the gate electrode and adjacent the first side of the gate electrode, a second area under the gate electrode and adjacent the second side of the gate electrode, and a third area under the gate electrode that is between the first area and the second area, wherein the first area is thinner than the second area, and the third area is thinner than the first area and is thinner than the second area.
摘要翻译：一种形成半导体器件的方法，包括形成半导体衬底; 在具有第一侧和第二侧的半导体衬底上形成栅电极，以及在栅极下形成栅极电介质。栅极电介质具有栅电极下方的第一区域，并且与栅电极的第一侧相邻，第二区域在栅电极下方并且邻近栅电极的第二侧，栅极下方的第三区域位于栅电极之间第一区域和第二区域，其中第一区域比第二区域薄，第三区域比第一区域薄，并且比第二区域薄。

3. 发明申请

US20080206939A1 SEMICONDUCTOR DEVICE WITH INTEGRATED RESISTIVE ELEMENT AND METHOD OF MAKING 失效
标题翻译：具有集成电阻元件的半导体器件及其制造方法
公开(公告)号：US20080206939A1
公开(公告)日：2008-08-28
申请号：US11680199
申请日：2007-02-28
申请人： Byoung W. Min , James K. Schaeffer , David C. Sing
发明人： Byoung W. Min , James K. Schaeffer , David C. Sing
IPC分类号： H01L21/8234
CPC分类号： H01L27/0629 , H01L28/20
摘要： A resistive device (44) and a transistor (42) are formed. Each uses a portion of a metal layer (18) that is formed at the same time and thus additional process steps are avoided to remove the metal from the resistive device. The metal used in the resistive device is selectively treated to increase the resistance in the resistive device. A polycrystalline semiconductor material layer (34) overlies the metal layer in the resistive device. The combination of these layers provides the resistive device. In one form the metal is treated after formation of the polycrystalline semiconductor material layer. In one form the metal treatment involves an implant of a species, such as oxygen, to increase the resistivity of the metal. Various transistor structures are formed using the untreated portion of the metal layer as a control electrode.
摘要翻译：形成电阻器件（44）和晶体管（42）。每个都使用同时形成的金属层（18）的一部分，因此避免了额外的工艺步骤以从电阻器件去除金属。选择性地处理在电阻器件中使用的金属以增加电阻器件中的电阻。多晶半导体材料层（34）覆盖电阻器件中的金属层。这些层的组合提供了电阻装置。在一种形式中，在形成多晶半导体材料层之后处理金属。在一种形式中，金属处理包括物质（例如氧）的植入物以增加金属的电阻率。使用金属层的未处理部分作为控制电极形成各种晶体管结构。

4. 发明授权

US07282426B2 Method of forming a semiconductor device having asymmetric dielectric regions and structure thereof 有权
标题翻译：形成具有不对称介电区域的半导体器件及其结构的方法
公开(公告)号：US07282426B2
公开(公告)日：2007-10-16
申请号：US11092289
申请日：2005-03-29
申请人： Leo Mathew , Venkat R. Kolagunta , David C. Sing
发明人： Leo Mathew , Venkat R. Kolagunta , David C. Sing
IPC分类号： H01L21/425
CPC分类号： H01L21/26506 , H01L21/26586 , H01L29/1083 , H01L29/665 , H01L29/6656 , H01L29/66659 , H01L29/7835 , H01L29/785 , H01L29/78624 , H01L2924/0002 , Y10S438/981 , H01L2924/00
摘要： A method for forming a semiconductor device including forming a semiconductor substrate; forming a gate electrode over the semiconductor substrate having a first side and a second side, and forming a gate dielectric under the gate electrode. The gate dielectric has a first area under the gate electrode and adjacent the first side of the gate electrode, a second area under the gate electrode and adjacent the second side of the gate electrode, and a third area under the gate electrode that is between the first area and the second area, wherein the first area is thinner than the second area, and the third area is thinner than the first area and is thinner than the second area.
摘要翻译：一种形成半导体器件的方法，包括形成半导体衬底; 在具有第一侧和第二侧的半导体衬底上形成栅电极，以及在栅极下形成栅极电介质。栅极电介质具有栅电极下方的第一区域，并且与栅电极的第一侧相邻，第二区域在栅电极下方并且邻近栅电极的第二侧，栅极下方的第三区域位于栅电极之间第一区域和第二区域，其中第一区域比第二区域薄，第三区域比第一区域薄，并且比第二区域薄。

5. 发明授权

US08258035B2 Method to improve source/drain parasitics in vertical devices 有权
标题翻译：在垂直设备中改善源极/漏极寄生效应的方法
公开(公告)号：US08258035B2
公开(公告)日：2012-09-04
申请号：US11800204
申请日：2007-05-04
申请人： Leo Mathew , John J. Hackenberg , David C. Sing , Tab A. Stephens , Daniel G. Tekleab , Vishal P. Trivedi
发明人： Leo Mathew , John J. Hackenberg , David C. Sing , Tab A. Stephens , Daniel G. Tekleab , Vishal P. Trivedi
IPC分类号： H01L21/336
CPC分类号： H01L21/26586 , H01L21/26513 , H01L21/2658 , H01L29/66803 , H01L29/785
摘要： A method for making a transistor is provided which comprises (a) providing a semiconductor structure having a gate (211) overlying a semiconductor layer (203), and having at least one spacer structure (213) disposed adjacent to said gate; (b) removing a portion of the semiconductor structure adjacent to the spacer structure, thereby exposing a portion (215) of the semiconductor structure which underlies the spacer structure; and (c) subjecting the exposed portion of the semiconductor structure to an angled implant (253, 254).
摘要翻译：提供一种制造晶体管的方法，其包括：（a）提供半导体结构，所述半导体结构具有覆盖半导体层（203）的栅极（211），并且具有邻近所述栅极设置的至少一个间隔结构（213）（b）去除与间隔结构相邻的半导体结构的一部分，从而暴露位于间隔结构下面的半导体结构的部分（215）; 和（c）将半导体结构的暴露部分经受成角度的植入物（253,254）。

6. 发明授权

US07648884B2 Semiconductor device with integrated resistive element and method of making 失效
标题翻译：具有集成电阻元件的半导体器件及其制造方法
公开(公告)号：US07648884B2
公开(公告)日：2010-01-19
申请号：US11680199
申请日：2007-02-28
申请人： Byoung W. Min , James K. Schaeffer , David C. Sing
发明人： Byoung W. Min , James K. Schaeffer , David C. Sing
IPC分类号： H01L21/20
CPC分类号： H01L27/0629 , H01L28/20
摘要： A resistive device (44) and a transistor (42) are formed. Each uses a portion of a metal layer (18) that is formed at the same time and thus additional process steps are avoided to remove the metal from the resistive device. The metal used in the resistive device is selectively treated to increase the resistance in the resistive device. A polycrystalline semiconductor material layer (34) overlies the metal layer in the resistive device. The combination of these layers provides the resistive device. In one form the metal is treated after formation of the polycrystalline semiconductor material layer. In one form the metal treatment involves an implant of a species, such as oxygen, to increase the resistivity of the metal. Various transistor structures are formed using the untreated portion of the metal layer as a control electrode.
摘要翻译：形成电阻器件（44）和晶体管（42）。每个都使用同时形成的金属层（18）的一部分，因此避免了额外的工艺步骤以从电阻器件去除金属。选择性地处理在电阻器件中使用的金属以增加电阻器件中的电阻。多晶半导体材料层（34）覆盖电阻器件中的金属层。这些层的组合提供了电阻装置。在一种形式中，在形成多晶半导体材料层之后处理金属。在一种形式中，金属处理包括物质（例如氧）的植入物以增加金属的电阻率。使用金属层的未处理部分作为控制电极形成各种晶体管结构。

7. 发明授权

US07323373B2 Method of forming a semiconductor device with decreased undercutting of semiconductor material 有权
标题翻译：半导体器件底切成形的方法
公开(公告)号：US07323373B2
公开(公告)日：2008-01-29
申请号：US11339133
申请日：2006-01-25
申请人： Leo Mathew , David C. Sing , Venkat Kolagunta
发明人： Leo Mathew , David C. Sing , Venkat Kolagunta
IPC分类号： H01L21/00
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/66818
摘要： A semiconductor device is formed by patterning a semiconductor layer to create a vertical active region and a horizontal active region, wherein the horizontal active region is adjacent the vertical active region. The semiconductor layer overlies an insulating layer. A spacer is formed adjacent the vertical active region and over a portion of the horizontal active region. At least a portion of the horizontal active region is oxidized to form an isolation region. The spacer is removed. A gate dielectric is formed over the vertical active region after removing the spacer. A gate electrode is formed over the gate dielectric. However, forming the spacer is optional.
摘要翻译：通过图案化半导体层以形成垂直有源区域和水平有源区域形成半导体器件，其中水平有源区域与垂直有源区域相邻。半导体层覆盖绝缘层。在垂直有源区域和水平有源区域的一部分附近形成间隔物。水平有源区域的至少一部分被氧化以形成隔离区域。移除间隔物。在去除间隔物之后，在垂直有源区上形成栅极电介质。在栅极电介质上形成栅电极。然而，形成间隔物是可选的。

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