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41. 发明授权

US06909146B1 Bonded wafer with metal silicidation 失效
标题翻译：带有金属硅化物的粘合晶片
公开(公告)号：US06909146B1
公开(公告)日：2005-06-21
申请号：US09316580
申请日：1999-05-21
申请人： Jack H. Linn , Robert K. Lowry , George V. Rouse , James F. Buller
发明人： Jack H. Linn , Robert K. Lowry , George V. Rouse , James F. Buller
IPC分类号： H01L21/20 , H01L21/316 , H01L21/762 , H01L27/01 , H01L27/12 , H01L29/00 , H01L31/0392
CPC分类号： H01L21/2007 , H01L21/31654 , H01L21/76264 , H01L21/76275 , H01L21/76283 , H01L21/76286
摘要： A silicon-on-insulator integrated circuit comprises a handle die, a substantially continuous and unbroken silicide layer over the handle die, and a substantially continuous and unbroken first dielectric layer overlying one side of the silicide layer. A device silicon layer having an upper surface overlies the first dielectric layer, and a second dielectric layer on the handle die underlies the opposite side of the silicide layer. Interconnected transistors are disposed in and at the upper surface of the device silicon layer. A silicon-on insulator integrated circuit includes a handle die and a first dielectric layer formed on the handle die. A substantially continuous and unbroken silicide layer is formed on the first dielectric layer; the silicide layer has a controlled resistance and provides a diffusion barrier to impurities. A substantially continuous and unbroken second dielectric layer is disposed between the silicide layer and a device silicon layer, and trenches extend through the device silicon layer and silicide layer and separate the device silicon layer into islands, each having an underlying continuous silicide area. Interconnected transistors are disposed in and at an upper surface of the device silicon layer. A bonded wafer integrated circuit comprised a handle die and a homogeneous silicide layer bonded to the handle die. A device layer is bonded to the silicide layer, and interconnected transistors are disposed in and at a surface of device layer.
摘要翻译：绝缘体上硅集成电路包括手柄芯片，位于手柄芯片上的基本上连续且不间断的硅化物层，以及覆盖在硅化物层的一侧上的基本上连续且不间断的第一介电层。具有上表面的器件硅层覆盖第一介电层，并且手柄模具上的第二介电层位于硅化物层的相对侧。互连晶体管设置在器件硅层的上表面和其上表面。硅上绝缘体集成电路包括手柄模和形成在手柄模上的第一电介质层。在第一电介质层上形成基本上连续且不间断的硅化物层; 硅化物层具有受控的电阻并且提供对杂质的扩散阻挡层。在硅化物层和器件硅层之间设置基本连续且不间断的第二电介质层，并且沟槽延伸穿过器件硅层和硅化物层，并将器件硅层分离成岛，每个具有下面的连续硅化物区域。互连晶体管设置在器件硅层的上表面和其上表面。键合晶片集成电路包括手柄模和结合到手柄模的均匀硅化物层。器件层与硅化物层结合，并且互连的晶体管设置在器件层的表面和表面。

42. 发明授权

US06794256B1 Method for asymmetric spacer formation 失效
标题翻译：非对称间隔物形成方法
公开(公告)号：US06794256B1
公开(公告)日：2004-09-21
申请号：US10633981
申请日：2003-08-04
申请人： Mark B. Fuselier , Edward E. Ehrichs , S. Doug Ray , Chad Weintraub , James F. Buller
发明人： Mark B. Fuselier , Edward E. Ehrichs , S. Doug Ray , Chad Weintraub , James F. Buller
IPC分类号： H01L21336
CPC分类号： H01L21/823468 , H01L21/823425 , H01L21/823864 , H01L29/66742 , H01L29/6678 , H01L29/78654 , H01L29/78657
摘要： A method for asymmetric spacer formation integratable into a manufacturing process for integrated circuit semiconductor devices is presented. The method comprises forming a gate structure over a substrate, and forming a sidewall layer overlying the gate structure and substrate, wherein the sidewall layer comprises a first portion overlying a first sidewall of the gate structure. A photoresist structure is formed adjacent to the first portion, and subjected to an ion beam. The photoresist structure serves to shield at least part of the first portion from the ion beam. During irradiation, the wafer is oriented such that a non-orthogonal tilt angle exists between a path of the ion beam and a surface of the first sidewall. Formation of asymmetric spacers is possible because radiation damage to unshielded sidewall portions permits subsequent etches to proceed at a faster rate.
摘要翻译：提出了可集成到集成电路半导体器件的制造工艺中的非对称间隔物形成方法。该方法包括在衬底上形成栅极结构，以及形成覆盖栅极结构和衬底的侧壁层，其中侧壁层包括覆盖栅极结构的第一侧壁的第一部分。光致抗蚀剂结构与第一部分相邻形成，并进行离子束。光致抗蚀剂结构用于将第一部分的至少一部分与离子束屏蔽。在照射期间，晶片被定向成使得在离子束的路径和第一侧壁的表面之间存在非正交倾斜角。不对称间隔物的形成是可能的，因为对非屏蔽侧壁部分的辐射损伤允许随后的蚀刻以更快的速率进行。

43. 发明授权

US06727534B1 Electrically programmed MOS transistor source/drain series resistance 有权
标题翻译：电子编程MOS晶体管源极/漏极串联电阻
公开(公告)号：US06727534B1
公开(公告)日：2004-04-27
申请号：US10022847
申请日：2001-12-20
申请人： James F. Buller , Qi Xiang , Derick J. Wristers
发明人： James F. Buller , Qi Xiang , Derick J. Wristers
IPC分类号： H01L2979
CPC分类号： H01L29/4983 , H01L29/42376 , H01L29/66484 , H01L29/6656
摘要： High-speed MOS transistors are provided by forming a conductive layer embedded in transistor gate sidewall spacers. The embedded conductive layer is electrically insulated from the gate electrode and the source/drain regions of the transistor. The embedded conductive layer is positioned over the source/drain extensions and causes charge to accumulate in the source/drain extensions lowering the series resistance of the source/drain regions.
摘要翻译：通过形成嵌入在晶体管栅极侧壁间隔物中的导电层来提供高速MOS晶体管。嵌入式导电层与晶体管的栅极电极和源极/漏极区域电绝缘。嵌入的导电层位于源极/漏极延伸部分上方，并使电荷累积在源极/漏极延伸部中，从而降低源极/漏极区域的串联电阻。

44. 发明授权

US06566696B1 Self-aligned VT implant 有权
标题翻译：自对准VT植入
公开(公告)号：US06566696B1
公开(公告)日：2003-05-20
申请号：US09907359
申请日：2001-07-17
申请人： Jon D. Cheek , Mark Michael , Derick J. Wristers , James F. Buller
发明人： Jon D. Cheek , Mark Michael , Derick J. Wristers , James F. Buller
IPC分类号： H01L2980
CPC分类号： H01L29/66583 , H01L29/105 , H01L29/66537 , H01L29/66545
摘要： Integrated circuits with transistors exhibiting improved junction capacitances and various methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a doped region in an active area of a substrate wherein the doped region has a first conductivity type and a first horizontal junction. A first source/drain region of the first conductivity type is formed in the active area with a second horizontal junction. A second source/drain region of the first conductivity type is formed in the active area with a third horizontal junction and a lateral separation from the first source/drain region that defines a channel region. The second and third horizontal junctions are positioned substantially at the first horizontal junction. The portion of the doped region positioned in the channel region is doped with an impurity of a second conductivity type that is opposite to the first conductivity type. Impurity grading across a source/drain-to-body junction is less abrupt, resulting in improved junction capacitance.
摘要翻译：提供了具有改善的结电容的晶体管的集成电路及其制造方法。一方面，提供一种制造方法，其包括在衬底的有源区中形成掺杂区域，其中所述掺杂区域具有第一导电类型和第一水平结。第一导电类型的第一源极/漏极区域形成在具有第二水平结的有源区域中。第一导电类型的第二源极/漏极区域在有源区域中形成有第三水平结和与限定沟道区域的第一源极/漏极区域的横向分离。第二和第三水平接头基本位于第一水平接头处。位于沟道区域中的掺杂区域的部分掺杂有与第一导电类型相反的第二导电类型的杂质。通过源极/漏极到体区结的杂质分级不太突然，导致改善的结电容。

45. 发明授权

US06506642B1 Removable spacer technique 有权
标题翻译：可拆卸间隔技术
公开(公告)号：US06506642B1
公开(公告)日：2003-01-14
申请号：US10020931
申请日：2001-12-19
申请人： Scott D. Luning , Jon D. Cheek , Daniel Kadosh , James F. Buller , David E. Brown
发明人： Scott D. Luning , Jon D. Cheek , Daniel Kadosh , James F. Buller , David E. Brown
IPC分类号： H01L218238
CPC分类号： H01L29/6653 , H01L21/823814 , H01L21/823864 , H01L29/6656
摘要： Submicron-dimensioned MOS and/or CMOS transistors are fabricated utilizing a simplified removable sidewall spacer technique, enabling effective tailoring of individual transistors to optimize their respective functionality. Embodiments include forming a first sidewall spacer having a first thickness on the side surfaces of a plurality of gate electrodes of transistors, selectively removing the first sidewall spacers from the gate electrodes of certain transistors, and then depositing second sidewall spacers on remaining first sidewall spacers and on the side surfaces of the gate electrodes from which the first sidewall spacers have been removed. Embodiments enable separately tailoring n- and p-MOS transistors as well as individual n- or p-MOS transistors having different functionality, e.g., different drive current and voltage leakage requirements.
摘要翻译：亚微米尺寸的MOS和/或CMOS晶体管使用简化的可移除侧壁间隔物技术制造，使得能够有效地定制各个晶体管以优化它们各自的功能。实施例包括在晶体管的多个栅极电极的侧表面上形成具有第一厚度的第一侧壁间隔物，从某些晶体管的栅电极选择性地去除第一侧壁间隔物，然后在剩余的第一侧壁间隔物上沉积第二侧壁间隔物，在栅电极的已经被去除了第一侧壁间隔物的侧表面上。实施例能够单独定制n型和p型MOS晶体管以及具有不同功能的单独n型或p型MOS晶体管，例如不同的驱动电流和电压泄漏要求。

46. 发明授权

US5728624A Bonded wafer processing 失效
公开(公告)号：US5728624A
公开(公告)日：1998-03-17
申请号：US573551
申请日：1995-12-15
申请人： Jack H. Linn , Robert K. Lowry , Geroge V. Rouse , James F. Buller , William Herman Speece
发明人： Jack H. Linn , Robert K. Lowry , Geroge V. Rouse , James F. Buller , William Herman Speece
IPC分类号： H01L21/20 , H01L21/762 , H01L21/76
CPC分类号： H01L21/2007 , H01L21/76264 , H01L21/76275 , H01L21/76283 , H01L21/76286 , Y10S148/012 , Y10S438/92
摘要： Low temperature wafer bonding using a silicon-oxidizing bonding liquid permits introduction of radiation hardening dopants and electrically active dopants as constituents of the bonding liquid. Oxidizers such as nitric acid may be used in the bonding liquid. Dielectric layers on the device wafer and the handle wafer may be used when additional silicon is provided for the oxidative bonding. Integrated circuits fabricated from such bonded wafers may have buried layers and radiation hardening with device silicon too thick for implantation.

47. 发明授权

US5362667A Bonded wafer processing 失效
标题翻译：粘合晶片加工
公开(公告)号：US5362667A
公开(公告)日：1994-11-08
申请号：US921197
申请日：1992-07-28
申请人： Jack H. Linn , Robert K. Lowry , George V. Rouse , James F. Buller , William H. Speece
发明人： Jack H. Linn , Robert K. Lowry , George V. Rouse , James F. Buller , William H. Speece
IPC分类号： H01L21/20 , H01L21/762 , H01L21/265
CPC分类号： H01L21/2007 , H01L21/76264 , H01L21/76275 , H01L21/76283 , H01L21/76286 , Y10S148/012 , Y10S438/92
摘要： Low temperature wafer bonding using a silicon-oxidizing bonding liquid permits introduction of radiation hardening dopants and electrically active dopants as constituents of the bonding liquid. Oxidizers such as nitric acid may be used in the bonding liquid. Dielectric layers on the device wafer and the handle wafer may be used when additional silicon is provided for the oxidative bonding. Integrated circuits fabricated from such bonded wafers may have buried layers and radiation hardening with device silicon too thick for implantation.
摘要翻译：使用硅氧化粘合液的低温晶片接合允许引入辐射固化掺杂剂和电活性掺杂剂作为粘合液的成分。可以在粘合液中使用硝酸等氧化剂。当为氧化粘合提供额外的硅时，可以使用器件晶片和处理晶片上的介电层。由这种接合晶片制造的集成电路可能具有掩埋层和放射硬化，器件硅太厚以用于植入。

48. 发明授权

US08377781B2 Transistor with asymmetric silicon germanium source region 有权
标题翻译：晶体管与不对称硅锗源区
公开(公告)号：US08377781B2
公开(公告)日：2013-02-19
申请号：US13230083
申请日：2011-09-12
申请人： Jian Chen , James F. Buller , Akif Sultan
发明人： Jian Chen , James F. Buller , Akif Sultan
IPC分类号： H01L21/336
CPC分类号： H01L29/78618 , H01L29/665 , H01L29/66636 , H01L29/66659 , H01L29/66772 , H01L29/7848
摘要： The present invention is directed to a transistor with an asymmetric silicon germanium source region, and various methods of making same. In one illustrative embodiment, the transistor includes a gate electrode formed above a semiconducting substrate comprised of silicon, a doped source region comprising a region of epitaxially grown silicon that is doped with germanium formed in the semiconducting substrate and a doped drain region formed in the semiconducting substrate.
摘要翻译：本发明涉及具有不对称硅锗源区的晶体管及其制造方法。在一个说明性实施例中，晶体管包括形成在由硅构成的半导体衬底之上的栅电极，掺杂源区包括在半导体衬底中形成的锗掺杂的外延生长硅的区域和形成在半导体衬底中的掺杂漏极区基质。

49. 发明授权

US08357584B2 Metal capacitor design for improved reliability and good electrical connection 有权
标题翻译：金属电容设计，提高可靠性和良好的电气连接
公开(公告)号：US08357584B2
公开(公告)日：2013-01-22
申请号：US12615796
申请日：2009-11-10
申请人： Jianhong Zhu , James F. Buller
发明人： Jianhong Zhu , James F. Buller
IPC分类号： H01L21/20
CPC分类号： H01L28/40 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A metal capacitor is formed with good conductivity for both nodes of the capacitor and improved reliability. An embodiment includes a first layer of alternating first and second metal lines, a second layer of alternating third and fourth metal lines, a dielectric layer between the first and second layers, and vias in the dielectric layer connecting the first and second metal lines with the third and fourth metal lines, respectively, wherein each metal line comprises alternating first segments having a first width and second segments having a second width, the first width being greater than the second width, each first segment lying adjacent to a second segment of an adjacent metal line, and only first segments of the metal lines overlapping the vias. The design enables the spacing between metal lines to be maintained, the spacing between via to metal to be increased, and via connection to be maintained for both nets, thereby improving the conductivity and reliability of the capacitor and maintaining capacitance density.
摘要翻译：形成对电容器的两个节点具有良好导电性的金属电容器，并提高可靠性。一个实施例包括交替的第一和第二金属线的第一层，交替的第三和第四金属线的第二层，第一和第二层之间的介电层，以及介电层中的通孔，将第一和第二金属线与第三和第四金属线，其中每个金属线包括具有第一宽度的交替的第一段和具有第二宽度的第二段，第一宽度大于第二宽度，每个第一段邻近相邻的第二段的第二段金属线，并且仅金属线的第一段与通孔重叠。该设计使得能够保持金属线之间的间距，通孔与金属之间的间隔增加，并且通过两个网络的连接来保持，从而提高电容器的导电性和可靠性并保持电容密度。

50. 发明授权

US07582493B2 Distinguishing between dopant and line width variation components 有权
标题翻译：区分掺杂剂和线宽变化组分
公开(公告)号：US07582493B2
公开(公告)日：2009-09-01
申请号：US11538872
申请日：2006-10-05
申请人： Akif Sultan , James F. Buller , David Donggang Wu
发明人： Akif Sultan , James F. Buller , David Donggang Wu
IPC分类号： H01L21/66
CPC分类号： H01L22/12 , H01L22/14
摘要： A test structure includes first and second pluralities of transistors. The first plurality of transistors includes gate electrodes of a first length. The second plurality of transistors includes gate electrodes of a second length different than the first length. A channel area of the transistors in the first plurality is substantially equal to a channel area of the transistors in the second plurality. A method for using the test structure includes measuring a performance metric of the first and second pluralities of transistors. Variation in the performance metric associated with the first plurality of transistors is compared to variation in the performance metric associated with the second plurality of transistors to identify a random length variation component associated with the first plurality of transistors.
摘要翻译：测试结构包括第一和第二多个晶体管。第一多个晶体管包括第一长度的栅电极。第二多个晶体管包括与第一长度不同的第二长度的栅电极。第一多个晶体管的沟道面积基本上等于第二多个晶体管的沟道面积。使用该测试结构的方法包括测量第一和第二多个晶体管的性能度量。将与第一多个晶体管相关联的性能度量的变化与与第二多个晶体管相关联的性能度量的变化进行比较，以识别与第一多个晶体管相关联的随机长度变化分量。

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