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1. 发明授权

US06909146B1 Bonded wafer with metal silicidation 失效
标题翻译：带有金属硅化物的粘合晶片
公开(公告)号：US06909146B1
公开(公告)日：2005-06-21
申请号：US09316580
申请日：1999-05-21
申请人： Jack H. Linn , Robert K. Lowry , George V. Rouse , James F. Buller
发明人： Jack H. Linn , Robert K. Lowry , George V. Rouse , James F. Buller
IPC分类号： H01L21/20 , H01L21/316 , H01L21/762 , H01L27/01 , H01L27/12 , H01L29/00 , H01L31/0392
CPC分类号： H01L21/2007 , H01L21/31654 , H01L21/76264 , H01L21/76275 , H01L21/76283 , H01L21/76286
摘要： A silicon-on-insulator integrated circuit comprises a handle die, a substantially continuous and unbroken silicide layer over the handle die, and a substantially continuous and unbroken first dielectric layer overlying one side of the silicide layer. A device silicon layer having an upper surface overlies the first dielectric layer, and a second dielectric layer on the handle die underlies the opposite side of the silicide layer. Interconnected transistors are disposed in and at the upper surface of the device silicon layer. A silicon-on insulator integrated circuit includes a handle die and a first dielectric layer formed on the handle die. A substantially continuous and unbroken silicide layer is formed on the first dielectric layer; the silicide layer has a controlled resistance and provides a diffusion barrier to impurities. A substantially continuous and unbroken second dielectric layer is disposed between the silicide layer and a device silicon layer, and trenches extend through the device silicon layer and silicide layer and separate the device silicon layer into islands, each having an underlying continuous silicide area. Interconnected transistors are disposed in and at an upper surface of the device silicon layer. A bonded wafer integrated circuit comprised a handle die and a homogeneous silicide layer bonded to the handle die. A device layer is bonded to the silicide layer, and interconnected transistors are disposed in and at a surface of device layer.
摘要翻译：绝缘体上硅集成电路包括手柄芯片，位于手柄芯片上的基本上连续且不间断的硅化物层，以及覆盖在硅化物层的一侧上的基本上连续且不间断的第一介电层。具有上表面的器件硅层覆盖第一介电层，并且手柄模具上的第二介电层位于硅化物层的相对侧。互连晶体管设置在器件硅层的上表面和其上表面。硅上绝缘体集成电路包括手柄模和形成在手柄模上的第一电介质层。在第一电介质层上形成基本上连续且不间断的硅化物层; 硅化物层具有受控的电阻并且提供对杂质的扩散阻挡层。在硅化物层和器件硅层之间设置基本连续且不间断的第二电介质层，并且沟槽延伸穿过器件硅层和硅化物层，并将器件硅层分离成岛，每个具有下面的连续硅化物区域。互连晶体管设置在器件硅层的上表面和其上表面。键合晶片集成电路包括手柄模和结合到手柄模的均匀硅化物层。器件层与硅化物层结合，并且互连的晶体管设置在器件层的表面和表面。

2. 发明授权

US5362667A Bonded wafer processing 失效
标题翻译：粘合晶片加工
公开(公告)号：US5362667A
公开(公告)日：1994-11-08
申请号：US921197
申请日：1992-07-28
申请人： Jack H. Linn , Robert K. Lowry , George V. Rouse , James F. Buller , William H. Speece
发明人： Jack H. Linn , Robert K. Lowry , George V. Rouse , James F. Buller , William H. Speece
IPC分类号： H01L21/20 , H01L21/762 , H01L21/265
CPC分类号： H01L21/2007 , H01L21/76264 , H01L21/76275 , H01L21/76283 , H01L21/76286 , Y10S148/012 , Y10S438/92
摘要： Low temperature wafer bonding using a silicon-oxidizing bonding liquid permits introduction of radiation hardening dopants and electrically active dopants as constituents of the bonding liquid. Oxidizers such as nitric acid may be used in the bonding liquid. Dielectric layers on the device wafer and the handle wafer may be used when additional silicon is provided for the oxidative bonding. Integrated circuits fabricated from such bonded wafers may have buried layers and radiation hardening with device silicon too thick for implantation.
摘要翻译：使用硅氧化粘合液的低温晶片接合允许引入辐射固化掺杂剂和电活性掺杂剂作为粘合液的成分。可以在粘合液中使用硝酸等氧化剂。当为氧化粘合提供额外的硅时，可以使用器件晶片和处理晶片上的介电层。由这种接合晶片制造的集成电路可能具有掩埋层和放射硬化，器件硅太厚以用于植入。

3. 发明授权

US5517047A Bonded wafer processing 失效
标题翻译：粘合晶片加工
公开(公告)号：US5517047A
公开(公告)日：1996-05-14
申请号：US287773
申请日：1994-08-09
申请人： Jack H. Linn , Robert K. Lowry , George V. Rouse , James F. Buller , William H. Speece
发明人： Jack H. Linn , Robert K. Lowry , George V. Rouse , James F. Buller , William H. Speece
IPC分类号： H01L21/20 , H01L21/762 , H01L27/01
CPC分类号： H01L21/2007 , H01L21/76264 , H01L21/76275 , H01L21/76283 , H01L21/76286 , Y10S148/012 , Y10S438/92
摘要： Low temperature wafer bonding using a silicon-oxidizing bonding liquid permits introduction of radiation hardening dopants and electrically active dopants as constituents of the bonding liquid. Oxidizers such as nitric acid may be used in the bonding liquid. Dielectric layers on the device wafer and the handle wafer may be used when additional silicon is provided for the oxidative bonding. Integrated circuits fabricated from such bonded wafers may have buried layers and radiation hardening with device silicon too thick for implantation.
摘要翻译：使用硅氧化粘合液的低温晶片接合允许引入辐射固化掺杂剂和电活性掺杂剂作为粘合液的成分。可以在粘合液中使用硝酸等氧化剂。当为氧化粘合提供额外的硅时，可以使用器件晶片和处理晶片上的介电层。由这种接合晶片制造的集成电路可能具有掩埋层和放射硬化，器件硅太厚以用于植入。

4. 发明授权

US5849627A Bonded wafer processing with oxidative bonding 失效
标题翻译：具有氧化粘合的粘结晶片加工
公开(公告)号：US5849627A
公开(公告)日：1998-12-15
申请号：US430312
申请日：1995-04-28
申请人： Jack H. Linn , Robert K. Lowry , George V. Rouse , James F. Buller
发明人： Jack H. Linn , Robert K. Lowry , George V. Rouse , James F. Buller
IPC分类号： H01L21/20 , H01L21/316 , H01L21/762 , H01L21/30
CPC分类号： H01L21/2007 , H01L21/31654 , H01L21/76264 , H01L21/76275 , H01L21/76283 , H01L21/76286 , Y10S148/012
摘要： Low temperature wafer bonding using a chemically reacting material between wafers to form a bonded zone to bond two wafers together. Examples include silicon wafers with a silicon-oxidizing bonding liquid which also permits introduction of radiation hardening dopants and electrically active dopants as constituents of the bonding liquid. Silicon wafers also may use solid reactants which include deposited layers of metal and polysilicon to form silicide bonded zones. Oxidizers such as nitric acid may be used in the bonding liquid, and a bonding liquid may be used in conjunction with a solid bonding reactant. Dielectric layers on silicon wafers may be used when additional silicon is provided for the bonding reactions. Integrated circuits fabricated from such bonded wafers may have buried layers and radiation hardening and buried resistors.
摘要翻译：使用晶片之间的化学反应材料进行低温晶片接合，以形成将两个晶片结合在一起的结合区域。实例包括具有硅氧化粘合液体的硅晶片，其也允许引入辐射固化掺杂剂和作为粘合液体的组分的电活性掺杂剂。硅晶片还可以使用固体反应物，其包括金属和多晶硅的沉积层以形成硅化物结合区。可以在接合液中使用硝酸等氧化剂，结合液可以与固体键合反应物结合使用。当为粘合反应提供额外的硅时，可以使用硅晶片上的介电层。由这种接合晶片制造的集成电路可以具有掩埋层和辐射硬化和掩埋电阻。

5. 发明授权

US5569620A Bonded wafer processing with metal silicidation 失效
标题翻译：用金属硅化物粘结晶片加工
公开(公告)号：US5569620A
公开(公告)日：1996-10-29
申请号：US351933
申请日：1994-12-08
申请人： Jack H. Linn , Robert K. Lowry , George V. Rouse , James F. Buller
发明人： Jack H. Linn , Robert K. Lowry , George V. Rouse , James F. Buller
IPC分类号： H01L21/20 , H01L21/762 , H01L21/30 , H01L21/46
CPC分类号： H01L21/2007 , H01L21/76264 , H01L21/76275 , H01L21/76283 , H01L21/76286 , Y10S148/012 , Y10S148/147
摘要： Low temperature silicon-on-insulator wafer bonding using a silicide bond formation reaction. Dielectric isolation with silicon dioxide, diamond, silicon-nitride, and so forth yields buried resistors under trench isolated silicon islands. Buried dielectrics can be thermally susceptible films like diamond due to the low temperature of the bonding silicidation reaction. Bonding silicides also provide thermal dissipating layer between a buried diamond layer and a handle wafer for good overall thermal conductivity. Bonding silicides also act as diffusion barriers.
摘要翻译：使用硅化物键形成反应的低温硅绝缘体晶片键合。与二氧化硅，金刚石，氮化硅等的介质隔离在沟槽隔离硅岛下产生埋入式电阻。由于接合硅化反应的低温，埋入的电介质可以是诸如金刚石的热敏膜。结合硅化物还在埋入金刚石层和处理晶片之间提供散热层，以获得良好的整体导热性。粘结硅化物也充当扩散阻挡层。

6. 发明授权

US5387555A Bonded wafer processing with metal silicidation 失效
标题翻译：用金属硅化物粘结晶片加工
公开(公告)号：US5387555A
公开(公告)日：1995-02-07
申请号：US939786
申请日：1992-09-03
申请人： Jack H. Linn , Robert K. Lowry , George V. Rouse , James F. Buller
发明人： Jack H. Linn , Robert K. Lowry , George V. Rouse , James F. Buller
IPC分类号： H01L21/20 , H01L21/762 , H01L21/30 , H01L21/46
CPC分类号： H01L21/2007 , H01L21/76264 , H01L21/76275 , H01L21/76283 , H01L21/76286 , Y10S148/012 , Y10S148/147
摘要： Low temperature silicon-on-insulator wafer bonding using a silicide bond formation reaction. Dielectric isolation with silicon dioxide, diamond, silicon nitride, and so forth yields buried resistors under trench isolated silicon islands. Buried dielectrics can be thermally susceptible films like diamond due to the low temperature of the bonding silicidation reaction. Bonding silicides also provide thermal dissipating layer between a buried diamond layer and a handle wafer for good overall thermal conductivity. Bonding silicides also act as diffusion barriers. The silicide bonding takes place in the presense of a liquid oxidizer such as aqueous solution of HNO.sub.3 and H.sub.2 O.sub.2.
摘要翻译：使用硅化物键形成反应的低温硅绝缘体晶片键合。使用二氧化硅，金刚石，氮化硅等进行介质隔离，在沟槽隔离硅岛下产生掩埋电阻。由于接合硅化反应的低温，埋入的电介质可以是诸如金刚石的热敏膜。结合硅化物还在埋入金刚石层和处理晶片之间提供散热层，以获得良好的整体导热性。粘结硅化物也充当扩散阻挡层。硅化物结合发生在液体氧化剂如HNO 3和H 2 O 2的水溶液的存在之中。

7. 发明授权

US06455379B2 Power trench transistor device source region formation using silicon spacer 失效
标题翻译：使用硅衬垫的功率沟槽晶体管器件源区域形成
公开(公告)号：US06455379B2
公开(公告)日：2002-09-24
申请号：US09799845
申请日：2001-03-06
申请人： Linda S. Brush , Jun Zeng , John J. Hackenberg , Jack H. Linn , George V. Rouse
发明人： Linda S. Brush , Jun Zeng , John J. Hackenberg , Jack H. Linn , George V. Rouse
IPC分类号： H01L21336
CPC分类号： H01L29/7802 , H01L29/41766 , H01L29/66348 , H01L29/66378 , H01L29/66545 , H01L29/7397 , H01L29/749 , H01L29/7813
摘要： A power trench MOS-gated transistor is constructed with a buried gate to source dielectric inside a gate trench region. In the innovative device, a thick oxide (grown or deposited) is used to define the height of the trench walls. A body region is initially formed by selective epitaxial growth and etch back. Source regions are formed also by selective epitaxial growth. The body is finally formed by selective epitaxial growth and etch back. The oxide is removed from the trench, the trench walls are oxidized to form a gate oxide, and doped polysilicon fills the trench to form a gate. By the formation of the source region using the spacer etch, this process simplifies the fabrication of power trench gated devices, and provides for increased contact surface area without increasing device size.
摘要翻译：功率沟槽MOS门控晶体管由栅极沟槽区域内的栅极源极构成。在创新的设备中，使用厚的氧化物（生长或沉积）来限定沟槽壁的高度。最初通过选择性外延生长和回蚀而形成体区。源区也通过选择性外延生长形成。身体最终通过选择性外延生长和回蚀而形成。从沟槽去除氧化物，沟槽壁被氧化以形成栅极氧化物，并且掺杂多晶硅填充沟槽以形成栅极。通过使用间隔物蚀刻形成源极区域，该工艺简化了功率沟槽门控器件的制造，并且提供了增加的接触表面积而不增加器件尺寸。

8. 发明授权

US06825532B2 Bonded substrate for an integrated circuit containing a planar intrinsic gettering zone 失效
公开(公告)号：US06825532B2
公开(公告)日：2004-11-30
申请号：US09846795
申请日：2001-05-01
申请人： Jack H. Linn , William H. Speece , Michael G. Shlepr , George V. Rouse
发明人： Jack H. Linn , William H. Speece , Michael G. Shlepr , George V. Rouse
IPC分类号： H01L2701
CPC分类号： H01L21/3226 , H01L21/2007 , H01L21/76251 , Y10S438/977
摘要： A bonded semiconductor-on-insulator substrate for an integrated circuit. The bonded semiconductor-on-insulator substrate includes a wafer, a handle wafer and an insulating bond layer. The wafer has a first layer of monocrystalline semiconductor material adjacent a first surface of the wafer. The wafer also has a second layer of undamaged by implantation monocrystalline semiconductor material adjacent a second surface of the wafer. The wafer further has a substantially planar intrinsic gettering zone of substantially pure semiconductor material and active gettering sites positioned between the first and second layers formed by implanting ions of the semiconductor material through the first layer of monocrystalline semiconductor material. The insulating bond layer bonds the handle wafer to the first surface of the wafer.

9. 发明授权

US06246090B1 Power trench transistor device source region formation using silicon spacer 有权
公开(公告)号：US06246090B1
公开(公告)日：2001-06-12
申请号：US09525182
申请日：2000-03-14
申请人： Linda S. Brush , Jun Zeng , John J. Hackenberg , Jack H. Linn , George V. Rouse
发明人： Linda S. Brush , Jun Zeng , John J. Hackenberg , Jack H. Linn , George V. Rouse
IPC分类号： H01L2976
CPC分类号： H01L29/7802 , H01L29/41766 , H01L29/66348 , H01L29/66378 , H01L29/66545 , H01L29/7397 , H01L29/749 , H01L29/7813
摘要： A power trench MOS-gated transistor is constructed with a buried gate to source dielectric inside a gate trench region. In the innovative device, a thick oxide (grown or deposited) is used to define the height of the trench walls. A body region is initially formed by selective epitaxial growth and etch back. Source regions are formed also by selective epitaxial growth. The body is finally formed by selective epitaxial growth and etch back. The oxide is removed from the trench, the trench walls are oxidized to form a gate oxide, and doped polysilicon fills the trench to form a gate. By the formation of the source region using the spacer etch, this process simplifies the fabrication of power trench gated devices, and provides for increased contact surface area without increasing device size.

10. 发明授权

US5932022A SC-2 based pre-thermal treatment wafer cleaning process 失效
标题翻译：基于SC-2的预热处理晶片清洗工艺
公开(公告)号：US5932022A
公开(公告)日：1999-08-03
申请号：US64029
申请日：1998-04-21
申请人： Jack H. Linn , George V. Rouse , Sana Rafie , Roberta R. Nolan-Lobmeyer , Diana Lynn Hackenberg , Steven T. Slasor , Timothy A. Valade
发明人： Jack H. Linn , George V. Rouse , Sana Rafie , Roberta R. Nolan-Lobmeyer , Diana Lynn Hackenberg , Steven T. Slasor , Timothy A. Valade
IPC分类号： H01L21/304 , H01L21/306 , H01L21/316 , B08B3/12 , C23G1/02 , H01L21/02
CPC分类号： H01L21/02052 , H01L21/02238 , H01L21/02307 , H01L21/31662
摘要： Pre heat-treatment processing of a silicon wafer to grow a hydrophilic oxide layer includes an initial step of contacting the wafer with a pre-clean SC-1 bath, thereby producing a silicon wafer surface that is highly particle free. After a deionized water rinse, the wafer is scoured with an aqueous solution containing hydrofluoric acid and hydrochloric acid to remove metallic-containing oxide from the wafer surface. In order to grow a hydrophilic oxide layer, an SC-2 bath (containing hydrogen peroxide and a dilute concentration of metal-scouring HCl) is used. The resulting hydrophilic silicon oxide layer grown on the surface of the silicon wafer using the combined SC-1.fwdarw.HF/HCL.fwdarw.SC-2 wafer cleaning process has a metal concentration no greater than 1.times.10.sup.9. The diffusion length of minority carriers is increased from a range on the order of 500-600 microns to a range on the order of 800-900 microns.
摘要翻译：硅晶片的预热处理处理以生长亲水氧化物层包括使晶片与预清洁SC-1浴接触的初始步骤，从而产生高度无颗粒的硅晶片表面。去离子水冲洗后，用含有氢氟酸和盐酸的水溶液洗涤晶片，以从晶片表面去除含金属的氧化物。为了生长亲水氧化物层，使用SC-2浴（含有过氧化氢和稀释浓度的金属洗涤HCl）。使用组合的SC-1-> HF / HCL-> SC-2晶片清洁工艺在硅晶片的表面上生长的所得亲水性氧化硅层的金属浓度不大于1×109。少数载体的扩散长度从500-600微米的范围增加到约800-900微米的范围。

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