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41. 发明授权

US07463515B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07463515B2
公开(公告)日：2008-12-09
申请号：US11773280
申请日：2007-07-03
申请人： Masanobu Shirakawa , Naoya Tokiwa
发明人： Masanobu Shirakawa , Naoya Tokiwa
IPC分类号： G11C16/26
CPC分类号： G11C8/08 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C29/835
摘要： A semiconductor memory device includes: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; a row decoder configured to select a memory cell in the memory cell array, the row decoder including a flag latch, in which a bad block flag is set for a bad block in the memory cell array; a sense amplifier configured to sense data of a selected memory cell in the memory cell array; and an output circuit configured to output read data in the sense amplifier, the output circuit including an output data fixing circuit configured to fix an output data at a logic level in accordance with the bad block flag.
摘要翻译：半导体存储器件包括：具有布置在其中的电可重写和非易失性存储单元的存储单元阵列; 行解码器，其被配置为选择存储单元阵列中的存储单元，所述行解码器包括标志锁存器，其中对所述存储单元阵列中的坏块设置坏块标志; 感测放大器，被配置为感测所述存储器单元阵列中的选定存储单元的数据; 以及输出电路，被配置为在所述读出放大器中输出读取数据，所述输出电路包括输出数据固定电路，其被配置为根据所述坏块标志将输出数据固定在逻辑电平。

42. 发明授权

US07369457B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07369457B2
公开(公告)日：2008-05-06
申请号：US11767025
申请日：2007-06-22
申请人： Naoya Tokiwa
发明人： Naoya Tokiwa
IPC分类号： G11C8/00 , G11C8/18
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/32
摘要： A semiconductor memory device includes: a memory cell array, in which electrically rewritable and non-volatile memory cells are arranged; a sense amplifier circuit configured to be coupled to the memory cell array; a data transfer circuit disposed between the sense amplifier circuit and data input/output ports; a control signal generation circuit configured to generate a plurality of control signals based on a reference clock signal externally supplied, the control signals serving for controlling data input and output of the sense amplifier circuit and data transferring timing in the data transfer circuit; and an internal clock signal generation circuit configured to generate an internal clock signal based on the reference clock signal for serving as the basis of the control signals, the internal clock signal having the same clock cycle as the reference clock signal and a constant duty ratio without regard to the duty ratio of the reference clock signal.
摘要翻译：半导体存储器件包括：存储单元阵列，其中布置有电可重写和非易失性存储单元; 被配置为耦合到所述存储单元阵列的读出放大器电路; 设置在读出放大器电路和数据输入/输出端口之间的数据传输电路; 控制信号生成电路，被配置为基于外部提供的参考时钟信号生成多个控制信号，所述控制信号用于控制读出放大器电路的数据输入和输出以及数据传送电路中的数据传送定时; 以及内部时钟信号生成电路，被配置为基于用于作为控制信号的基础的参考时钟信号产生内部时钟信号，内部时钟信号具有与参考时钟信号相同的时钟周期和不具有恒定占空比的内部时钟信号关于参考时钟信号的占空比。

43. 发明申请

US20070297236A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20070297236A1
公开(公告)日：2007-12-27
申请号：US11754531
申请日：2007-05-29
申请人： Naoya Tokiwa
发明人： Naoya Tokiwa
IPC分类号： G11C11/34
CPC分类号： G11C16/3436 , G11C16/0483
摘要： A semiconductor memory device includes: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; a data storage circuit configured to store data simultaneously read from or written into the memory cell array, the data constituting a collective processing unit; and a data state judgment circuit configured to sequentially judge the data states of multiple divided areas, which are obtained by dividing the collective processing unit.
摘要翻译：半导体存储器件包括：具有布置在其中的电可重写和非易失性存储单元的存储单元阵列; 数据存储电路，被配置为存储同时从存储单元阵列读取或写入存储单元阵列的数据，所述数据构成集合处理单元; 以及数据状态判断电路，被配置为顺序地判断通过分割集体处理单元获得的多个分割区域的数据状态。

44. 发明申请

US20070147144A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
标题翻译：半导体集成电路设备
公开(公告)号：US20070147144A1
公开(公告)日：2007-06-28
申请号：US11616112
申请日：2006-12-26
申请人： Naoya Tokiwa
发明人： Naoya Tokiwa
IPC分类号： G11C16/06 , G11C11/34 , G11C29/00 , G11C7/00
CPC分类号： G11C29/76 , G11C16/0483 , G11C29/82
摘要： A semiconductor integrated circuit device includes a memory cell array having a plurality of blocks, a storage unit, a block replacement information register group, and a bad block flag register group. The storage unit includes a block replacement information registration area with which it is possible to register block replacement information, and a bad block information registration area with which it is possible to register bad block information. The block replacement information register group is set in accordance with the block replacement information read out of the storage unit during a boot sequence, and the bad block flag register group is set in accordance with both of the block replacement information and the bad block information read out of the storage unit during the boot sequence.
摘要翻译：半导体集成电路装置包括具有多个块的存储单元阵列，存储单元，块替换信息寄存器组和坏块标志寄存器组。存储单元包括可以注册块替换信息的块替换信息登记区域和可以注册坏块信息的坏块信息登记区域。根据在引导顺序期间从存储单元读出的块替换信息来设置块替换信息寄存器组，并且根据读取的块替换信息和坏块信息两者来设置坏块标志寄存器组在引导顺序期间从存储单元出来。

45. 发明授权

US08582369B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08582369B2
公开(公告)日：2013-11-12
申请号：US13357241
申请日：2012-01-24
申请人： Yasushi Nagadomi , Naoya Tokiwa
发明人： Yasushi Nagadomi , Naoya Tokiwa
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C16/3459 , G11C16/0483 , G11C16/10 , G11C16/3454
摘要： In writing, a first write operation to a first memory cell is executed; and a second write operation for providing a first threshold-voltage distribution to a second memory cell adjacent to the first one, is executed. The first threshold voltage distribution is a lowest threshold-voltage distribution among the positive threshold voltage distributions. It is verified whether a desired threshold voltage distribution has been obtained in the first memory cell or not (first write verify operation), moreover, it is verified whether a first threshold voltage distribution or a threshold voltage distribution having a voltage level larger than the first threshold-voltage distribution has been obtained in the second memory cell or not (second write verify operation). A control circuit outputs results of the first write verify operation and the second write verify operation.
摘要翻译：在写入时，执行对第一存储单元的第一写入操作; 并且执行用于向与第一阈值电压分布相邻的第二存储单元提供第一阈值电压分布的第二写入操作。第一阈值电压分布是正阈值电压分布中的最低阈值电压分布。验证在第一存储器单元中是否已经获得期望的阈值电压分布（第一写入验证操作），此外，验证第一阈值电压分布或具有大于第一存储器单元的电压电平的阈值电压分布在第二存储器单元中已经获得阈值电压分布（第二写入验证操作）。控制电路输出第一写入验证操作和第二写入验证操作的结果。

46. 发明授权

US08289800B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08289800B2
公开(公告)日：2012-10-16
申请号：US12693824
申请日：2010-01-26
申请人： Takuya Futatsuyama , Naoya Tokiwa
发明人： Takuya Futatsuyama , Naoya Tokiwa
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C16/30
摘要： A nonvolatile semiconductor memory device has an internal step-down power generation circuit and a memory circuit. The internal step-down power generation circuit generates a first internal power supply voltage from an external power supply voltage in an active state, and generates a second internal power supply voltage different from the first internal power supply voltage from the external power supply voltage in a standby state. The memory circuit includes a cell array containing a nonvolatile memory cell and a sense amplifier detecting data read from the cell array. The sense amplifier is supplied with a voltage generated by the internal step-down power generation circuit as an internal power supply voltage.
摘要翻译：非易失性半导体存储器件具有内部降压发电电路和存储电路。内部降压发电电路从活动状态的外部电源电压产生第一内部电源电压，并且从外部电源电压生成与第一内部电源电压不同的第二内部电源电压待机状态。存储电路包括一个包含非易失性存储单元的单元阵列和一个检测从该单元阵列读出的数据的读出放大器。感测放大器被提供有由内部降压发电电路产生的电压作为内部电源电压。

47. 发明授权

US08117508B2 Non-volatile memory device and programming method thereof 有权
标题翻译：非易失性存储器件及其编程方法
公开(公告)号：US08117508B2
公开(公告)日：2012-02-14
申请号：US12650006
申请日：2009-12-30
申请人： Naoya Tokiwa
发明人： Naoya Tokiwa
IPC分类号： G06F11/00
CPC分类号： G11C13/0007 , G11C13/003 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0057 , G11C2013/0073 , G11C2029/0411 , G11C2213/71 , G11C2213/72 , G11C2213/76
摘要： A non-volatile memory device including: a memory cell array storing an electrically rewritable resistance value as data in a non-volatile manner; a first cache circuit configured to hold program data to be programmed in the cell array; a second cache circuit configured to hold preprogrammed data read from an area of the cell array; and a judging circuit configured to compare and check the program data with the preprogrammed data, and judge whether there are one or more disagreement bits therebetween or not.
摘要翻译：一种非易失性存储器件，包括：以非易失性方式存储作为数据的电可重写电阻值的存储单元阵列; 第一高速缓存电路，被配置为保存要在所述单元阵列中编程的程序数据; 第二高速缓存电路，被配置为保持从所述单元阵列的区域读取的预编程数据; 以及判断电路，被配置为将程序数据与预编程数据进行比较和检查，并判断其间是否存在一个或多个不一致的位。

48. 发明授权

US07965552B2 Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US07965552B2
公开(公告)日：2011-06-21
申请号：US12343990
申请日：2008-12-24
申请人： Masanobu Shirakawa , Naoya Tokiwa
发明人： Masanobu Shirakawa , Naoya Tokiwa
IPC分类号： G11C16/04 , G11C8/10 , G11C5/02 , G11C29/00
CPC分类号： G11C16/20 , G11C16/0483 , G11C29/82
摘要： A non-volatile semiconductor memory device includes: a memory cell array; a bad block position data register area defined in the memory cell array to store bad block position data; an address decoder circuit configured to select a block in the cell array; and bad block flag latches disposed in the address decoder circuit, bad block flags being set in the bad block flag latches in accordance with the bad block position data read out the bad block position data register area, wherein the bad block position data in the bad block position data register area are defined by such a bit position assignment scheme that one bit is assigned to one block under the condition that block positions in the cell array and column positions in one page are set in one-to-one correspondence.
摘要翻译：非易失性半导体存储器件包括：存储单元阵列; 在存储单元阵列中定义的坏块位置数据寄存器区域，用于存储坏块位置数据; 配置为选择所述单元阵列中的块的地址解码器电路; 以及设置在地址解码器电路中的坏块标志锁存器，根据读出坏块位置数据寄存器区域的坏块位置数据，在坏块标志中设置坏块标志锁存，其中坏块位置数据在坏通过这样的位位置分配方案来定义块位置数据寄存器区域，即在一页对应的单元阵列中的块位置和列位置被设置为一一对应的条件下，一位被分配给一个块。

49. 发明授权

US07911823B2 Method of programming a non-volatile memory device 有权
标题翻译：编程非易失性存储器件的方法
公开(公告)号：US07911823B2
公开(公告)日：2011-03-22
申请号：US12123827
申请日：2008-05-20
申请人： Takuya Futatsuyama , Koji Hosono , Toshiaki Edahiro , Naoya Tokiwa , Kazushige Kanda , Shigeo Ohshima
发明人： Takuya Futatsuyama , Koji Hosono , Toshiaki Edahiro , Naoya Tokiwa , Kazushige Kanda , Shigeo Ohshima
IPC分类号： G11C11/00 , G11C7/00 , G11C7/02 , G11C7/12 , G11C8/08
CPC分类号： G11C11/36
摘要： A method of programming a non-volatile memory device with memory cells formed of variable resistance elements and disposed between word lines and bit lines, includes: previously charging a selected word line and a selected bit line together with a non-selected word line and a non-selected bit line up to a certain voltage; and further charging the selected word line and the non-selected bit line up to a program voltage higher than the certain voltage and a program-block voltage, respectively, and simultaneously discharging the selected bit line.
摘要翻译：一种使用由可变电阻元件形成并且设置在字线和位线之间的存储单元来编程非易失性存储器件的方法包括：预先对所选择的字线和所选择的位线以及未选择的字线和非选择位线达到一定电压; 并且进一步对所选字线和未选择的位线进行充电，直到分别高于特定电压和编程块电压的编程电压，并同时对所选择的位线进行放电。

50. 发明授权

US07876626B2 Semiconductor memory device and semiconductor memory system 有权
标题翻译：半导体存储器件和半导体存储器系统
公开(公告)号：US07876626B2
公开(公告)日：2011-01-25
申请号：US12408232
申请日：2009-03-20
申请人： Hideo Mukai , Hiroshi Maejima , Satoru Takase , Naoya Tokiwa , Katsuaki Isobe
发明人： Hideo Mukai , Hiroshi Maejima , Satoru Takase , Naoya Tokiwa , Katsuaki Isobe
IPC分类号： G11C7/00
CPC分类号： G11C8/10 , G11C7/18 , G11C7/22 , G11C8/08 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0023 , G11C13/0028 , G11C13/0069 , G11C2013/0076 , G11C2207/2263 , G11C2211/5647 , G11C2213/31 , G11C2213/56 , G11C2213/72
摘要： A semiconductor memory device comprises a memory cell array including a plurality of memory cells arranged at intersections of word lines and bit lines; a read/write circuit operative to execute data read/write to the memory cell; and an operational circuit operative to compare certain length data read out by the read/write circuit from plural ones of the memory cells with certain length data to be written in the plural memory cells to make a decision, and create a flag representing the decision result. The read/write circuit inverts each bit in the certain length data to be written in the memory cells in accordance with the flag, and writes only rewrite-intended data of the certain length data and the flag. The read/write circuit reads the certain length data together with the flag corresponding thereto, and inverts each bit in the certain length data in accordance with the flag.
摘要翻译：半导体存储器件包括存储单元阵列，其包括布置在字线和位线的交点处的多个存储单元; 读/写电路，用于执行对存储器单元的数据读/写; 以及操作电路，用于将来自多个存储器单元的读/写电路读出的某些长度数据与要写入多个存储器单元的一定长度数据进行比较，并作出决定，并创建表示决定结果的标志。读/写电路根据该标志反转要写入存储单元的一定长度数据中的每个位，并且仅写入特定长度数据和标志的重写预期数据。读/写电路读取与其对应的标志一定的长度数据，并根据该标志反转一定长度数据中的每一位。

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