专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07889537B2 Non-volatile memory device and method for writing data thereto 有权
标题翻译：用于向其写入数据的非易失性存储器件和方法
公开(公告)号：US07889537B2
公开(公告)日：2011-02-15
申请号：US12118064
申请日：2008-05-09
申请人： Toshiaki Edahiro , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
发明人： Toshiaki Edahiro , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
IPC分类号： G11C11/00 , G11C17/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/009 , G11C2213/32 , G11C2213/72
摘要： The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.
摘要翻译：本发明提供一种将数据写入非易失性存储器件的方法，该非易失性存储器件具有彼此相交的第一布线和第二布线以及布置在其间的每个交叉处的存储单元，每个存储单元具有可变电阻元件和整流元件系列。根据该方法，在所选择的第一布线中升高之前，将第二布线充电至不小于整流元件阈值的一定电压。然后，将所选择的第一布线充电到写入或擦除所需的电压，之后放电所选择的第二布线。

2. 发明授权

US08000155B2 Non-volatile memory device and method for writing data thereto 有权
公开(公告)号：US08000155B2
公开(公告)日：2011-08-16
申请号：US13005582
申请日：2011-01-13
申请人： Toshiaki Edahiro , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
发明人： Toshiaki Edahiro , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
IPC分类号： G11C7/22 , G11C7/06 , G11C11/00 , G11C17/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/009 , G11C2213/32 , G11C2213/72
摘要： The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.

3. 发明申请

US20110103135A1 NON-VOLATILE MEMORY DEVICE AND METHOD FOR WRITING DATA THERETO 有权
标题翻译：非易失性存储器件及其数据写入方法
公开(公告)号：US20110103135A1
公开(公告)日：2011-05-05
申请号：US13005582
申请日：2011-01-13
申请人： Toshiaki EDAHIRO , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
发明人： Toshiaki EDAHIRO , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/009 , G11C2213/32 , G11C2213/72
摘要： The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.
摘要翻译：本发明提供一种将数据写入非易失性存储器件的方法，该非易失性存储器件具有彼此相交的第一布线和第二布线以及布置在其间的每个交叉处的存储单元，每个存储单元具有可变电阻元件和整流元件系列。根据该方法，在所选择的第一布线中升高之前，将第二布线充电至不小于整流元件阈值的一定电压。然后，将所选择的第一布线充电到写入或擦除所需的电压，之后放电所选择的第二布线。

4. 发明申请

US20090010039A1 NON-VOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件
公开(公告)号：US20090010039A1
公开(公告)日：2009-01-08
申请号：US12132972
申请日：2008-06-04
申请人： Naoya Tokiwa , Kazushige Kanda , Toshiaki Edahiro , Koji Hosono , Takuya Futatsuyama , Shigeo Ohsima
发明人： Naoya Tokiwa , Kazushige Kanda , Toshiaki Edahiro , Koji Hosono , Takuya Futatsuyama , Shigeo Ohsima
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/0097 , G11C2013/0092 , G11C2213/32 , G11C2213/72
摘要： According to one embodiment, a nonvolatile memory device includes: a memory cell array including memory cells each having a variable resistance element for nonvolatilely storing data identified by an electrically rewritable resistance value; a first data latch storing write and erase data to be written on a given group of memory cells of the memory cell array for a write and erase operation; and a second data latch storing reference data for performing a compensation operation of the given group to compensate write and erase disturbance accompanied by the write or erase operation.
摘要翻译：根据一个实施例，非易失性存储器件包括：存储单元阵列，其包括各自具有用于非易失性地存储由电可重写电阻值识别的数据的可变电阻元件的存储单元; 存储要写入存储单元阵列的给定组的存储单元的用于写入和擦除操作的写入和擦除数据的第一数据锁存器; 以及第二数据锁存器，存储用于执行给定组的补偿操作以补偿伴随着写入或擦除操作的写入和擦除干扰的参考数据。

5. 发明申请

US20080291716A1 METHOD OF PROGRAMMING A NON-VOLATILE MEMORY DEVICE 有权
标题翻译：编程非易失性存储器件的方法
公开(公告)号：US20080291716A1
公开(公告)日：2008-11-27
申请号：US12123827
申请日：2008-05-20
申请人： Takuya Futatsuyama , Koji Hosono , Toshiaki Edahiro , Naoya Tokiwa , Kazushige Kanda , Shigeo Ohshima
发明人： Takuya Futatsuyama , Koji Hosono , Toshiaki Edahiro , Naoya Tokiwa , Kazushige Kanda , Shigeo Ohshima
IPC分类号： G11C11/00
CPC分类号： G11C11/36
摘要： A method of programming a non-volatile memory device with memory cells formed of variable resistance elements and disposed between word lines and bit lines, includes: previously charging a selected word line and a selected bit line together with a non-selected word line and a non-selected bit line up to a certain voltage; and further charging the selected word line and the non-selected bit line up to a program voltage higher than the certain voltage and a program-block voltage, respectively, and simultaneously discharging the selected bit line.
摘要翻译：一种使用由可变电阻元件形成并且设置在字线和位线之间的存储单元来编程非易失性存储器件的方法包括：预先对所选择的字线和所选择的位线以及未选择的字线和非选择位线达到一定电压; 并且进一步对所选字线和未选择的位线进行充电，直到分别高于特定电压和编程块电压的编程电压，并同时对所选择的位线进行放电。

6. 发明授权

US08289800B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08289800B2
公开(公告)日：2012-10-16
申请号：US12693824
申请日：2010-01-26
申请人： Takuya Futatsuyama , Naoya Tokiwa
发明人： Takuya Futatsuyama , Naoya Tokiwa
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C16/30
摘要： A nonvolatile semiconductor memory device has an internal step-down power generation circuit and a memory circuit. The internal step-down power generation circuit generates a first internal power supply voltage from an external power supply voltage in an active state, and generates a second internal power supply voltage different from the first internal power supply voltage from the external power supply voltage in a standby state. The memory circuit includes a cell array containing a nonvolatile memory cell and a sense amplifier detecting data read from the cell array. The sense amplifier is supplied with a voltage generated by the internal step-down power generation circuit as an internal power supply voltage.
摘要翻译：非易失性半导体存储器件具有内部降压发电电路和存储电路。内部降压发电电路从活动状态的外部电源电压产生第一内部电源电压，并且从外部电源电压生成与第一内部电源电压不同的第二内部电源电压待机状态。存储电路包括一个包含非易失性存储单元的单元阵列和一个检测从该单元阵列读出的数据的读出放大器。感测放大器被提供有由内部降压发电电路产生的电压作为内部电源电压。

7. 发明授权

US07911823B2 Method of programming a non-volatile memory device 有权
标题翻译：编程非易失性存储器件的方法
公开(公告)号：US07911823B2
公开(公告)日：2011-03-22
申请号：US12123827
申请日：2008-05-20
申请人： Takuya Futatsuyama , Koji Hosono , Toshiaki Edahiro , Naoya Tokiwa , Kazushige Kanda , Shigeo Ohshima
发明人： Takuya Futatsuyama , Koji Hosono , Toshiaki Edahiro , Naoya Tokiwa , Kazushige Kanda , Shigeo Ohshima
IPC分类号： G11C11/00 , G11C7/00 , G11C7/02 , G11C7/12 , G11C8/08
CPC分类号： G11C11/36
摘要： A method of programming a non-volatile memory device with memory cells formed of variable resistance elements and disposed between word lines and bit lines, includes: previously charging a selected word line and a selected bit line together with a non-selected word line and a non-selected bit line up to a certain voltage; and further charging the selected word line and the non-selected bit line up to a program voltage higher than the certain voltage and a program-block voltage, respectively, and simultaneously discharging the selected bit line.
摘要翻译：一种使用由可变电阻元件形成并且设置在字线和位线之间的存储单元来编程非易失性存储器件的方法包括：预先对所选择的字线和所选择的位线以及未选择的字线和非选择位线达到一定电压; 并且进一步对所选字线和未选择的位线进行充电，直到分别高于特定电压和编程块电压的编程电压，并同时对所选择的位线进行放电。

8. 发明授权

US07817457B2 Non-volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US07817457B2
公开(公告)日：2010-10-19
申请号：US12132972
申请日：2008-06-04
申请人： Naoya Tokiwa , Kazushige Kanda , Toshiaki Edahiro , Koji Hosono , Takuya Futatsuyama , Shigeo Ohshima
发明人： Naoya Tokiwa , Kazushige Kanda , Toshiaki Edahiro , Koji Hosono , Takuya Futatsuyama , Shigeo Ohshima
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/0097 , G11C2013/0092 , G11C2213/32 , G11C2213/72
摘要： According to one embodiment, a nonvolatile memory device includes: a memory cell array including memory cells each having a variable resistance element for nonvolatilely storing data identified by an electrically rewritable resistance value; a first data latch storing write and erase data to be written on a given group of memory cells of the memory cell array for a write and erase operation; and a second data latch storing reference data for performing a compensation operation of the given group to compensate write and erase disturbance accompanied by the write or erase operation.
摘要翻译：根据一个实施例，非易失性存储器件包括：存储单元阵列，其包括各自具有用于非易失性地存储由电可重写电阻值识别的数据的可变电阻元件的存储单元; 存储要写入存储单元阵列的给定组的存储单元的用于写入和擦除操作的写入和擦除数据的第一数据锁存器; 以及第二数据锁存器，存储用于执行给定组的补偿操作以补偿伴随着写入或擦除操作的写入和擦除干扰的参考数据。

9. 发明申请

US20090052227A1 NON-VOLATILE MEMORY DEVICE AND METHOD FOR WRITING DATA THERETO 有权
标题翻译：非易失性存储器件及其数据写入方法
公开(公告)号：US20090052227A1
公开(公告)日：2009-02-26
申请号：US12118064
申请日：2008-05-09
申请人： Toshiaki Edahiro , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
发明人： Toshiaki Edahiro , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
IPC分类号： G11C11/00 , G11C7/00 , G11C7/06
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/009 , G11C2213/32 , G11C2213/72
摘要： The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.
摘要翻译：本发明提供一种将数据写入非易失性存储器件的方法，该非易失性存储器件具有彼此相交的第一布线和第二布线以及布置在其间的每个交叉处的存储单元，每个存储单元具有可变电阻元件和整流元件系列。根据该方法，在所选择的第一布线中升高之前，将第二布线充电至不小于整流元件阈值的一定电压。然后，将所选择的第一布线充电到写入或擦除所需的电压，之后放电所选择的第二布线。

10. 发明授权

US08233325B2 NAND flash memory 有权
标题翻译： NAND闪存
公开(公告)号：US08233325B2
公开(公告)日：2012-07-31
申请号：US13108641
申请日：2011-05-16
申请人： Kiyofumi Sakurai , Takuya Futatsuyama
发明人： Kiyofumi Sakurai , Takuya Futatsuyama
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/08 , G11C8/08 , G11C16/0483
摘要： A method of controlling a programming of a flash memory with memory blocks. The method includes checking whether a selected block among the memory blocks belongs to a first group or a second group. The method further includes executing the programming from a least bit address when the selected block belongs to the first group. The method also includes executing the programming from a most bit address when the selected block belongs to the second group.
摘要翻译：一种利用存储块控制闪速存储器编程的方法。该方法包括检查存储器块中的所选块是否属于第一组或第二组。该方法还包括当所选择的块属于第一组时从最小位地址执行编程。该方法还包括当所选择的块属于第二组时从大多数位地址执行编程。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式