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1. 发明授权

US07911845B2 Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US07911845B2
公开(公告)日：2011-03-22
申请号：US12350398
申请日：2009-01-08
申请人： Naoya Tokiwa , Masanobu Shirakawa
发明人： Naoya Tokiwa , Masanobu Shirakawa
IPC分类号： G11C16/04
CPC分类号： G11C29/12 , G11C16/04 , G11C16/10 , G11C29/1201 , G11C2029/2602
摘要： A non-volatile semiconductor memory device includes: a memory cell array having electrically rewritable and non-volatile memory cells arranged; a data register circuit configured to hold write data to be written into the memory cell array; and an address decode circuit configured to decode a write address signal and control the write data-loading in the data register circuit, the address decode circuit being settable in such a multiple selection mode that the same write data is loaded in multiple registers in the data register circuit in correspondence to multiple addresses.
摘要翻译：非易失性半导体存储器件包括：具有布置的电可重写和非易失性存储单元的存储单元阵列; 数据寄存器电路，被配置为保持要写入存储单元阵列的写入数据; 以及地址解码电路，被配置为对写入地址信号进行解码并且控制数据寄存器电路中的写入数据加载，地址解码电路可以以相同的写入数据被加载到数据中的多个寄存器的多重选择模式中被设置寄存器电路对应于多个地址。

2. 发明授权

US07965552B2 Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US07965552B2
公开(公告)日：2011-06-21
申请号：US12343990
申请日：2008-12-24
申请人： Masanobu Shirakawa , Naoya Tokiwa
发明人： Masanobu Shirakawa , Naoya Tokiwa
IPC分类号： G11C16/04 , G11C8/10 , G11C5/02 , G11C29/00
CPC分类号： G11C16/20 , G11C16/0483 , G11C29/82
摘要： A non-volatile semiconductor memory device includes: a memory cell array; a bad block position data register area defined in the memory cell array to store bad block position data; an address decoder circuit configured to select a block in the cell array; and bad block flag latches disposed in the address decoder circuit, bad block flags being set in the bad block flag latches in accordance with the bad block position data read out the bad block position data register area, wherein the bad block position data in the bad block position data register area are defined by such a bit position assignment scheme that one bit is assigned to one block under the condition that block positions in the cell array and column positions in one page are set in one-to-one correspondence.
摘要翻译：非易失性半导体存储器件包括：存储单元阵列; 在存储单元阵列中定义的坏块位置数据寄存器区域，用于存储坏块位置数据; 配置为选择所述单元阵列中的块的地址解码器电路; 以及设置在地址解码器电路中的坏块标志锁存器，根据读出坏块位置数据寄存器区域的坏块位置数据，在坏块标志中设置坏块标志锁存，其中坏块位置数据在坏通过这样的位位置分配方案来定义块位置数据寄存器区域，即在一页对应的单元阵列中的块位置和列位置被设置为一一对应的条件下，一位被分配给一个块。

3. 发明申请

US20080123410A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20080123410A1
公开(公告)日：2008-05-29
申请号：US11773280
申请日：2007-07-03
申请人： Masanobu Shirakawa , Naoya Tokiwa
发明人： Masanobu Shirakawa , Naoya Tokiwa
IPC分类号： G11C11/34
CPC分类号： G11C8/08 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C29/835
摘要： A semiconductor memory device includes: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; a row decoder configured to select a memory cell in the memory cell array, the row decoder including a flag latch, in which a bad block flag is set for a bad block in the memory cell array; a sense amplifier configured to sense data of a selected memory cell in the memory cell array; and an output circuit configured to output read data in the sense amplifier, the output circuit including an output data fixing circuit configured to fix an output data at a logic level in accordance with the bad block flag.
摘要翻译：半导体存储器件包括：具有布置在其中的电可重写和非易失性存储单元的存储单元阵列; 行解码器，其被配置为选择存储单元阵列中的存储单元，所述行解码器包括标志锁存器，其中对所述存储单元阵列中的坏块设置坏块标志; 感测放大器，被配置为感测所述存储器单元阵列中的选定存储单元的数据; 以及输出电路，被配置为在所述读出放大器中输出读取数据，所述输出电路包括输出数据固定电路，其被配置为根据所述坏块标志将输出数据固定在逻辑电平。

4. 发明申请

US20090190405A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20090190405A1
公开(公告)日：2009-07-30
申请号：US12350398
申请日：2009-01-08
申请人： Naoya Tokiwa , Masanobu Shirakawa
发明人： Naoya Tokiwa , Masanobu Shirakawa
IPC分类号： G11C16/04 , G11C8/00 , G11C16/06
CPC分类号： G11C29/12 , G11C16/04 , G11C16/10 , G11C29/1201 , G11C2029/2602
摘要： A non-volatile semiconductor memory device includes: a memory cell array having electrically rewritable and non-volatile memory cells arranged; a data register circuit configured to hold write data to be written into the memory cell array; and an address decode circuit configured to decode a write address signal and control the write data-loading in the data register circuit, the address decode circuit being settable in such a multiple selection mode that the same write data is loaded in multiple registers in the data register circuit in correspondence to multiple addresses.
摘要翻译：非易失性半导体存储器件包括：具有布置的电可重写和非易失性存储单元的存储单元阵列; 数据寄存器电路，被配置为保持要写入存储单元阵列的写入数据; 以及地址解码电路，被配置为对写入地址信号进行解码并且控制数据寄存器电路中的写入数据加载，地址解码电路可以以相同的写入数据被加载到数据中的多个寄存器的多重选择模式中被设置寄存器电路对应于多个地址。

5. 发明授权

US07463515B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07463515B2
公开(公告)日：2008-12-09
申请号：US11773280
申请日：2007-07-03
申请人： Masanobu Shirakawa , Naoya Tokiwa
发明人： Masanobu Shirakawa , Naoya Tokiwa
IPC分类号： G11C16/26
CPC分类号： G11C8/08 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C29/835
摘要： A semiconductor memory device includes: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; a row decoder configured to select a memory cell in the memory cell array, the row decoder including a flag latch, in which a bad block flag is set for a bad block in the memory cell array; a sense amplifier configured to sense data of a selected memory cell in the memory cell array; and an output circuit configured to output read data in the sense amplifier, the output circuit including an output data fixing circuit configured to fix an output data at a logic level in accordance with the bad block flag.
摘要翻译：半导体存储器件包括：具有布置在其中的电可重写和非易失性存储单元的存储单元阵列; 行解码器，其被配置为选择存储单元阵列中的存储单元，所述行解码器包括标志锁存器，其中对所述存储单元阵列中的坏块设置坏块标志; 感测放大器，被配置为感测所述存储器单元阵列中的选定存储单元的数据; 以及输出电路，被配置为在所述读出放大器中输出读取数据，所述输出电路包括输出数据固定电路，其被配置为根据所述坏块标志将输出数据固定在逻辑电平。

6. 发明授权

US09003242B2 Semiconductor memory device and method of controlling the same 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US09003242B2
公开(公告)日：2015-04-07
申请号：US13428089
申请日：2012-03-23
申请人： Naoya Tokiwa
发明人： Naoya Tokiwa
IPC分类号： G06F11/00 , G11C29/44 , G11C13/00
CPC分类号： G11C29/44 , G11C13/0004 , G11C13/0007 , G11C2029/4402
摘要： According to one embodiment, a semiconductor memory device includes a memory cell array including a plurality of memory cells, a first register configured to store data of the memory cells, and a sequence control circuit configured to control the memory cell array and the first register. In at least a data read operation of the memory cells, the sequence control circuit reads out, from the memory cell array, data including flag information representing whether the number of failed bits is in an allowable range.
摘要翻译：根据一个实施例，半导体存储器件包括存储单元阵列，该存储单元阵列包括多个存储器单元，第一寄存器，被配置为存储存储单元的数据;以及序列控制电路，被配置为控制存储单元阵列和第一寄存器。在存储器单元的至少一个数据读取操作中，顺序控制电路从存储单元阵列读出包括表示故障位数是否在允许范围内的标志信息的数据。

7. 发明授权

US08228733B2 Three-dimensionally stacked nonvolatile semiconductor memory 有权
标题翻译：三维堆叠的非易失性半导体存储器
公开(公告)号：US08228733B2
公开(公告)日：2012-07-24
申请号：US13164938
申请日：2011-06-21
申请人： Naoya Tokiwa , Hideo Mukai
发明人： Naoya Tokiwa , Hideo Mukai
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C8/08 , G11C16/08 , G11C16/30 , G11C29/028 , G11C2029/1202 , H01L27/11578 , H01L27/11582
摘要： A three-dimensionally stacked nonvolatile semiconductor memory of an aspect of the present invention including conductive layers stacked on a semiconductor substrate in such a manner as to be insulated from one another, a bit line which is disposed on the stacked conductive layers, a semiconductor column which extends through the stacked conductive layers, word lines for which the stacked conductive layers except for the uppermost and lowermost conductive layers are used and which have a plate-like planar shape, memory cells provided at intersections of the word lines and the semiconductor column, a register circuit which has information to supply a potential suitable for each of the word lines, and a potential control circuit which reads the information retained in the register circuit in accordance with an input address signal of a word line and which supplies a potential suitable for the word line corresponding to the address signal.
摘要翻译：本发明的一个方面的三维叠层的非易失性半导体存储器包括以彼此绝缘的方式堆叠在半导体衬底上的导电层，布置在层叠的导电层上的位线，半导体柱其延伸穿过堆叠的导电层，使用除了最上面和最下面的导电层之外的层叠的导电层并且具有板状平面形状的字线，设置在字线和半导体柱的交叉处的存储单元，具有提供适于每个字线的电位的信息的寄存器电路以及根据字线的输入地址信号读取保存在寄存器电路中的信息的电位控制电路，并提供适于对应于地址信号的字线。

8. 发明申请

US20120026804A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20120026804A1
公开(公告)日：2012-02-02
申请号：US13271645
申请日：2011-10-12
申请人： Hiroyuki NAGASHIMA , Naoya Tokiwa
发明人： Hiroyuki NAGASHIMA , Naoya Tokiwa
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C13/0069 , G11C5/02 , G11C5/04 , G11C8/04 , G11C8/10 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0023 , G11C13/0038 , G11C13/0061 , G11C13/0064 , G11C2013/0078 , G11C2013/0092 , G11C2213/31 , G11C2213/71 , G11C2213/72
摘要： A semiconductor memory device comprises a plurality of memory layers arranged in multilayer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lines, and a plurality of memory cells connected at intersections of the first lines and the second lines; a pulse generator operative to generate pulses required for data access to the memory cell; and a control means operative to control the pulse generator such that the pulse output from the pulse generator has energy in accordance with the memory layer to which the access target memory cell belongs.
摘要翻译：半导体存储器件包括多层布置的多个存储层，每个存储层包括一个单元阵列，该单元阵列包含多条第一平行线，多条第二平行线与第一条线交叉，以及多个存储器在第一线和第二线的交叉处连接的细胞; 脉冲发生器，用于产生数据访问存储单元所需的脉冲; 以及控制装置，用于控制脉冲发生器，使得从脉冲发生器输出的脉冲具有与存取目标存储单元所属的存储层相对应的能量。

9. 发明授权

US07986557B2 Nonvolatile semiconductor memory device and nonvolatile semiconductor memory system 有权
标题翻译：非易失性半导体存储器件和非易失性半导体存储器系统
公开(公告)号：US07986557B2
公开(公告)日：2011-07-26
申请号：US12533529
申请日：2009-07-31
申请人： Naoya Tokiwa , Shigeo Ohshima
发明人： Naoya Tokiwa , Shigeo Ohshima
IPC分类号： G11C16/04 , G11C5/14
CPC分类号： G11C16/30 , G11C5/143 , G11C5/145 , G11C8/06 , G11C8/10 , G11C16/0483
摘要： A memory may include word lines; bit lines; cells provided corresponding to intersections between the word lines and the bit lines; sense amplifiers detecting data; a column decoder selecting a certain bit line for the sense amplifiers to output read data or receive write data; a row decoder configured to select a certain word line; a charge pump supplying power to the sense amplifiers, the column decoder, and the row decoder; a logic circuit controlling the sense amplifiers, the column decoder, and the row decoder based on an address selecting the memory cells; a first power source input applying a voltage to the logic circuit; and a second power source input applying a voltage higher than a voltage of the first power source input to the charge pump, and to supply power to the charge pump at least at a data reading time and a data writing time.
摘要翻译：存储器可以包括字线; 位线对应于字线和位线之间的交点提供的单元; 感测放大器检测数据; 选择用于读出放大器的特定位线以输出读取数据或接收写入数据的列解码器; 行解码器，被配置为选择某个字线; 电荷泵向读出放大器，列解码器和行解码器供电; 基于选择存储器单元的地址来控制读出放大器，列解码器和行解码器的逻辑电路; 向逻辑电路施加电压的第一电源输入; 以及施加比所述第一电源输入的电压高于所述电荷泵的电压的第二电源输入，以及至少在数据读取时和数据写入时间向所述电荷泵供电。

10. 发明申请

US20110134681A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110134681A1
公开(公告)日：2011-06-09
申请号：US13027798
申请日：2011-02-15
申请人： Hiroyuki NAGASHIMA , Naoya Tokiwa
发明人： Hiroyuki NAGASHIMA , Naoya Tokiwa
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C5/02 , G11C5/04 , G11C8/04 , G11C8/10 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0023 , G11C13/0038 , G11C13/0061 , G11C13/0064 , G11C2013/0078 , G11C2013/0092 , G11C2213/31 , G11C2213/71 , G11C2213/72
摘要： A semiconductor memory device comprises a plurality of memory layers arranged in multi layer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lines, and a plurality of memory cells connected at intersections of the first lines and the second lines; a pulse generator operative to generate pulses required for data access to the memory cell; and a control means operative to control the pulse generator such that the pulse output from the pulse generator has energy in accordance with the memory layer to which the access target memory cell belongs.
摘要翻译：半导体存储器件包括多层布置的多个存储层，每个存储层包括一个单元阵列，该单元阵列包含多条第一平行线，多条第二平行线与第一条线交叉，存储单元连接在第一行和第二行的交点处; 脉冲发生器，用于产生数据访问存储单元所需的脉冲; 以及控制装置，用于控制脉冲发生器，使得从脉冲发生器输出的脉冲具有与存取目标存储单元所属的存储层相对应的能量。

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