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1. 发明授权

US07911845B2 Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US07911845B2
公开(公告)日：2011-03-22
申请号：US12350398
申请日：2009-01-08
申请人： Naoya Tokiwa , Masanobu Shirakawa
发明人： Naoya Tokiwa , Masanobu Shirakawa
IPC分类号： G11C16/04
CPC分类号： G11C29/12 , G11C16/04 , G11C16/10 , G11C29/1201 , G11C2029/2602
摘要： A non-volatile semiconductor memory device includes: a memory cell array having electrically rewritable and non-volatile memory cells arranged; a data register circuit configured to hold write data to be written into the memory cell array; and an address decode circuit configured to decode a write address signal and control the write data-loading in the data register circuit, the address decode circuit being settable in such a multiple selection mode that the same write data is loaded in multiple registers in the data register circuit in correspondence to multiple addresses.
摘要翻译：非易失性半导体存储器件包括：具有布置的电可重写和非易失性存储单元的存储单元阵列; 数据寄存器电路，被配置为保持要写入存储单元阵列的写入数据; 以及地址解码电路，被配置为对写入地址信号进行解码并且控制数据寄存器电路中的写入数据加载，地址解码电路可以以相同的写入数据被加载到数据中的多个寄存器的多重选择模式中被设置寄存器电路对应于多个地址。

2. 发明授权

US07965552B2 Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US07965552B2
公开(公告)日：2011-06-21
申请号：US12343990
申请日：2008-12-24
申请人： Masanobu Shirakawa , Naoya Tokiwa
发明人： Masanobu Shirakawa , Naoya Tokiwa
IPC分类号： G11C16/04 , G11C8/10 , G11C5/02 , G11C29/00
CPC分类号： G11C16/20 , G11C16/0483 , G11C29/82
摘要： A non-volatile semiconductor memory device includes: a memory cell array; a bad block position data register area defined in the memory cell array to store bad block position data; an address decoder circuit configured to select a block in the cell array; and bad block flag latches disposed in the address decoder circuit, bad block flags being set in the bad block flag latches in accordance with the bad block position data read out the bad block position data register area, wherein the bad block position data in the bad block position data register area are defined by such a bit position assignment scheme that one bit is assigned to one block under the condition that block positions in the cell array and column positions in one page are set in one-to-one correspondence.
摘要翻译：非易失性半导体存储器件包括：存储单元阵列; 在存储单元阵列中定义的坏块位置数据寄存器区域，用于存储坏块位置数据; 配置为选择所述单元阵列中的块的地址解码器电路; 以及设置在地址解码器电路中的坏块标志锁存器，根据读出坏块位置数据寄存器区域的坏块位置数据，在坏块标志中设置坏块标志锁存，其中坏块位置数据在坏通过这样的位位置分配方案来定义块位置数据寄存器区域，即在一页对应的单元阵列中的块位置和列位置被设置为一一对应的条件下，一位被分配给一个块。

3. 发明申请

US20080123410A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20080123410A1
公开(公告)日：2008-05-29
申请号：US11773280
申请日：2007-07-03
申请人： Masanobu Shirakawa , Naoya Tokiwa
发明人： Masanobu Shirakawa , Naoya Tokiwa
IPC分类号： G11C11/34
CPC分类号： G11C8/08 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C29/835
摘要： A semiconductor memory device includes: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; a row decoder configured to select a memory cell in the memory cell array, the row decoder including a flag latch, in which a bad block flag is set for a bad block in the memory cell array; a sense amplifier configured to sense data of a selected memory cell in the memory cell array; and an output circuit configured to output read data in the sense amplifier, the output circuit including an output data fixing circuit configured to fix an output data at a logic level in accordance with the bad block flag.
摘要翻译：半导体存储器件包括：具有布置在其中的电可重写和非易失性存储单元的存储单元阵列; 行解码器，其被配置为选择存储单元阵列中的存储单元，所述行解码器包括标志锁存器，其中对所述存储单元阵列中的坏块设置坏块标志; 感测放大器，被配置为感测所述存储器单元阵列中的选定存储单元的数据; 以及输出电路，被配置为在所述读出放大器中输出读取数据，所述输出电路包括输出数据固定电路，其被配置为根据所述坏块标志将输出数据固定在逻辑电平。

4. 发明申请

US20090190405A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20090190405A1
公开(公告)日：2009-07-30
申请号：US12350398
申请日：2009-01-08
申请人： Naoya Tokiwa , Masanobu Shirakawa
发明人： Naoya Tokiwa , Masanobu Shirakawa
IPC分类号： G11C16/04 , G11C8/00 , G11C16/06
CPC分类号： G11C29/12 , G11C16/04 , G11C16/10 , G11C29/1201 , G11C2029/2602
摘要： A non-volatile semiconductor memory device includes: a memory cell array having electrically rewritable and non-volatile memory cells arranged; a data register circuit configured to hold write data to be written into the memory cell array; and an address decode circuit configured to decode a write address signal and control the write data-loading in the data register circuit, the address decode circuit being settable in such a multiple selection mode that the same write data is loaded in multiple registers in the data register circuit in correspondence to multiple addresses.
摘要翻译：非易失性半导体存储器件包括：具有布置的电可重写和非易失性存储单元的存储单元阵列; 数据寄存器电路，被配置为保持要写入存储单元阵列的写入数据; 以及地址解码电路，被配置为对写入地址信号进行解码并且控制数据寄存器电路中的写入数据加载，地址解码电路可以以相同的写入数据被加载到数据中的多个寄存器的多重选择模式中被设置寄存器电路对应于多个地址。

5. 发明授权

US07463515B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07463515B2
公开(公告)日：2008-12-09
申请号：US11773280
申请日：2007-07-03
申请人： Masanobu Shirakawa , Naoya Tokiwa
发明人： Masanobu Shirakawa , Naoya Tokiwa
IPC分类号： G11C16/26
CPC分类号： G11C8/08 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C29/835
摘要： A semiconductor memory device includes: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; a row decoder configured to select a memory cell in the memory cell array, the row decoder including a flag latch, in which a bad block flag is set for a bad block in the memory cell array; a sense amplifier configured to sense data of a selected memory cell in the memory cell array; and an output circuit configured to output read data in the sense amplifier, the output circuit including an output data fixing circuit configured to fix an output data at a logic level in accordance with the bad block flag.
摘要翻译：半导体存储器件包括：具有布置在其中的电可重写和非易失性存储单元的存储单元阵列; 行解码器，其被配置为选择存储单元阵列中的存储单元，所述行解码器包括标志锁存器，其中对所述存储单元阵列中的坏块设置坏块标志; 感测放大器，被配置为感测所述存储器单元阵列中的选定存储单元的数据; 以及输出电路，被配置为在所述读出放大器中输出读取数据，所述输出电路包括输出数据固定电路，其被配置为根据所述坏块标志将输出数据固定在逻辑电平。

6. 发明授权

US08649224B2 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08649224B2
公开(公告)日：2014-02-11
申请号：US13329553
申请日：2011-12-19
申请人： Masanobu Shirakawa , Hiroshi Sukegawa
发明人： Masanobu Shirakawa , Hiroshi Sukegawa
IPC分类号： G11C11/34
CPC分类号： G11C16/3422 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C2213/71
摘要： A control circuit performs a read operation of reading data held in a memory-cell by supplying a selected word-line with a read voltage that is a voltage between the lower limit and the upper limit of a plurality of threshold-voltage distributions provided to the memory-cell. The control circuit also performs a verify operation of determining whether a write operation is completed by supplying a selected word-line with a verify voltage higher than the read voltage to read the memory cell. The control circuit then performs a data variation determination operation of determining whether the memory-cells connected to a selected word-line each have a threshold voltage equal to or less than a certain value to determine, from among the plurality of memory cells connected to the selected word-line, whether the number of memory cells where data variation has occurred is not less than a certain number.
摘要翻译：控制电路通过向所选择的字线提供读取电压来执行对存储单元中保持的数据的读取操作，该读取电压是设置在该存储单元中的多个阈值电压分布的下限和上限之间的电压记忆单元控制电路还通过提供具有高于读取电压的验证电压的所选字线来执行写入操作是否完成的验证操作，以读取存储单元。控制电路然后执行数据变化确定操作，确定连接到所选字线的存储器单元是否具有等于或小于某一值的阈值电压，以从连接到所述字线的多个存储器单元中确定选择的字线，是否发生数据变化的存储单元的数量不少于一定数量。

7. 发明授权

US07884859B2 Digital camera 有权
标题翻译：数码相机
公开(公告)号：US07884859B2
公开(公告)日：2011-02-08
申请号：US10543056
申请日：2003-12-25
申请人： Yasumasa Nakajima , Shuji Tsuji , Masanobu Shirakawa
发明人： Yasumasa Nakajima , Shuji Tsuji , Masanobu Shirakawa
IPC分类号： H04N5/76
CPC分类号： H04N5/262 , H04N5/772 , H04N5/907 , H04N9/8042
摘要： A digital camera including a layout inputting unit that inputs a layout in drawing a digital image, an internal memory stored with the inputted layout, a selection receiving unit (S400) that receives selection of the layout stored in the internal memory, an object image outputting unit (S410, S420) that outputs the digital image outputted by the converting unit to a removable memory by being related to the layout selected by the selection receiving unit, and a layout unit (S440) that outputs the layout stored in the internal memory in the removable memory stored with the digital image by the object image outputting unit.
摘要翻译：一种数字照相机，包括输入绘制数字图像的布局的布局输入单元，存储有输入布局的内部存储器，接收对存储在内部存储器中的布局的选择的选择接收单元（S400），输出的对象图像单元（S410，S420），其通过与由选择接收单元选择的布局相关地将由转换单元输出的数字图像输出到可移动存储器;以及布局单元（S440），其输出存储在内部存储器中的布局通过对象图像输出单元与数字图像一起存储的可移动存储器。

8. 发明授权

US07679977B2 Semiconductor memory device and test method thereof 失效
标题翻译：半导体存储器件及其测试方法
公开(公告)号：US07679977B2
公开(公告)日：2010-03-16
申请号：US11773119
申请日：2007-07-03
申请人： Masanobu Shirakawa
发明人： Masanobu Shirakawa
IPC分类号： G11C29/00
CPC分类号： G11C11/5628 , G11C16/04 , G11C16/0483 , G11C16/3454 , G11C16/3459 , G11C29/028 , G11C29/12005 , G11C29/50 , G11C29/50004 , G11C2211/5621
摘要： A semiconductor memory device including a memory cell array with electrically rewritable and non-volatile memory cells arranged therein, wherein the device has such a test mode that includes a page searching sequence for searching a fast page with the fastest write speed in the memory cell array.
摘要翻译：一种包括其中布置有电可重写和非易失性存储单元的存储单元阵列的半导体存储器件，其中该器件具有这样的测试模式，该测试模式包括用于在存储单元阵列中以最快的写入速度搜索快速寻址的寻呼序列。

9. 发明授权

US07466350B2 Digital camera recording a composite image 有权
标题翻译：数码相机拍摄合成图像
公开(公告)号：US07466350B2
公开(公告)日：2008-12-16
申请号：US11003761
申请日：2004-12-06
申请人： Shuji Tsuji , Yasumasa Nakajima , Masanobu Shirakawa
发明人： Shuji Tsuji , Yasumasa Nakajima , Masanobu Shirakawa
IPC分类号： H04N5/76
CPC分类号： H04N5/2621 , H04N5/272
摘要： A digital camera capable of recording a subject image so that the subject image can be drawn as it is combined with a selected default image and so that the subject image can be drawn separately from the selected default image. The digital camera includes an image processor which creates subject image data based on output of an image sensor and a default image setting unit which stores subject image data in a removable memory together with information for associating background data with the subject image data, whereby the subject image data, rather than the data provided by combining the subject image data and the background data, is stored in the removable memory and the subject image data and the background data are associated with each other.
摘要翻译：能够记录被摄体图像的数字照相机，使得被摄体图像能够被绘制为与所选择的默认图像组合，并且可以与所选择的默认图像分离地绘制被摄体图像。数字照相机包括：图像处理器，其基于图像传感器的输出创建被摄体图像数据;以及默认图像设置单元，用于将背景数据与对象图像数据相关联的信息与用于将背景数据相关联的主题图像数据存储在可移动存储器中，由此，图像数据而不是通过组合主体图像数据和背景数据提供的数据被存储在可移动存储器中，并且对象图像数据和背景数据彼此相关联。

10. 发明申请

US20080112222A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：US20080112222A1
公开(公告)日：2008-05-15
申请号：US11935562
申请日：2007-11-06
申请人： Masanobu Shirakawa
发明人： Masanobu Shirakawa
IPC分类号： G11C16/04
CPC分类号： G11C11/5621 , G11C16/349 , G11C29/88 , G11C2211/5641
摘要： A non-volatile semiconductor memory device includes: a memory chip configured to be electrically rewritable and store such multi-level data as being defined by n-bits/cell (where n≧2); and a memory controller configured to control read and write of the memory chip, wherein the operation mode of the memory chip is changed from n-bits/cell to m-bits/cell (where m
摘要翻译：非易失性半导体存储器件包括：被配置为电可重写的存储器芯片，并存储由n位/单元（其中n≥2）定义的多电平数据; 以及存储器控制器，其被配置为控制所述存储器芯片的读取和写入，其中当所述存储器芯片的数量较晚时，所述存储器芯片的操作模式从n位/单元变为m位/单元（其中m

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