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41. 发明申请

US20080263497A1 Enhanced Routing Grid System and Method 审中-公开
公开(公告)号：US20080263497A1
公开(公告)日：2008-10-23
申请号：US12062286
申请日：2008-04-03
申请人： Sharad Mehrotra , Parsotam T. Patel , Joe T. Rahmeh , Jeanette N. Sutherland
发明人： Sharad Mehrotra , Parsotam T. Patel , Joe T. Rahmeh , Jeanette N. Sutherland
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Routing systems and methods are provided having various strategies for optimizing and evaluating possible routes for netlist connections. In one embodiment, a data structure or matrix provides cost related data weighted to evaluate the impact proposed a connection or segment will have upon an attribute of interest such as, for example, speed, manufacturability or noise tolerance. This cost information can be related to terrain costs as well as shape costs to provide multidimensional cost information for connections. Processing such higher information cost data is made more efficient with an additive process that is less demanding than a computationally intensive iterative multiplication process. Various methods are also disclosed for shifting and adjusting routing grids to improve use of available space or reduce run time in routing. In another embodiment, a parallel processing scheme is used to process multiple regions on multiple processors simultaneously without creating conflicts, that could arise, for example, when two processors try to route a trace on the same gridpoint.

42. 发明申请

US20080072201A1 Enhanced Routing Grid System And Method 审中-公开
标题翻译：增强路由网格系统和方法
公开(公告)号：US20080072201A1
公开(公告)日：2008-03-20
申请号：US11934527
申请日：2007-11-02
申请人： Sharad Mehrotra , Parsotam Patel , Joe Rahmeh , Jeannette Sutherland
发明人： Sharad Mehrotra , Parsotam Patel , Joe Rahmeh , Jeannette Sutherland
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Routing systems and methods are provided having various strategies for optimizing and evaluating possible routes for netlist connections. In one embodiment, a data structure or matrix provides cost related data weighted to evaluate the impact proposed a connection or segment will have upon an attribute of interest such as, for example, speed, manufacturability or noise tolerance. This cost information can be related to terrain costs as well as shape costs to provide multidimensional cost information for connections. Processing such higher information cost data is made more efficient with an additive process that is less demanding than a computationally intensive iterative multiplication process. Various method are also disclosed for shifting and adjusting routing grides to improve use of available space or reduce run time in routing. In another embodiment, a parallel processing scheme is used to process multiple regions on multiple processors simulataneously without creating conflicts, that could arise, for example, when two processors try to route a trace on the same gridpoint.
摘要翻译：提供了路由系统和方法，其具有用于优化和评估网表连接的可能路由的各种策略。在一个实施例中，数据结构或矩阵提供加权的成本相关数据，以评估连接或分段将对感兴趣的属性（例如速度，可制造性或噪声容限）提出的影响。该成本信息可以与地形成本以及形状成本相关联，以提供用于连接的多维成本信息。使用比计算密集型迭代乘法过程要求低的加法过程，处理这种更高信息成本数据变得更有效。还公开了用于移动和调整路线栅格以改善可用空间的使用或减少路由中的运行时间的各种方法。在另一个实施例中，使用并行处理方案来同时处理多个处理器上的多个区域而不产生冲突，例如当两个处理器尝试在同一网格点上路由跟踪时可能出现冲突。

43. 发明申请

US20080059936A1 Enhanced Routing Grid System And Method 审中-公开
公开(公告)号：US20080059936A1
公开(公告)日：2008-03-06
申请号：US11934565
申请日：2007-11-02
申请人： Sharad Mehrotra , Parsotam Patel , Joe Rahmeh , Jeanette Sutherland
发明人： Sharad Mehrotra , Parsotam Patel , Joe Rahmeh , Jeanette Sutherland
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Routing systems and methods are provided having various strategies for optimizing and evaluating possible routes for netlist connections. In one embodiment, a data structure or matrix provides cost related data weighted to evaluate the impact proposed a connection or segment will have upon an attribute of interest such as, for example, speed, manufacturability or noise tolerance. This cost information can be related to terrain costs as well as shape costs to provide multidimensional cost information for connections. Processing such higher information cost data is made more efficient with an additive process that is less demanding than a computationally intensive iterative multiplication process. Various methods are also disclosed for shifting and adjusting routing grids to improve use of available space or reduce run time in routing. In another embodiment, a parallel processing scheme is used to process multiple regions on multiple processors simultaneously without creating conflicts, that could arise, for example, when two processors try to route a trace on the same gridpoint.

44. 发明申请

US20070028201A1 Enhanced routing grid system and method 审中-公开
标题翻译：增强路由网格系统和方法
公开(公告)号：US20070028201A1
公开(公告)日：2007-02-01
申请号：US11477078
申请日：2006-06-28
申请人： Sharad Mehrotra , Parsotam Patel , Joe Rahmeh
发明人： Sharad Mehrotra , Parsotam Patel , Joe Rahmeh
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Routing systems and methods are provided having various strategies for optimizing and evaluating possible routes for netlist connections. In one embodiment, a data structure or matrix provides cost related data weighted to evaluate the impact proposed a connection or segment will have upon an attribute of interest such as, for example, speed, manufacturability or noise tolerance. This cost information can be related to terrain costs as well as shape costs to provide multidimensional cost information for connections. Processing such higher information cost data is made more efficient with an additive process that is less demanding than a computationally intensive iterative multiplication process. Various methods are also disclosed for shifting and adjusting routing grids to improve use of available space or reduce run time in routing. In another embodiment, a parallel processing scheme is used to process multiple regions on multiple processors simultaneously without creating conflicts, that could arise, for example, when two processors try to route a trace on the same gridpoint. In another embodiment, various methods are used to spread nets over one or more wiring layers.
摘要翻译：提供了路由系统和方法，其具有用于优化和评估网表连接的可能路由的各种策略。在一个实施例中，数据结构或矩阵提供加权的成本相关数据，以评估连接或分段将对感兴趣的属性（例如速度，可制造性或噪声容限）提出的影响。该成本信息可以与地形成本以及形状成本相关联，以提供用于连接的多维成本信息。使用比计算密集型迭代乘法过程要求低的加法过程，处理这种更高信息成本数据变得更有效。还公开了用于移动和调整路由网格以改进对可用空间的使用或减少路由中的运行时间的各种方法。在另一个实施例中，使用并行处理方案来同时处理多个处理器上的多个区域而不会产生冲突，例如当两个处理器尝试在同一网格点上路由跟踪时可能出现冲突。在另一个实施例中，使用各种方法将网络扩展到一个或多个布线层上。

45. 发明授权

US06601222B1 Coupled noise estimation and avoidance of noise-failure using global routing information 失效
标题翻译：使用全局路由信息耦合噪声估计和避免噪声故障
公开(公告)号：US06601222B1
公开(公告)日：2003-07-29
申请号：US09687132
申请日：2000-10-13
申请人： Sharad Mehrotra , Parsotam Trikam Patel , David J. Widiger
发明人： Sharad Mehrotra , Parsotam Trikam Patel , David J. Widiger
IPC分类号： G06F1750
CPC分类号： G06F17/5036 , G06F17/5077
摘要： Disclosed is a method for pre-design estimation of coupling noise and avoidance of coupling noise failures in interconnects. An initial routing of a plurality of nets is estimated utilizing global paths. Then, the worst-case and average-case models for various parameters of each net are evaluated. With these models, a noise analysis is completed by which a determination is made whether coupling noise of any one of the nets is above a threshold level for noise-induced failure (i.e., a noise-failure threshold). When it is determined that the estimated coupling noise of a net falls below the noise-failure threshold, a response mechanism is triggered for later implementation during detailed routing of the nets to prevent the coupling noise from reaching the noise-failure threshold.
摘要翻译：公开了一种用于耦合噪声的预设计估计和避免互连中的耦合噪声故障的方法。使用全局路径来估计多个网络的初始路由。然后，对每个网络的各种参数的最坏情况和平均情况模型进行评估。利用这些模型，完成噪声分析，通过该噪声分析确定任何一个网络的耦合噪声是否高于用于噪声引起的故障（即，噪声失效阈值）的阈值电平。当确定网络的估计耦合噪声低于噪声失效阈值时，在网络的详细路由期间触发响应机制以供稍后实现，以防止耦合噪声达到噪声失效阈值。

46. 发明授权

US06532574B1 Post-manufacture signal delay adjustment to solve noise-induced delay variations 失效
标题翻译：制造后信号延迟调整，以解决噪声引起的延迟变化
公开(公告)号：US06532574B1
公开(公告)日：2003-03-11
申请号：US09640537
申请日：2000-08-17
申请人： Christopher McCall Durham , Sharad Mehrotra , Alexander Koos Spencer , Barry Duane Williamson
发明人： Christopher McCall Durham , Sharad Mehrotra , Alexander Koos Spencer , Barry Duane Williamson
IPC分类号： G06F1750
CPC分类号： G06F17/5036 , G06F1/10 , G06F17/505
摘要： Adjacent signal lines within the critical path of logic within an integrated circuit are checked for capacitive coupling induced signal delay variations resulting from concurrent signal transitions. When found, signal transition overlap is eliminated by delaying the clock edge (rising or falling) triggering the signal driving logic, without necessarily delaying the other clock edge. A delay circuit is incorporated into clock stages for the signal driving logic, and may be selectively actuated to delay the clock edge to particular signal driving logic circuits. Selection of signal lines in which signal transitions are to be delayed may be performed after manufacture of the integrated circuit, and iterative determinations may be required since signal adjustment may create new critical paths within the integrated circuit logic. Once the final signal adjustment configuration is determined, that configuration may be stored as a vector within a memory in the integrated circuit and read during power-up into a scan chain controlling the individual delay circuits.
摘要翻译：检查集成电路内的逻辑关键路径内的相邻信号线，检查由并发信号转换引起的电容耦合感应信号延迟变化。当发现时，通过延迟触发信号驱动逻辑的时钟边沿（上升或下降）来消除信号转换重叠，而不必延迟另一个时钟沿。延迟电路被并入用于信号驱动逻辑的时钟级中，并且可以选择性地启动以将时钟沿延迟到特定信号驱动逻辑电路。可以在制造集成电路之后执行其中要延迟信号转换的信号线的选择，并且可能需要迭代确定，因为信号调整可能在集成电路逻辑内产生新的关键路径。一旦确定了最终信号调整配置，该配置可以作为向量存储在集成电路中的存储器中，并且在上电期间读取，以控制各个延迟电路的扫描链。

47. 发明授权

US06523149B1 Method and system to improve noise analysis performance of electrical circuits 失效
标题翻译：改善电路噪声分析性能的方法和系统
公开(公告)号：US06523149B1
公开(公告)日：2003-02-18
申请号：US09666272
申请日：2000-09-21
申请人： Sharad Mehrotra , Mark W. Wenning , David J. Widiger
发明人： Sharad Mehrotra , Mark W. Wenning , David J. Widiger
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A method, system and apparatus is provided to perform noise analysis of electrical circuits. The method and system partitions an original multi-port circuit to a reduced circuit model having a specific layout configuration. The reduced circuit model may have a variety of configurations. Then an input signal is applied to a first port of the reduced circuit model using the specific layout configuration and an output signal is measured from a second port of the reduced circuit model. The process continues until all input ports which may contribute noise to the circuit are measured and then the results are calculated to determine the total output of simulated noise experienced by the circuit. The calculated output results of the reduced circuit model are then used to determine whether the original circuit is designed to withstand the quantity of noise experienced by the reduced circuit model.
摘要翻译：提供了一种方法，系统和装置来执行电路的噪声分析。该方法和系统将原始多端口电路分为具有特定布局配置的简化电路模型。简化电路模型可以具有各种配置。然后使用特定布局配置将输入信号施加到减小电路模型的第一端口，并且从简化电路模型的第二端口测量输出信号。该过程继续进行，直到可能对电路产生噪声的所有输入端口进行测量，然后计算结果以确定电路经历的模拟噪声的总输出。然后，使用降低电路模型的计算输出结果来确定原始电路是否被设计成承受减小电路模型所经历的噪声量。

48. 发明授权

US06467069B2 Timing closure and noise avoidance in detailed routing 失效
标题翻译：详细路由中的定时关闭和避免噪声
公开(公告)号：US06467069B2
公开(公告)日：2002-10-15
申请号：US09737333
申请日：2000-12-15
申请人： Sharad Mehrotra , Parsotam Trikam Patel
发明人： Sharad Mehrotra , Parsotam Trikam Patel
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A method for timing and noise analysis in designing data processing chips is provided. The process begins by wiring all unconnected nets in the design and then using a 2½ D capacitance extraction technique built into a detailed router to extract all of the wired nets. The data from the extracted nets is then process using a timing and analysis tool. Optimization programs are then used to generate fixes for any nets in the design which contribute to timing and noise failures. The present invention gives designers the capability of fast and accurate interconnect extraction within the routing tool. In addition, this technique is incremental. Any wiring changes can be quickly re-extracted, since only local information is required for extraction. This incremental capability allows designers to perform quick iterations of wiring, extraction and timing analysis.
摘要翻译：提供了一种设计数据处理芯片的时序和噪声分析方法。该过程开始于将设计中所有未连接网络接线，然后使用内置于详细路由器中的2½D电容提取技术来提取所有有线网络。然后使用定时和分析工具处理来自提取的网络的数据。然后，优化程序用于为设计中的任何网络生成有助于定时和噪声故障的修复。本发明使设计人员能够在路由工具内快速准确的互连提取。此外，这种技术是增量的。任何布线变化都可以快速重新提取，因为只需要提取本地信息。这种增量功能允许设计人员快速地进行布线，提取和时序分析。

49. 发明授权

US6148371A Multi-level non-blocking cache system with inhibiting thrashing 失效
标题翻译：多级无阻塞缓存系统，具有抑制抖动
公开(公告)号：US6148371A
公开(公告)日：2000-11-14
申请号：US881727
申请日：1997-06-25
申请人： Ricky C. Hetherington , Sharad Mehrotra , Ramesh Panwar
发明人： Ricky C. Hetherington , Sharad Mehrotra , Ramesh Panwar
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0859
摘要： A data cache unit associated with a processor, the data cache unit including a first non-blocking cache receiving a data access from a device in the processor. A second non-blocking cache is coupled to the first non-blocking cache to service misses in the first non-blocking cache. A data return path coupled to the second non-blocking cache couples data returning from the second non-blocking cache to both the first non-blocking cache and the device generating the access to the first non-blocking cache.
摘要翻译：与处理器相关联的数据高速缓存单元，所述数据高速缓存单元包括从所述处理器中的设备接收数据访问的第一非阻塞缓存。第二非阻塞高速缓存耦合到第一非阻塞高速缓存以服务第一非阻塞高速缓存中的未命中。耦合到第二非阻塞缓存的数据返回路径将从第二非阻塞高速缓存返回的数据与第一非阻塞高速缓存和产生对第一非阻塞高速缓存的访问的设备耦合。

50. 发明授权

US5838582A Method and system for performing parasitic capacitance estimations on interconnect data within an integrated circuit 失效
标题翻译：用于对集成电路内的互连数据执行寄生电容估计的方法和系统
公开(公告)号：US5838582A
公开(公告)日：1998-11-17
申请号：US726720
申请日：1996-10-07
申请人： Sharad Mehrotra , Paul Gerard Villarrubia
发明人： Sharad Mehrotra , Paul Gerard Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method and system for providing parasitic capacitance estimation on interconnect data for an integrated circuit is disclosed. An integrated circuit typically includes a substrate layer and several metal layers. In accordance with the method and system of the present invention, a center wire within one of the several metal layers is first identified. Then, a first capacitance value between a first wire and the center wire as well as a second capacitance value between a second wire and the center wire are determined. The first wire, the second wire, and the center wire are in the same metal layer. Next, a third capacitance value between a third wire and the center wire is determined. This third wire is in a metal layer located directly beneath the center wire. Finally, a fourth capacitance value between a fourth wire and the center wire is determined. The fourth wire is in a metal layer located directly above the center wire. If there are more than one wire within the metal layer directly above the center wire, the fourth capacitance value is distributed among all these wires. By so doing, the total parasitic capacitance for the center wire can be estimated by utilizing the first capacitance value, the second capacitance value, the third capacitance value, and the fourth capacitance value or the distributed fourth capacitance values.
摘要翻译：公开了一种用于为集成电路的互连数据提供寄生电容估计的方法和系统。集成电路通常包括基底层和几个金属层。根据本发明的方法和系统，首先确定几个金属层之一内的中心线。然后，确定第一线和中心线之间的第一电容值以及第二线和中心线之间的第二电容值。第一线，第二线和中心线在相同的金属层中。接下来，确定第三线和中心线之间的第三电容值。该第三根导线位于中心线正下方的金属层中。最后，确定第四线和中心线之间的第四电容值。第四根导线位于中心线正上方的金属层中。如果在中心线正上方的金属层内存在多根线，则第四电容值分布在所有这些线之间。通过这样做，可以通过利用第一电容值，第二电容值，第三电容值和第四电容值或分布的第四电容值来估计中心线的总寄生电容。

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