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1. 发明授权

US06532574B1 Post-manufacture signal delay adjustment to solve noise-induced delay variations 失效
标题翻译：制造后信号延迟调整，以解决噪声引起的延迟变化
公开(公告)号：US06532574B1
公开(公告)日：2003-03-11
申请号：US09640537
申请日：2000-08-17
申请人： Christopher McCall Durham , Sharad Mehrotra , Alexander Koos Spencer , Barry Duane Williamson
发明人： Christopher McCall Durham , Sharad Mehrotra , Alexander Koos Spencer , Barry Duane Williamson
IPC分类号： G06F1750
CPC分类号： G06F17/5036 , G06F1/10 , G06F17/505
摘要： Adjacent signal lines within the critical path of logic within an integrated circuit are checked for capacitive coupling induced signal delay variations resulting from concurrent signal transitions. When found, signal transition overlap is eliminated by delaying the clock edge (rising or falling) triggering the signal driving logic, without necessarily delaying the other clock edge. A delay circuit is incorporated into clock stages for the signal driving logic, and may be selectively actuated to delay the clock edge to particular signal driving logic circuits. Selection of signal lines in which signal transitions are to be delayed may be performed after manufacture of the integrated circuit, and iterative determinations may be required since signal adjustment may create new critical paths within the integrated circuit logic. Once the final signal adjustment configuration is determined, that configuration may be stored as a vector within a memory in the integrated circuit and read during power-up into a scan chain controlling the individual delay circuits.
摘要翻译：检查集成电路内的逻辑关键路径内的相邻信号线，检查由并发信号转换引起的电容耦合感应信号延迟变化。当发现时，通过延迟触发信号驱动逻辑的时钟边沿（上升或下降）来消除信号转换重叠，而不必延迟另一个时钟沿。延迟电路被并入用于信号驱动逻辑的时钟级中，并且可以选择性地启动以将时钟沿延迟到特定信号驱动逻辑电路。可以在制造集成电路之后执行其中要延迟信号转换的信号线的选择，并且可能需要迭代确定，因为信号调整可能在集成电路逻辑内产生新的关键路径。一旦确定了最终信号调整配置，该配置可以作为向量存储在集成电路中的存储器中，并且在上电期间读取，以控制各个延迟电路的扫描链。

2. 发明授权

US06405352B1 Method and system for analyzing wire-only changes to a microprocessor design using delta model 失效
标题翻译：使用增量模型分析微处理器设计中仅有线变化的方法和系统
公开(公告)号：US06405352B1
公开(公告)日：2002-06-11
申请号：US09343448
申请日：1999-06-30
申请人： Alexander Koos Spencer , Barry Duane Williamson
发明人： Alexander Koos Spencer , Barry Duane Williamson
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A method for analyzing a design or a model of a microprocessor chip model is provided. A base chip model is generated, and it is modified with wire-only changes to produce a modified chip model. The modified chip model is compared to the base chip model to discern the wire-only changes to form a delta chip model. A set of values for RC delays and net capacitance based on the delta chip model is produced, and the modified chip model is timed using the set of values for RC delays and net capacitance on the delta chip model and RC delays and net capacitance on the base chip model.
摘要翻译：提供了一种用于分析微处理器芯片模型的设计或模型的方法。生成基本芯片模型，并通过有线修改来修改芯片模型。将修改的芯片模型与基本芯片模型进行比较，以辨别仅有线的变化以形成增量芯片模型。产生了一组基于增量芯片模型的RC延迟和净电容的值，并且修改后的芯片模型使用一组RC延迟和增量芯片模型上的净电容值，RC延迟和网络电容基本芯片型号。

3. 发明授权

US07900020B2 Correction of incorrect cache accesses 有权
标题翻译：更正错误的缓存访问
公开(公告)号：US07900020B2
公开(公告)日：2011-03-01
申请号：US12010512
申请日：2008-01-25
申请人： Barry Duane Williamson , Gerard Richard Williams , Muralidharan Santharaman Chinnakonda
发明人： Barry Duane Williamson , Gerard Richard Williams , Muralidharan Santharaman Chinnakonda
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F12/1054 , Y02D10/13
摘要： The application describes a data processor operable to process data, and comprising: a cache in which a storage location of a data item within said cache is identified by an address, said cache comprising a plurality of storage locations and said data processor comprising a cache directory operable to store a physical address indicator for each storage location comprising stored data; a hash value generator operable to generate a generated hash value from at least some of said bits of said address said generated hash value having fewer bits than said address; a buffer operable to store a plurality of hash values relating to said plurality of storage locations within said cache; wherein in response to a request to access said data item said data processor is operable to compare said generated hash value with at least some of said plurality of hash values stored within said buffer and in response to a match to indicate a indicated storage location of said data item; and said data processor is operable to access one of said physical address indicators stored within said cache directory corresponding to said indicated storage location and in response to said accessed physical address indicator not indicating said address said data processor is operable to invalidate said indicated storage location within said cache.
摘要翻译：应用程序描述可操作以处理数据的数据处理器，并且包括：高速缓存，其中通过地址识别所述高速缓存内的数据项的存储位置，所述高速缓存包括多个存储位置，并且所述数据处理器包括高速缓存目录可操作地存储包括存储的数据的每个存储位置的物理地址指示符; 哈希值发生器，用于从所述地址的所述比特中的至少一些产生生成的散列值，所述哈希值生成的哈希值具有比所述地址少的位; 缓冲器，用于存储与所述高速缓存内的所述多个存储位置相关的多个散列值; 其中响应于访问所述数据项的请求，所述数据处理器可操作以将所生成的散列值与所述缓冲器中存储的所述多个散列值中的至少一些进行比较，并响应于匹配来指示所述数据项的所指示的存储位置数据项; 并且所述数据处理器可操作以访问存储在与所述指示的存储位置相对应的所述高速缓存目录内的所述物理地址指示符之一，并且响应于所述访问的物理地址指示符不指示所述地址，所述数据处理器可操作以使所述指示的存储位置无效说缓存。

4. 发明授权

US06148394A Apparatus and method for tracking out of order load instructions to avoid data coherency violations in a processor 失效
标题翻译：用于跟踪不合格的加载指令以避免处理器中的数据一致性违规的装置和方法
公开(公告)号：US06148394A
公开(公告)日：2000-11-14
申请号：US21134
申请日：1998-02-10
申请人： Shih-Hsiung Stephen Tung , David Scott Ray , Kevin Arthur Chiarot , Barry Duane Williamson
发明人： Shih-Hsiung Stephen Tung , David Scott Ray , Kevin Arthur Chiarot , Barry Duane Williamson
IPC分类号： G06F9/38 , G06F12/08 , G06F9/312
CPC分类号： G06F9/3834 , G06F12/0859
摘要： The present invention is directed towards a means to detect and reorder out of order instructions that may violate data coherency. The invention comprises a mis-queue table for holding entries of instruction data, each entry corresponding to an instruction in a computer microprocesor. The instruction data in each entry comprises: i) address information for the instruction; ii) ordering information for the instruction, indicating the order of the instruction relative to other instructions in the mis-queue table; iii) data modification information for the instruction, for indicating a possibility of modified data; and iv) out of order information, for indicating that a newer instruction has completed before the corresponding older instruction to the entry. The invention also comprises an out of order comparator for comparing an address of a completed instruction to any address information entries in the miss queue. If a completed instruction accesses the same address as another instruction, as indicated in the address information in the mis-queue table, and the completed instruction is newer than the matched instruction, the out of order field is marked indicating this condition exists. The invention comprises a modification comparator. This compares addresses from data altering events to those addresses in the entries in the mis-queue table. On a match, the modification field of the corresponding entry is marked to indicate this condition exists. When an instruction entry indicates that the corresponding instruction's data is modified, and that the instruction is out of order, all subsequent instructions are canceled.
摘要翻译：本发明涉及一种检测和重新排序可能违反数据一致性的乱序指令的手段。本发明包括用于保存指令数据条目的错误队列表，每个条目对应于计算机微处理器中的指令。每个条目中的指令数据包括：i）指令的地址信息; ii）订购指令的信息，指示相对于错误队列表中的其他指令的指令的顺序; iii）指示用于指示修改数据的可能性的数据修改信息; 以及iv）无序信息，用于指示较新的指令在对条目的相应较老指令之前已经完成。本发明还包括一个无序比较器，用于将完成的指令的地址与未命中队列中的任何地址信息条目进行比较。如果完成的指令访问与其他指令相同的地址，如错误队列表中的地址信息中所示，并且完成的指令比匹配的指令更新，则会显示乱序字段，指示此条件存在。本发明包括修改比较器。这将比较从数据更改事件到错误队列表中条目中的那些地址的地址。在比赛中，相应条目的修改字段被标记为表示此条件存在。当指令条目指示对应指令的数据被修改并且指令出现故障时，所有后续指令都被取消。

5. 发明申请

US20080222387A1 Correction of incorrect cache accesses 有权
标题翻译：更正错误的缓存访问
公开(公告)号：US20080222387A1
公开(公告)日：2008-09-11
申请号：US12010512
申请日：2008-01-25
申请人： Barry Duane Williamson , Gerard Richard Williams , Muralidharan Santharaman Chinnakonda
发明人： Barry Duane Williamson , Gerard Richard Williams , Muralidharan Santharaman Chinnakonda
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F12/1054 , Y02D10/13
摘要： The application describes a data processor operable to process data, and comprising: a cache in which a storage location of a data item within said cache is identified by an address, said cache comprising a plurality of storage locations and said data processor comprising a cache directory operable to store a physical address indicator for each storage location comprising stored data; a hash value generator operable to generate a generated hash value from at least some of said bits of said address said generated hash value having fewer bits than said address; a buffer operable to store a plurality of hash values relating to said plurality of storage locations within said cache; wherein in response to a request to access said data item said data processor is operable to compare said generated hash value with at least some of said plurality of hash values stored within said buffer and in response to a match to indicate a indicated storage location of said data item; and said data processor is operable to access one of said physical address indicators stored within said cache directory corresponding to said indicated storage location and in response to said accessed physical address indicator not indicating said address said data processor is operable to invalidate said indicated storage location within said cache.
摘要翻译：应用程序描述可操作以处理数据的数据处理器，并且包括：高速缓存，其中通过地址识别所述高速缓存内的数据项的存储位置，所述高速缓存包括多个存储位置，并且所述数据处理器包括高速缓存目录可操作地存储包括存储的数据的每个存储位置的物理地址指示符; 哈希值发生器，用于从所述地址的所述比特中的至少一些产生生成的散列值，所述哈希值生成的哈希值具有比所述地址少的位; 缓冲器，用于存储与所述高速缓存内的所述多个存储位置相关的多个散列值; 其中响应于访问所述数据项的请求，所述数据处理器可操作以将所生成的散列值与所述缓冲器中存储的所述多个散列值中的至少一些进行比较，并响应于匹配来指示所述数据项的所指示的存储位置数据项; 并且所述数据处理器可操作以访问存储在与所述指示的存储位置相对应的所述高速缓存目录内的所述物理地址指示符之一，并且响应于所述访问的物理地址指示符不指示所述地址，所述数据处理器可操作以使所述指示的存储位置无效说缓存。

6. 发明授权

US08271733B2 Line allocation in multi-level hierarchical data stores 有权
标题翻译：多级分层数据存储中的行分配
公开(公告)号：US08271733B2
公开(公告)日：2012-09-18
申请号：US12458690
申请日：2009-07-20
申请人： Barry Duane Williamson
发明人： Barry Duane Williamson
IPC分类号： G06F13/00
CPC分类号： G06F12/0811 , G06F12/0817 , G06F12/084 , G06F12/12
摘要： A storage apparatus for storing data is disclosed. The storage apparatus comprises: a plurality of stores having storage locations for storing data items, including a level one store and a level two store the storage apparatus having a hierarchy such that in response to an access request for accessing a data item the level one store is accessed and in response to detecting that the item is not stored in the level one store the level two store is accessed. The storage apparatus is configured to store a copy of at least some items in both of the one level one store and the level two store, the storage apparatus comprising a plurality of indicator storage elements associated with a corresponding plurality of storage locations of the level two store, a set value of an indicator stored in one of the indicator storage elements indicating that the corresponding stored data item is also stored in the level one store. The storage apparatus is configured such that in response to a request to allocate a storage location in the level two store, storage locations having a set indicator associated with them are not selected for eviction.
摘要翻译：公开了一种用于存储数据的存储装置。存储装置包括：多个存储器，具有用于存储数据项的存储位置，包括一级存储，二级存储具有层级的存储装置，使得响应于访问数据项的访问请求，第一级存储被访问并且响应于检测到该项目未被存储在一级存储器中，二级存储被访问。存储装置被配置为存储一级存储和二级存储中的至少一些项目的副本，该存储装置包括多个指示符存储元件，其与第二层的对应的多个存储位置相关联存储指示存储在一个指示符存储元素中的指示符，其指示相应的存储数据项也存储在一级存储中。存储装置被配置为使得响应于在二级存储器中分配存储位置的请求，具有与其相关联的设置指示符的存储位置不被选择用于驱逐。

7. 发明申请

US20110016281A1 Line allocation in multi-level hierarchical data stores 有权
标题翻译：多级分层数据存储中的行分配
公开(公告)号：US20110016281A1
公开(公告)日：2011-01-20
申请号：US12458690
申请日：2009-07-20
申请人： Barry Duane Williamson
发明人： Barry Duane Williamson
IPC分类号： G06F12/16 , G06F12/00
CPC分类号： G06F12/0811 , G06F12/0817 , G06F12/084 , G06F12/12
摘要： A storage apparatus for storing data is disclosed. The storage apparatus comprises: a plurality of stores having storage locations for storing data items, including a level one store and a level two store the storage apparatus having a hierarchy such that in response to an access request for accessing a data item the level one store is accessed and in response to detecting that the item is not stored in the level one store the level two store is accessed. The storage apparatus is configured to store a copy of at least some items in both of the one level one store and the level two store, the storage apparatus comprising a plurality of indicator storage elements associated with a corresponding plurality of storage locations of the level two store, a set value of an indicator stored in one of the indicator storage elements indicating that the corresponding stored data item is also stored in the level one store. The storage apparatus is configured such that in response to a request to allocate a storage location in the level two store, storage locations having a set indicator associated with them are not selected for eviction.
摘要翻译：公开了一种用于存储数据的存储装置。存储装置包括：多个存储器，具有用于存储数据项的存储位置，包括一级存储，二级存储具有层级的存储装置，使得响应于访问数据项的访问请求，第一级存储被访问并且响应于检测到该项目未被存储在一级存储器中，二级存储被访问。存储装置被配置为存储一级存储和二级存储中的至少一些项目的副本，该存储装置包括多个指示符存储元件，其与第二层的对应的多个存储位置相关联存储指示存储在一个指示符存储元素中的指示符，其指示相应的存储数据项也存储在一级存储中。存储装置被配置为使得响应于在二级存储器中分配存储位置的请求，具有与其相关联的设置指示符的存储位置不被选择用于驱逐。

8. 发明授权

US6112297A Apparatus and method for processing misaligned load instructions in a processor supporting out of order execution 失效
标题翻译：在处理器中处理不对齐负载指令的装置和方法，该处理器支持无序执行
公开(公告)号：US6112297A
公开(公告)日：2000-08-29
申请号：US21133
申请日：1998-02-10
申请人： David Scott Ray , Barry Duane Williamson , Shih-Hsiung Stephen Tung
发明人： David Scott Ray , Barry Duane Williamson , Shih-Hsiung Stephen Tung
IPC分类号： G06F12/08 , G06F9/312 , G06F9/38
CPC分类号： G06F9/30043 , G06F9/3816
摘要： One aspect of the invention relates to a method for processing load instructions in a superscalar processor having a data cache and a register file. In one embodiment, the method includes the steps of dispatching a misaligned load instruction to access a block of data that is misaligned in the cache; while continuing to dispatch aligned instructions: generating a first access and a final access to the cache in response to the misaligned load instruction; storing data retrieved from the first access until data from the final access is available; reassembling the data from the first and final access into the order required by the load instruction; and storing the re-assembled data to the register file.
摘要翻译：本发明的一个方面涉及一种用于在具有数据高速缓存和寄存器文件的超标量处理器中处理加载指令的方法。在一个实施例中，该方法包括以下步骤：调度未对准加载指令以访问在高速缓存中未对准的数据块; 同时继续调度对准的指令：响应于未对准的加载指令产生对高速缓存的第一访问和最终访问; 存储从第一访问检索的数据，直到来自最终访问的数据可用; 将来自第一次和最后访问的数据重新组装成加载指令所要求的顺序; 并将重新组装的数据存储到寄存器文件中。

9. 发明授权

US6035394A System for providing high performance speculative processing of complex load/store instructions by generating primitive instructions in the load/store unit and sequencer in parallel 失效
标题翻译：用于通过在并行装载/存储单元和定序器中产生原始指令来提供复杂加载/存储指令的高性能推测性处理的系统
公开(公告)号：US6035394A
公开(公告)日：2000-03-07
申请号：US24805
申请日：1998-02-17
申请人： David Scott Ray , Kevin Arthur Chiarot , David Andrew Schroter , A. James Van Norstrand, Jr. , Barry Duane Williamson
发明人： David Scott Ray , Kevin Arthur Chiarot , David Andrew Schroter , A. James Van Norstrand, Jr. , Barry Duane Williamson
IPC分类号： G06F9/30 , G06F9/312 , G06F9/318 , G06F9/38
CPC分类号： G06F9/3824 , G06F9/30043 , G06F9/3017 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： One aspect of the invention relates to a method for operating a superscalar processor having an instruction cache, a sequencing unit, a load/store unit, a cache, an architectural register file and a rename register file. In one particular version of the invention, the method includes the steps of forwarding an instruction from the instruction cache to the sequencing unit operable to access multiple architectural registers; generating a plurality of primitive instructions responsive to the forwarded instruction in which an individual primitive instruction is operable to access an individual architectural register; and sequentially issuing the primitive instructions to move data between the data cache and the rename register file.
摘要翻译：本发明的一个方面涉及一种用于操作具有指令高速缓存，排序单元，加载/存储单元，高速缓存，架构寄存器文件和重命名寄存器文件的超标量处理器的方法。在本发明的一个特定版本中，该方法包括以下步骤：将指令从指令高速缓存转发到可操作以访问多个架构寄存器的排序单元; 响应于转发的指令产生多个原语指令，其中单个原语指令可操作以访问单个体系结构寄存器; 并顺序地发出原始指令以在数据高速缓存和重命名寄存器文件之间移动数据。

10. 发明授权

US5926645A Method and system for enabling multiple store instruction completions in a processing system 失效
标题翻译：用于在处理系统中实现多个存储指令完成的方法和系统
公开(公告)号：US5926645A
公开(公告)日：1999-07-20
申请号：US898359
申请日：1997-07-22
申请人： Barry Duane Williamson
发明人： Barry Duane Williamson
IPC分类号： G06F9/312 , G06F9/38 , G06F9/06 , G06F9/305
CPC分类号： G06F9/30043 , G06F9/3824 , G06F9/3836 , G06F9/384 , G06F9/3857
摘要： A method and system for a handling multiple store instruction completions in a processing system after a stall condition is disclosed. The processing system includes an instruction unit, the instruction unit including a dispatch unit and a completion unit, a translation unit and at least one execution unit. A load store unit comprises an instruction queue for receiving a plurality of instructions from the dispatch unit; at least one effective address (EA) unit for receiving the plurality of instructions from the instruction queue, and a store queue. The store queue is coupled to the translation unit, the at least one execution unit and the at least one EA unit. The store queue receives data and real address information relating to each of the plurality of instructions from the at least one execution unit prior to completion of each of the plurality of instructions. In so doing, the bottleneck associated with conventional systems, i.e., a maximum number of instructions that can be dispatched by the instruction unit is reduced.
摘要翻译：公开了一种在失速状态之后处理系统中处理多个存储指令完成的方法和系统。处理系统包括指令单元，指令单元包括调度单元和完成单元，转换单元和至少一个执行单元。加载存储单元包括用于从调度单元接收多个指令的指令队列; 用于从指令队列接收多个指令的至少一个有效地址（EA）单元和存储队列。存储队列耦合到翻译单元，至少一个执行单元和至少一个EA单元。存储队列在完成多个指令中的每一个之前从至少一个执行单元接收与多个指令中的每一个相关的数据和实地址信息。在这样做时，与传统系统相关联的瓶颈，即可以由指令单元调度的指令的最大数目减少。

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