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1. 发明授权

US06406980B1 Physical design technique providing single and multiple core microprocessor chips in a single design cycle and manufacturing lot using shared mask sets 失效
标题翻译：物理设计技术在单个设计周期中提供单核和多核微处理器芯片，并使用共享掩模集提供制造批次
公开(公告)号：US06406980B1
公开(公告)日：2002-06-18
申请号：US09645155
申请日：2000-08-24
申请人： Matthew J. Amatangelo , Christopher McCall Durham , Peter Juergen Klim , Stephen Larry Runyon
发明人： Matthew J. Amatangelo , Christopher McCall Durham , Peter Juergen Klim , Stephen Larry Runyon
IPC分类号： H01L21301
CPC分类号： H01L27/0207 , H01L27/118
摘要： A wafer design layout and method of producing multiple integrated chip types using a single set of masks for a wafer and then at the time the type of chip desired is known, using a few customizing steps to produce the final integrated chip is provided. In one embodiment, the wafer layout includes a plurality of groupings of components and a plurality of dicing channels separating each of the components from others of the components. After the particular type of integrated circuit chip desired is selected, the wafer may then have the final few layers processed and the chips removed using the appropriate dicing channels for the integrated circuit chip desired.
摘要翻译：提供了使用单个用于晶片的掩模的然后在所期望的芯片类型的时候产生多个集成芯片类型的晶片设计布局和方法，使用几个定制步骤来产生最终的集成芯片。在一个实施例中，晶片布局包括多个组件分组和多个分割通道，每个分组通道将组件中的每一个与其他部件分离。在选择了期望的特定类型的集成电路芯片之后，晶片可以处理最后几个层，并且使用用于集成电路芯片的合适的切割通道去除芯片。

2. 发明授权

US6133758A Selectable self-timed replacement for self-resetting circuitry 失效
标题翻译：自复位电路可选择自定时更换
公开(公告)号：US6133758A
公开(公告)日：2000-10-17
申请号：US86737
申请日：1998-05-29
申请人： Christopher McCall Durham , Peter J. Klim
发明人： Christopher McCall Durham , Peter J. Klim
IPC分类号： G06F9/38 , H03K19/096 , H03K19/00
CPC分类号： H03K19/0966 , G06F9/3869
摘要： A method and apparatus is provided for changing a self-timed circuit into a self-resetting circuit to reduce the inherent delay of the self-timed circuit by an amount of latency between the assertion of the data and the assertion of the valid signal. Circuitry is provided to enable the effective de-coupling of the self-timing operation to enable data to move through the logic circuitry without the latency associated with the reception and generation of "valid" and "complete" signals being necessary. On the "receiving" side (the circuit being set into self-resetting mode), the logic circuit does not have to wait for the reception of the "valid" signals to begin operation. On the "driving" side (the circuit sending the data), the logic circuit does not have to wait for the "completion" signal to arrive to permit a new operation to occur.
摘要翻译：提供了一种方法和装置，用于将自定时电路改变为自复位电路，以便将自定时电路的固有延迟减小在数据的断言和有效信号的断言之间的等待时间量。提供电路以实现自定时操作的有效解耦，使得数据能够通过逻辑电路移动，而不需要与接收相关联的等待时间并产生“有效”和“完整”信号。在“接收”侧（电路被设置为自复位模式）中，逻辑电路不必等待接收“有效”信号开始运行。在“驱动”侧（发送数据的电路）中，逻辑电路不必等待“完成”信号到达以允许发生新的操作。

3. 发明授权

US5896059A Decoupling capacitor fuse system 失效
标题翻译：去耦电容保险丝系统
公开(公告)号：US5896059A
公开(公告)日：1999-04-20
申请号：US854224
申请日：1997-05-09
申请人： Christopher McCall Durham , Peter Juergen Klim
发明人： Christopher McCall Durham , Peter Juergen Klim
IPC分类号： H03K19/003 , H03K3/01
CPC分类号： H03K19/003
摘要： An apparatus to remove from operation a decoupling capacitor connected to a power supply providing power to logic circuitry in an integrated circuit. One technique for doing so is to connect a fuse in series with a decoupling capacitor. The present invention amplifies current transmitting through the fuse in a positive feedback manner to force the fuse to blow sooner than would normally occur. Therefore, when the current through the decoupling capacitor is deemed unacceptable, the fuse current is increased until such a time that the fuse opens.
摘要翻译：一种用于从操作中去除连接到向集成电路中的逻辑电路提供电力的电源的去耦电容器的装置。一种这样做的技术是将保险丝与去耦电容串联。本发明以正反馈方式放大通过保险丝传输的电流，以使熔丝比通常发生的更快地吹动。因此，当通过去耦电容器的电流被认为是不可接受的时候，熔丝电流增加直至熔丝开启的时间为止。

4. 发明授权

US06269045B1 Self-timed address decoder for register file and compare circuit of multi-port cam 失效
标题翻译：多端口凸轮的寄存器文件和比较电路的自定时地址解码器
公开(公告)号：US06269045B1
公开(公告)日：2001-07-31
申请号：US09500348
申请日：2000-02-08
申请人： Christopher McCall Durham , Peter Juergen Klim , Roy Keith Waite
发明人： Christopher McCall Durham , Peter Juergen Klim , Roy Keith Waite
IPC分类号： G11C800
CPC分类号： G11C8/10
摘要： A circuit evaluates a plurality of data inputs, provides for stabilization of the evaluation, and then drives the evaluation from the circuit. The providing of the stabilization is performed by delaying an activation signal, which controls the evaluation circuitry. The activation signal may be either a clock signal or a reset signal. This circuit may be an address decoder that decodes certain ones of the address signals during the evaluation phase, and then drives the evaluation during the second phase.
摘要翻译：电路评估多个数据输入，提供评估的稳定性，然后驱动来自电路的评估。通过延迟控制评估电路的激活信号来执行稳定化的提供。激活信号可以是时钟信号或复位信号。该电路可以是在评估阶段解码某些地址信号的地址解码器，然后在第二阶段期间驱动评估。

5. 发明授权

US06209055B1 Method and apparatus for reducing noise induced among conductive lines 失效
标题翻译：用于降低导线间感应的噪声的方法和装置
公开(公告)号：US06209055B1
公开(公告)日：2001-03-27
申请号：US09182301
申请日：1998-10-29
申请人： Christopher McCall Durham , Peter Juergen Klim , John Andrew Beck
发明人： Christopher McCall Durham , Peter Juergen Klim , John Andrew Beck
IPC分类号： G06F1300
CPC分类号： G11C7/10 , G11C5/063 , G11C7/18
摘要： For transmitting information on a plurality of integrated circuit conductive lines, n conductive lines are provided on a path in an integrated circuit. The path has first and second portions, and an interposing, transition portion. The lines have first positions with respect to one another in the first portion, and certain of the lines change relative positions in the transition portion, so that the lines have second positions with respect to one another in the second portion. The information is encoded in a format wherein no more than one of the n lines has a signal asserted thereon at a time, so that there is a reduction in noise induced among the lines.
摘要翻译：为了在多个集成电路导线上发送信息，在集成电路的路径上设置n条导线。路径具有第一和第二部分，以及插入的过渡部分。这些线在第一部分中具有相对于彼此的第一位置，并且某些线改变了过渡部分中的相对位置，使得线在第二部分中具有彼此相对的第二位置。信息被编码成格式，其中n行中不超过一行具有一次在其上被声明的信号，使得在线之间引起的噪声降低。

6. 发明授权

US06208907B1 Domino to static circuit technique 失效
标题翻译： Domino到静态电路技术
公开(公告)号：US06208907B1
公开(公告)日：2001-03-27
申请号：US09016653
申请日：1998-01-30
申请人： Christopher McCall Durham , Visweswara Rao Kodali , Douglas Ele Martin , Harsh Dev Sharma
发明人： Christopher McCall Durham , Visweswara Rao Kodali , Douglas Ele Martin , Harsh Dev Sharma
IPC分类号： G06F1900
CPC分类号： G06F9/38 , H03K19/0963 , H03K19/1735
摘要： A method and apparatus is provided for enabling the transformation of a domino circuit to a static circuit without requiring the re-design of the chip or integrated circuit mask set. The domino circuit masks may be designed to include additional unconnected devices as appropriate which may be added or connected into the circuit after chip design release by changing only interconnection masks. Spare devices can be added and selectively used to make a domino circuit metal-mask programmable into a logically equivalent static circuit. In a first exemplary method, extra devices are added to, and/or existing devices are re-wired in the domino circuitry to make a complementary equivalent static gate. In a second exemplary methodology, the domino circuit is converted into a pseudo-NMOS circuit using devices already available in the circuit and modifying the circuit connections thereto.
摘要翻译：提供了一种方法和装置，用于使得能够将多米诺骨牌电路转换成静态电路，而不需要重新设计芯片或集成电路掩模组。多米诺骨牌电路掩模可以被设计为包括适当的额外的未连接的设备，其可以通过仅改变互连掩模而在芯片设计释放之后被添加或连接到电路中。备用器件可以添加并选择性地用于使多米诺骨电路金属掩模可编程成逻辑等效的静态电路。在第一示例性方法中，添加额外的设备，和/或将现有设备重新连接在多米诺骨牌电路中以形成互补的等效静态门。在第二示例性方法中，使用电路中已经可用的设备并修改其电路连接，将多米诺骨电路转换成伪NMOS电路。

7. 发明授权

US06181156B2 Noise suppression circuits for suppressing noises above and below reference voltages 失效
标题翻译：用于抑制高于和低于参考电压的噪声的噪声抑制电路
公开(公告)号：US06181156B2
公开(公告)日：2001-01-30
申请号：US09282269
申请日：1999-03-31
申请人： Christopher McCall Durham , Peter Juergen Klim
发明人： Christopher McCall Durham , Peter Juergen Klim
IPC分类号： H03K1716
CPC分类号： H03K17/223 , H03K3/356008 , H03K5/1252 , H03K19/00361 , H04L25/08
摘要： A noise suppression circuit for suppressing noises above and below reference voltages is disclosed. The noise suppression circuit for suppressing noises includes a means for generating a power-on-reset signal, a clamping transistor, and a feedback circuit. The means for generating a power-on-reset signal presets an internal latch of the noise suppression circuit to a predetermined state, such as a logical high state. The clamping transistor restores the state of a data input of a circuit to which the noise suppression circuit is providing protection, after the occurrence of a noise coupling event. The feedback circuit then turns off the clamping transistor after a predetermined amount of time.
摘要翻译：公开了一种用于抑制高于和低于参考电压的噪声的噪声抑制电路。用于抑制噪声的噪声抑制电路包括用于产生上电复位信号的装置，钳位晶体管和反馈电路。用于产生上电复位信号的装置将噪声抑制电路的内部锁存器预设为诸如逻辑高状态的预定状态。在发生噪声耦合事件之后，钳位晶体管恢复噪声抑制电路提供保护的电路的数据输入的状态。然后，反馈电路在预定的时间量之后关断钳位晶体管。

8. 发明授权

US6072746A Self-timed address decoder for register file and compare circuit of a multi-port CAM 失效
标题翻译：用于多端口CAM的寄存器文件和比较电路的自定时地址解码器
公开(公告)号：US6072746A
公开(公告)日：2000-06-06
申请号：US134339
申请日：1998-08-14
申请人： Christopher McCall Durham , Peter Juergen Klim , Roy Keith Waite
发明人： Christopher McCall Durham , Peter Juergen Klim , Roy Keith Waite
IPC分类号： G11C8/10 , G11C8/00
CPC分类号： G11C8/10
摘要： A circuit evaluates a plurality of data inputs, provides for stabilization of the evaluation, and then drives the evaluation from the circuit. The providing of the stabilization is performed by delaying an activation signal, which controls the evaluation circuitry. The activation signal may be either a clock signal or a reset signal. This circuit may be an address decoder that decodes certain ones of the address signals during the evaluation phase, and then drives the evaluation during the second phase.
摘要翻译：电路评估多个数据输入，提供评估的稳定性，然后驱动来自电路的评估。通过延迟控制评估电路的激活信号来执行稳定化的提供。激活信号可以是时钟信号或复位信号。该电路可以是在评估阶段解码某些地址信号的地址解码器，然后在第二阶段期间驱动评估。

9. 发明授权

US6037804A Reduced power dynamic logic circuit that inhibits reevaluation of stable inputs 失效
标题翻译：减少功率动态逻辑电路，抑制稳定输入的重新评估
公开(公告)号：US6037804A
公开(公告)日：2000-03-14
申请号：US049741
申请日：1998-03-27
申请人： Christopher McCall Durham , Visweswara Rao Kodali , Michael Ju Hyeok Lee , Douglas Ele Martin , Harsh Dev Sharma
发明人： Christopher McCall Durham , Visweswara Rao Kodali , Michael Ju Hyeok Lee , Douglas Ele Martin , Harsh Dev Sharma
IPC分类号： H03K19/00 , H03K19/096 , H03K19/094
CPC分类号： H03K19/096 , H03K19/0016
摘要： A reduced-power integrated circuit includes a circuit data input, a circuit data output, and at least one row of dynamic logic. The row of dynamic logic includes a row clock input, a row data input, and a row data output coupled to the circuit data output, where a value received at the row data input is derived from the value at the circuit data input. The integrated circuit further includes a comparator that compares current and previous values at the circuit data input and a switch that selectively sets the row clock signal received at the row clock input to an inactive state and temporarily maintains the row clock signal in the inactive state in response to the comparator detecting that the current previous values of at the circuit data input are equivalent. Consequently, the row of dynamic logic does not (and need not) reevaluate the circuit data input value, and power dissipation is reduced.
摘要翻译：降低功率的集成电路包括电路数据输入，电路数据输出和至少一行动态逻辑。动态逻辑行包括行时钟输入，行数据输入和耦合到电路数据输出的行数据输出，其中根据电路数据输入的值导出在行数据输入处接收的值。集成电路还包括比较器，其比较电路数据输入端的当前值和先前值，以及开关，其选择性地将在行时钟输入处接收的行时钟信号设置为非活动状态，并将行时钟信号暂时保持在非活动状态对比较器的响应检测到电路数据输入端的当前先前值是等效的。因此，动态逻辑行（并不需要）重新评估电路数据输入值，并降低功耗。

10. 发明授权

US5912900A Method and system for testing self-timed circuitry 失效
标题翻译：用于测试自定时电路的方法和系统
公开(公告)号：US5912900A
公开(公告)日：1999-06-15
申请号：US767244
申请日：1996-12-13
申请人： Christopher McCall Durham , Peter Juergen Klim , Srinivas Patil
发明人： Christopher McCall Durham , Peter Juergen Klim , Srinivas Patil
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318536
摘要： From a first circuit, information is output in response to acknowledgement signals. From a second circuit, the acknowledgement signals are output in response to the second circuit receiving portions of the information from the first circuit. The portions and the acknowledgement signals are output asynchronously with respect to one another. With at least one of the first and second circuits, a signal having a logic state is received, the logic state is latched, and an operation is performed in response to the latched logic state.
摘要翻译：从第一电路，响应于确认信号输出信息。响应于第二电路接收来自第一电路的信息的部分，从第二电路输出确认信号。部分和确认信号相对于彼此异步地输出。利用第一和第二电路中的至少一个，接收到具有逻辑状态的信号，锁存逻辑状态，并且响应于锁存的逻辑状态执行操作。

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