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41. 发明申请

US20120153910A1 DUAL-LOOP VOLTAGE REGULATOR ARCHITECTURE WITH HIGH DC ACCURACY AND FAST RESPONSE TIME 有权
标题翻译：具有高直流精度和快速响应时间的双环电压调节器架构
公开(公告)号：US20120153910A1
公开(公告)日：2012-06-21
申请号：US13213578
申请日：2011-08-19
申请人： John F. Bulzacchelli , Carrie E. Cox , Zeynep Toprak-Deniz , Daniel J. Friedman , Joseph A. Iadanza , Todd M. Rasmus
发明人： John F. Bulzacchelli , Carrie E. Cox , Zeynep Toprak-Deniz , Daniel J. Friedman , Joseph A. Iadanza , Todd M. Rasmus
IPC分类号： G05F1/10
CPC分类号： G05F1/575
摘要： Dual-loop voltage regulator circuits and methods in which a dual-loop voltage regulation framework is implemented with a first inner loop having a bang-bang voltage regulator to achieve nearly instantaneous response time, and a second outer loop, which is slower in operating speed than the first inner loop, to controllably adjust a trip point of the bang-bang voltage regulator to achieve high DC accuracy.
摘要翻译：双环路电压调节器电路和方法，其中使用具有爆轰电压调节器的第一内环实现双回路电压调节框架以实现几乎瞬时的响应时间，以及第二外环，其操作速度较慢比第一个内环，可控地调节砰砰电压调节器的跳闸点，以实现高直流精度。

42. 发明授权

US07932641B2 Low voltage head room detection for reliable start-up of self-biased analog circuits 有权
标题翻译：低电压头部房间检测可靠启动自偏置模拟电路
公开(公告)号：US07932641B2
公开(公告)日：2011-04-26
申请号：US11760856
申请日：2007-06-11
申请人： Bradford L. Hunter , Joseph A. Iadanza
发明人： Bradford L. Hunter , Joseph A. Iadanza
IPC分类号： H02J1/00
CPC分类号： H02H11/006 , Y10S323/901 , Y10T307/729 , Y10T307/832 , Y10T307/858
摘要： A method and structure for preventing operation of a circuit in a high current operating region by disabling a start-up circuit until a power supply headroom is detected at a predetermined voltage level.
摘要翻译：一种用于通过禁用启动电路直到在预定电压电平检测到电源余量来防止电路在高电流操作区域中的操作的方法和结构。

43. 发明授权

US07932552B2 Multiple source-single drain field effect semiconductor device and circuit 有权
标题翻译：多源单漏极场效应半导体器件和电路
公开(公告)号：US07932552B2
公开(公告)日：2011-04-26
申请号：US11833538
申请日：2007-08-03
申请人： Wagdi W. Abadeer , Anthony R. Bonaccio , Joseph A. Iadanza
发明人： Wagdi W. Abadeer , Anthony R. Bonaccio , Joseph A. Iadanza
IPC分类号： H01L29/66
CPC分类号： H01L27/0705 , H01L21/823418
摘要： Disclosed are embodiments of a variable-delay field effect transistor (FET) having multiple source regions that can be individually and selectively biased to provide an electrical connection to a single drain region. Delay is a function of which of the multiple source regions is/are selectively biased as well as a function of gate resistance and capacitance. Such a variable-delay FET can be incorporated into a phase adjusting circuit, which uses gate propagation delays to selectively phase adjust an input signal. The phase adjusting circuit can be tuned by incorporating non-salicided resistances and additional capacitance at various positions on the gate structure. The phase adjusting circuit can further be modified into a phase adjusting mixer circuit that enables a phase adjusted signal to be combined with an additional signal.
摘要翻译：公开了具有多个源极区域的可变延迟场效应晶体管（FET）的实施例，其可被单独和选择性地偏置以提供到单个漏极区域的电连接。延迟是多个源极区域中的哪一个被选择性偏置以及栅极电阻和电容的函数的函数。这样的可变延迟FET可以并入相位调整电路中，该相位调整电路使用栅极传播延迟来选择性地相位调整输入信号。相位调整电路可以通过在栅极结构上的各个位置并入非水银电阻和附加电容来调节。相位调整电路可以进一步修改为使相位调整信号与附加信号组合的相位调整混频器电路。

44. 发明授权

US07795940B2 Micro-phase adjusting and micro-phase adjusting mixer circuits designed with standard field effect transistor structures 失效
标题翻译：微相调节和微相调谐混频器电路采用标准场效应晶体管结构设计
公开(公告)号：US07795940B2
公开(公告)日：2010-09-14
申请号：US12573910
申请日：2009-10-06
申请人： Wagdi W. Abadeer , Anthony R. Bonaccio , Joseph A. Iadanza
发明人： Wagdi W. Abadeer , Anthony R. Bonaccio , Joseph A. Iadanza
IPC分类号： H03K3/00 , H03H11/16 , H03K5/13
CPC分类号： H03K5/06 , H03K2005/00052 , H03K2005/00058
摘要： Disclosed herein are embodiments of a programmable phase adjusting circuit, a programmable phase adjusting mixer circuit and design structures for these circuits. These circuits comprise a variable delay device connected between input and output nodes. The device includes multiple FETs with input diffusion regions that are connected to a voltage rail via switches so that they can be selectively biased, gates that are connected in series to the input node so that a periodic input signal can be propagated sequentially through each of the gates and output diffusion regions that are connected in parallel to the output node. A current source is connected between the output node and another voltage rail for biasing the output node when the variable delay device is off. The variable delay device enables a circuit in which small increments of selectable phase adjustments can be made to the periodic input signal as a function of propagation delay.
摘要翻译：这里公开了可编程相位调整电路，可编程相位调整混频器电路和这些电路的设计结构的实施例。这些电路包括连接在输入和输出节点之间的可变延迟器件。该器件包括多个FET，其输入扩散区通过开关连接到电压轨，使得它们可以被选择性偏置，与输入节点串联连接的栅极，使得周期性输入信号可以顺序地传播通过门和输出扩散区域并联连接到输出节点。当可变延迟装置关闭时，电流源连接在输出节点和另一个电压轨道之间，用于偏置输出节点。可变延迟装置使得能够作为传播延迟的函数对周期性输入信号进行可选相位调整的小增量的电路。

45. 发明申请

US20080273373A1 APPARATUS FOR IMPROVED SRAM DEVICE PERFORMANCE THROUGH DOUBLE GATE TOPOLOGY 有权
标题翻译：通过双门拓扑改进SRAM设备性能的设备
公开(公告)号：US20080273373A1
公开(公告)日：2008-11-06
申请号：US12146554
申请日：2008-06-26
申请人： George M. Braceras , Wilfried E. A. Haensch , Joseph A. Iadanza
发明人： George M. Braceras , Wilfried E. A. Haensch , Joseph A. Iadanza
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A static random access memory (SRAM) device a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data, a first pair of transfer gates configured to couple complementary internal nodes of the storage cell to a corresponding pair of bitlines during a read operation of the device; and a second pair of transfer gates configured to couple the storage cell nodes to the pair of bitlines during a write operation of the device, wherein impedance between the bitlines and the storage cell nodes during the write operation is less than that for the read operation, wherein impedance between the bitlines and the storage cell nodes during the write operation is less than that for the read operation.
摘要翻译：一种静态随机存取存储器（SRAM）装置，被配置为用于数据位的存储单元的一对交叉耦合的互补金属氧化物半导体（CMOS）反相器，第一对传输门，被配置为耦合所述存储器的互补的内部节点在设备的读取操作期间，单元到相应的位线对; 以及第二对传输门，其被配置为在所述器件的写入操作期间将所述存储单元节点耦合到所述一对位线，其中在所述写入操作期间所述位线和所述存储单元节点之间的阻抗小于所述读操作的阻抗，其中在写入操作期间位线和存储单元节点之间的阻抗小于读取操作的阻抗。

46. 发明授权

US07408800B1 Apparatus and method for improved SRAM device performance through double gate topology 有权
标题翻译：通过双栅拓扑改善SRAM器件性能的装置和方法
公开(公告)号：US07408800B1
公开(公告)日：2008-08-05
申请号：US11743686
申请日：2007-05-03
申请人： George M. Braceras , Wilfried E. A. Haensch , Joseph A. Iadanza
发明人： George M. Braceras , Wilfried E. A. Haensch , Joseph A. Iadanza
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A static random access memory (SRAM) device a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data, a first pair of transfer gates configured to couple complementary internal nodes of the storage cell to a corresponding pair of bitlines during a read operation of the device; and a second pair of transfer gates configured to couple the storage cell nodes to the pair of bitlines during a write operation of the device, wherein impedance between the bitlines and the storage cell nodes during the write operation is less than that for the read operation, wherein impedance between the bitlines and the storage cell nodes during the write operation is less than that for the read operation.
摘要翻译：一种静态随机存取存储器（SRAM）装置，被配置为用于数据位的存储单元的一对交叉耦合的互补金属氧化物半导体（CMOS）反相器，第一对传输门，被配置为耦合所述存储器的互补的内部节点在设备的读取操作期间，单元到相应的位线对; 以及第二对传输门，其被配置为在所述器件的写入操作期间将所述存储单元节点耦合到所述一对位线，其中在所述写入操作期间所述位线和所述存储单元节点之间的阻抗小于所述读操作的阻抗，其中在写入操作期间位线和存储单元节点之间的阻抗小于读取操作的阻抗。

47. 发明授权

US07307467B2 Structure and method for implementing oxide leakage based voltage divider network for integrated circuit devices 有权
标题翻译：用于集成电路器件实现基于氧化物泄漏的分压网络的结构和方法
公开(公告)号：US07307467B2
公开(公告)日：2007-12-11
申请号：US11380799
申请日：2006-04-28
申请人： Kenneth J. Goodnow , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout
发明人： Kenneth J. Goodnow , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H01L29/42384 , H01L21/823842 , H01L21/823857 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/785 , H01L29/78645 , H01L29/78648
摘要： A voltage divider device includes a double gate field effect transistor (FET) having a first gate and a second gate disposed at opposite sides of a body region. An input voltage is coupled between the first and second gates, and an output voltage is taken from at least one of a source of the FET and a drain of the FET, wherein the output voltage represents a divided voltage with respect to the input voltage.
摘要翻译：分压器装置包括具有第一栅极的双栅场效应晶体管（FET）和设置在体区相对侧的第二栅极。输入电压耦合在第一和第二栅极之间，并且输出电压取自FET的源极和FET的漏极中的至少一个，其中输出电压表示相对于输入电压的分压。

48. 发明授权

US06298458B1 System and method for manufacturing test of a physical layer transceiver 失效
标题翻译：物理层收发器的制造和测试方法
公开(公告)号：US06298458B1
公开(公告)日：2001-10-02
申请号：US09225111
申请日：1999-01-04
申请人： Hayden C. Cranford, Jr. , Eirik Gude , Joseph A. Iadanza , Paul A. Owczarski , Jonathan H. Raymond
发明人： Hayden C. Cranford, Jr. , Eirik Gude , Joseph A. Iadanza , Paul A. Owczarski , Jonathan H. Raymond
IPC分类号： G01R3128
CPC分类号： H04L43/50 , G01R31/2884 , H04B17/10 , H04B17/20
摘要： A system and method for testing the most complex portions of transceiver devices integrated into digital VLSI chips. The testing is performed in a manufacturing environment with minimal external hardware and using a combination of test-specific circuitry and pattern algorithms built into a mixed signal transceiver implementing a test methodology suitable for application and measurement on a digital tester.
摘要翻译：用于测试集成到数字VLSI芯片中的收发器设备的最复杂部分的系统和方法。该测试在具有最小外部硬件的制造环境中进行，并且使用内置于混合信号收发器中的测试专用电路和模式算法的组合来实现适用于数字测试仪上的应用和测量的测试方法。

49. 发明授权

US08643987B2 Current leakage in RC ESD clamps 有权
标题翻译： RC ESD钳位电流泄漏
公开(公告)号：US08643987B2
公开(公告)日：2014-02-04
申请号：US13464131
申请日：2012-05-04
申请人： Albert M. Chu , Joseph A. Iadanza , Mujahid Muhammad , Daryl M. Seitzer , Rohit Shetty , Jane S. Tu
发明人： Albert M. Chu , Joseph A. Iadanza , Mujahid Muhammad , Daryl M. Seitzer , Rohit Shetty , Jane S. Tu
IPC分类号： H02H9/00 , H02H3/20 , H02H9/04 , H02H3/22
CPC分类号： H02H9/046
摘要： Aspects of the invention provide an electrostatic discharge (ESD) protection device for eliminating current leakage, and a related method. In one embodiment, an ESD protection device includes: a resistor-capacitor (RC) circuit for receiving a power supply voltage; an ESD clamp including a plurality of n-type field-effect transistors (nFETs) for protecting the IC during an ESD event; a trigger circuit for receiving an output of the RC circuit and generating a trigger pulse to turn on the ESD clamp during the ESD event; and an nFET bias selection circuit connected to the trigger circuit, the nFET bias selection circuit for selecting one of: a low voltage supply or a negative bias voltage supply for the trigger circuit, such that the trigger circuit generates a trigger pulse, in response to selecting the negative bias voltage supply, to turn off the ESD clamp during normal operation.
摘要翻译：本发明提供一种用于消除电流泄漏的静电放电（ESD）保护装置及相关方法。在一个实施例中，ESD保护装置包括：用于接收电源电压的电阻器 - 电容器（RC）电路; 包括用于在ESD事件期间保护IC的多个n型场效应晶体管（nFET）的ESD钳位; 触发电路，用于接收RC电路的输出并产生触发脉冲以在ESD事件期间导通ESD钳位; 以及连接到触发电路的nFET偏置选择电路，nFET偏置选择电路，用于选择触发电路的低电压电源或负偏置电压源，使得触发电路响应于触发电路产生触发脉冲选择负偏压电源，在正常工作期间关闭ESD钳位。

50. 发明申请

US20130293991A1 CURRENT LEAKAGE IN RC ESD CLAMPS 有权
标题翻译： RC ESD CLAMP中的电流泄漏
公开(公告)号：US20130293991A1
公开(公告)日：2013-11-07
申请号：US13464131
申请日：2012-05-04
申请人： Albert M. Chu , Joseph A. Iadanza , Mujahid Muhammad , Daryl M. Seitzer , Rohit Shetty , Jane S. Tu
发明人： Albert M. Chu , Joseph A. Iadanza , Mujahid Muhammad , Daryl M. Seitzer , Rohit Shetty , Jane S. Tu
IPC分类号： H02H9/04 , H01L27/06
CPC分类号： H02H9/046
摘要： Aspects of the invention provide an electrostatic discharge (ESD) protection device for eliminating current leakage, and a related method. In one embodiment, an ESD protection device includes: a resistor-capacitor (RC) circuit for receiving a power supply voltage; an ESD clamp including a plurality of n-type field-effect transistors (nFETs) for protecting the IC during an ESD event; a trigger circuit for receiving an output of the RC circuit and generating a trigger pulse to turn on the ESD clamp during the ESD event; and an nFET bias selection circuit connected to the trigger circuit, the nFET bias selection circuit for selecting one of: a low voltage supply or a negative bias voltage supply for the trigger circuit, such that the trigger circuit generates a trigger pulse, in response to selecting the negative bias voltage supply, to turn off the ESD clamp during normal operation.
摘要翻译：本发明提供一种用于消除电流泄漏的静电放电（ESD）保护装置及相关方法。在一个实施例中，ESD保护装置包括：用于接收电源电压的电阻器 - 电容器（RC）电路; 包括用于在ESD事件期间保护IC的多个n型场效应晶体管（nFET）的ESD钳位; 触发电路，用于接收RC电路的输出并产生触发脉冲以在ESD事件期间导通ESD钳位; 以及连接到触发电路的nFET偏置选择电路，nFET偏置选择电路，用于选择触发电路的低电压电源或负偏置电压源，使得触发电路响应于触发电路产生触发脉冲选择负偏压电源，在正常工作期间关闭ESD钳位。

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