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1. 发明申请

US20080157858A1 DESIGN STRUCTURE FOR IMPLEMENTING OXIDE LEAKAGE BASED VOLTAGE DIVIDER NETWORK FOR INTEGRATED CIRCUIT DEVICES 失效
标题翻译：用于集成电路设备实现基于氧化物泄漏的电压分压网络的设计结构
公开(公告)号：US20080157858A1
公开(公告)日：2008-07-03
申请号：US11872743
申请日：2007-10-16
申请人： Kenneth J. Goodnow , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout
发明人： Kenneth J. Goodnow , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H03K17/687 , H03K2017/6878
摘要： A design structure embodied in a machine readable medium used in a design process includes a voltage divider device, including a double gate field effect transistor (FET) having a first gate and a second gate disposed at opposite sides of a body region; the first and second gates configured to have an input voltage coupled thereacross; and at least one of a source of the FET and a drain of the FET configured to have an output voltage taken therefrom; wherein the output voltage represents a divided voltage with respect to the input voltage.
摘要翻译：体现在设计过程中使用的机器可读介质中的设计结构包括分压器件，其包括具有第一栅极的双栅场效应晶体管（FET）和设置在体区相对侧的第二栅极; 所述第一和第二栅极配置成具有耦合到其上的输入电压; 并且所述FET的源极和所述FET的漏极中的至少一个被配置为具有从其获取的输出电压; 其中输出电压表示相对于输入电压的分压。

2. 发明授权

US07579897B2 Design structure for implementing oxide leakage based voltage divider network for integrated circuit devices 失效
标题翻译：用于集成电路器件实现基于氧化物泄漏的分压网络的设计结构
公开(公告)号：US07579897B2
公开(公告)日：2009-08-25
申请号：US11872743
申请日：2007-10-16
申请人： Kenneth J. Goodnow , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout
发明人： Kenneth J. Goodnow , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout
IPC分类号： H03K17/687
CPC分类号： H03K17/687 , H03K2017/6878
摘要： A design structure embodied in a machine readable medium used in a design process includes a voltage divider device, including a double gate field effect transistor (FET) having a first gate and a second gate disposed at opposite sides of a body region; the first and second gates configured to have an input voltage coupled thereacross; and at least one of a source of the FET and a drain of the FET configured to have an output voltage taken therefrom; wherein the output voltage represents a divided voltage with respect to the input voltage.
摘要翻译：体现在设计过程中使用的机器可读介质中的设计结构包括分压器件，其包括具有第一栅极的双栅场效应晶体管（FET）和设置在体区相对侧的第二栅极; 所述第一和第二栅极配置成具有耦合到其上的输入电压; 并且所述FET的源极和所述FET的漏极中的至少一个被配置为具有从其获取的输出电压; 其中输出电压表示相对于输入电压的分压。

3. 发明授权

US07307467B2 Structure and method for implementing oxide leakage based voltage divider network for integrated circuit devices 有权
标题翻译：用于集成电路器件实现基于氧化物泄漏的分压网络的结构和方法
公开(公告)号：US07307467B2
公开(公告)日：2007-12-11
申请号：US11380799
申请日：2006-04-28
申请人： Kenneth J. Goodnow , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout
发明人： Kenneth J. Goodnow , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H01L29/42384 , H01L21/823842 , H01L21/823857 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/785 , H01L29/78645 , H01L29/78648
摘要： A voltage divider device includes a double gate field effect transistor (FET) having a first gate and a second gate disposed at opposite sides of a body region. An input voltage is coupled between the first and second gates, and an output voltage is taken from at least one of a source of the FET and a drain of the FET, wherein the output voltage represents a divided voltage with respect to the input voltage.
摘要翻译：分压器装置包括具有第一栅极的双栅场效应晶体管（FET）和设置在体区相对侧的第二栅极。输入电压耦合在第一和第二栅极之间，并且输出电压取自FET的源极和FET的漏极中的至少一个，其中输出电压表示相对于输入电压的分压。

4. 发明申请

US20090108320A1 TUNABLE CAPACITOR 有权
标题翻译： TUNABLE电容器
公开(公告)号：US20090108320A1
公开(公告)日：2009-04-30
申请号：US11923864
申请日：2007-10-25
申请人： Corey K. Barrows , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout , Mark S. Styduhar
发明人： Corey K. Barrows , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout , Mark S. Styduhar
IPC分类号： H01L29/94
CPC分类号： H01L29/94
摘要： Disclosed are embodiments of a design structure transistor that operates as a capacitor and an associated method of tuning capacitance within such a capacitor. The embodiments of the capacitor comprise a field effect transistor with front and back gates above and below a semiconductor layer, respectively. The capacitance value exhibited by the capacitor can be selectively varied between two different values by changing the voltage condition in a source/drain region of the transistor, e.g., using a switch or resistor between the source/drain region and a voltage supply. Alternatively, the capacitance value exhibited by the capacitor can be selectively varied between multiple different values by changing voltage conditions in one or more of multiple channel regions that are flanked by multiple source/drain regions within the transistor. The capacitor will exhibit different capacitance values depending upon the conductivity in each of the channel regions.
摘要翻译：公开了作为电容器操作的设计结构晶体管的实施例以及在这种电容器内调谐电容的相关方法。电容器的实施例包括分别在半导体层上方和下方具有前栅极和后栅极的场效应晶体管。通过改变晶体管的源极/漏极区域中的电压条件，例如使用源极/漏极区域和电压源之间的开关或电阻器，可以通过改变晶体管的源极/ 或者，可以通过改变在晶体管内侧面有多个源极/漏极区域的多个沟道区域中的一个或多个中的电压条件来选择性地在多个不同值之间变化由电容器呈现的电容值。根据每个通道区域中的电导率，电容器将呈现不同的电容值。

5. 发明申请

US20090101940A1 DUAL GATE FET STRUCTURES FOR FLEXIBLE GATE ARRAY DESIGN METHODOLOGIES 审中-公开
标题翻译：用于柔性门阵列设计方法的双门FET结构
公开(公告)号：US20090101940A1
公开(公告)日：2009-04-23
申请号：US11874957
申请日：2007-10-19
申请人： Corey K. Barrows , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout
发明人： Corey K. Barrows , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout
IPC分类号： H01L29/76 , H01L21/82 , G06F17/50
CPC分类号： H03K19/1778 , H01L29/785 , H01L29/78648
摘要： A gate array cell adapted for standard cell design methodology or programmable gate array that incorporates a dual gate FET device to offer a range of performance options within the same unit cell area. The conductivity and drive strength of the dual gate device may be selectively tuned through independent processing of manufacturing parameters to provide an asymmetric circuit response for the device or a symmetric response as dictated by the circuit application.
摘要翻译：适用于标准单元设计方法的门阵列单元或包括双栅极FET器件的可编程门阵列，以在相同单元单元区域内提供一系列性能选项。可以通过制造参数的独立处理来选择性地调节双栅极器件的导电性和驱动强度，以为器件提供不对称电路响应或由电路应用所指示的对称响应。

6. 发明申请

US20080111176A1 TUNABLE CAPACITOR 有权
标题翻译： TUNABLE电容器
公开(公告)号：US20080111176A1
公开(公告)日：2008-05-15
申请号：US11560126
申请日：2006-11-15
申请人： Corey K. Barrows , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout , Mark S. Styduhar
发明人： Corey K. Barrows , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout , Mark S. Styduhar
IPC分类号： H01L29/93
CPC分类号： H01L29/94
摘要： Disclosed are embodiments of a transistor that operates as a capacitor and an associated method of tuning capacitance within such a capacitor. The embodiments of the capacitor comprise a field effect transistor with front and back gates above and below a semiconductor layer, respectively. The capacitance value exhibited by the capacitor can be selectively varied between two different values by changing the voltage condition in a source/drain region of the transistor, e.g., using a switch or resistor between the source/drain region and a voltage supply. Alternatively, the capacitance value exhibited by the capacitor can be selectively varied between multiple different values by changing voltage conditions in one or more of multiple channel regions that are flanked by multiple source/drain regions within the transistor. The capacitor will exhibit different capacitance values depending upon the conductivity in each of the channel regions.
摘要翻译：公开了用作电容器的晶体管的实施例以及在这种电容器内调谐电容的相关联的方法。电容器的实施例包括分别在半导体层上方和下方具有前栅极和后栅极的场效应晶体管。通过改变晶体管的源极/漏极区域中的电压条件，例如使用源极/漏极区域和电压源之间的开关或电阻器，可以通过改变晶体管的源极/ 或者，可以通过改变在晶体管内侧面有多个源极/漏极区域的多个沟道区域中的一个或多个中的电压条件来选择性地在多个不同值之间变化由电容器呈现的电容值。根据每个通道区域中的电导率，电容器将呈现不同的电容值。

7. 发明授权

US09070791B2 Tunable capacitor 有权
标题翻译：可调谐电容
公开(公告)号：US09070791B2
公开(公告)日：2015-06-30
申请号：US11923864
申请日：2007-10-25
申请人： Corey K. Barrows , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout , Mark S. Styduhar
发明人： Corey K. Barrows , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout , Mark S. Styduhar
IPC分类号： H01L29/94
CPC分类号： H01L29/94
摘要： Disclosed are embodiments of a design structure transistor that operates as a capacitor and an associated method of tuning capacitance within such a capacitor. The embodiments of the capacitor comprise a field effect transistor with front and back gates above and below a semiconductor layer, respectively. The capacitance value exhibited by the capacitor can be selectively varied between two different values by changing the voltage condition in a source/drain region of the transistor, e.g., using a switch or resistor between the source/drain region and a voltage supply. Alternatively, the capacitance value exhibited by the capacitor can be selectively varied between multiple different values by changing voltage conditions in one or more of multiple channel regions that are flanked by multiple source/drain regions within the transistor. The capacitor will exhibit different capacitance values depending upon the conductivity in each of the channel regions.
摘要翻译：公开了作为电容器操作的设计结构晶体管的实施例以及在这种电容器内调谐电容的相关方法。电容器的实施例包括分别在半导体层上方和下方具有前栅极和后栅极的场效应晶体管。通过改变晶体管的源极/漏极区域中的电压条件，例如使用源极/漏极区域和电压源之间的开关或电阻器，可以通过改变晶体管的源极/漏极区域中的电压条件来选择性地在两个不同的值之间改变电容器所呈现的电容值。或者，可以通过改变在晶体管内侧面有多个源极/漏极区域的多个沟道区域中的一个或多个中的电压条件来选择性地在多个不同值之间变化由电容器呈现的电容值。根据每个通道区域中的电导率，电容器将呈现不同的电容值。

8. 发明授权

US07821053B2 Tunable capacitor 有权
标题翻译：可调谐电容
公开(公告)号：US07821053B2
公开(公告)日：2010-10-26
申请号：US11560126
申请日：2006-11-15
申请人： Corey K. Barrows , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout , Mark S. Styduhar
发明人： Corey K. Barrows , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout , Mark S. Styduhar
IPC分类号： H01L29/93
CPC分类号： H01L29/94
摘要： Disclosed are embodiments of a transistor that operates as a capacitor and an associated method of tuning capacitance within such a capacitor. The embodiments of the capacitor comprise a field effect transistor with front and back gates above and below a semiconductor layer, respectively. The capacitance value exhibited by the capacitor can be selectively varied between two different values by changing the voltage condition in a source/drain region of the transistor, e.g., using a switch or resistor between the source/drain region and a voltage supply. Alternatively, the capacitance value exhibited by the capacitor can be selectively varied between multiple different values by changing voltage conditions in one or more of multiple channel regions that are flanked by multiple source/drain regions within the transistor. The capacitor will exhibit different capacitance values depending upon the conductivity in each of the channel regions.
摘要翻译：公开了用作电容器的晶体管的实施例以及在这种电容器内调谐电容的相关联的方法。电容器的实施例包括分别在半导体层上方和下方具有前栅极和后栅极的场效应晶体管。通过改变晶体管的源极/漏极区域中的电压条件，例如使用源极/漏极区域和电压源之间的开关或电阻器，可以通过改变晶体管的源极/ 或者，可以通过改变在晶体管内侧面有多个源极/漏极区域的多个沟道区域中的一个或多个中的电压条件来选择性地在多个不同值之间变化由电容器呈现的电容值。根据每个通道区域中的电导率，电容器将呈现不同的电容值。

9. 发明授权

US06577178B1 Transient gate tunneling current control 有权
标题翻译：瞬态栅极隧道电流控制
公开(公告)号：US06577178B1
公开(公告)日：2003-06-10
申请号：US10064504
申请日：2002-07-23
申请人： Kerry Bernstein , Peter E. Cottrell , Edward J. Nowak , Norman J. Rohrer , Douglas W. Stout
发明人： Kerry Bernstein , Peter E. Cottrell , Edward J. Nowak , Norman J. Rohrer , Douglas W. Stout
IPC分类号： H03K1730
CPC分类号： H03K19/00361 , H03K19/0948
摘要： A circuit includes a resistance-capacitance (RC) structure connected to a first set of transistors and a second set of transistors that perform the same logical function as the first set of transistors. The first set of transistors have thinner gate oxides than the second set of transistors. The RC structure drains an electric field from the first set of transistors, such that the first set of transistors are on only during initial transistor switching. In other words, the RC structure turns off the first set of transistors after transistor switching is completed. Also, the first set of transistors and the second set of transistors share common inputs and outputs. The first set of transistors exhibit higher tunneling currents than the second set of transistors. The thinner gate oxides of the first set of transistors cause the first set of transistors to exhibit higher device currents than the second set of transistors. The RC structure includes a capacitor connected to a gate of the first set of transistors and a resistor connected to the capacitor and to ground.
摘要翻译：电路包括连接到第一组晶体管的电阻 - 电容（RC）结构和执行与第一组晶体管相同的逻辑功能的第二组晶体管。第一组晶体管具有比第二组晶体管更薄的栅极氧化物。 RC结构从第一组晶体管引出电场，使得第一组晶体管仅在初始晶体管切换期间导通。换句话说，在晶体管切换完成之后，RC结构关闭第一组晶体管。此外，第一组晶体管和第二组晶体管共享公共输入和输出。第一组晶体管表现出比第二组晶体管更高的隧穿电流。第一组晶体管的较薄的栅极氧化物导致第一组晶体管表现出比第二组晶体管更高的器件电流。 RC结构包括连接到第一组晶体管的栅极的电容器和连接到电容器并接地的电阻器。

10. 发明授权

US09368410B2 Semiconductor devices having tensile and/or compressive stress and methods of manufacturing 有权
标题翻译：具有拉伸和/或压缩应力的半导体器件和制造方法
公开(公告)号：US09368410B2
公开(公告)日：2016-06-14
申请号：US12033280
申请日：2008-02-19
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Edmund J. Sprogis
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Edmund J. Sprogis
IPC分类号： H01L29/78 , H01L21/762 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/76205 , H01L21/823878 , H01L29/7846
摘要： A semiconductor device and method of manufacturing is disclosed which has a tensile and/or compressive strain applied thereto. The method includes forming at least one trench in a material; and filling the at least one trench by an oxidation process thereby forming a strain concentration in a channel of a device. The structure includes a gate structure having a channel and a first oxidized trench on a first of the channel, respectively. The first oxidized trench creates a strain component in the channel to increase device performance.
摘要翻译：公开了一种半导体器件和制造方法，其具有施加到其上的拉伸和/或压缩应变。该方法包括在材料中形成至少一个沟槽; 以及通过氧化工艺填充所述至少一个沟槽，从而在器件的通道中形成应变集中。该结构包括分别在第一通道上具有沟道和第一氧化沟槽的栅极结构。第一氧化沟槽在通道中产生应变分量以增加器件性能。

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