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1. 发明授权

US07814449B2 Design structure for multiple source-single drain field effect semiconductor device and circuit 有权
标题翻译：多源单源漏极场效应半导体器件和电路的设计结构
公开(公告)号：US07814449B2
公开(公告)日：2010-10-12
申请号：US11873515
申请日：2007-10-17
申请人： Wagdi W. Abadeer , Anthony R. Bonaccio , Joseph A. Iadanza
发明人： Wagdi W. Abadeer , Anthony R. Bonaccio , Joseph A. Iadanza
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： Disclosed are embodiments of a design structure for a variable-delay field effect transistor (FET) having multiple source regions that can be individually and selectively biased to provide an electrical connection to a single drain region. Delay is a function of which of the multiple source regions is/are selectively biased as well as a function of gate resistance and capacitance. Such a variable-delay FET can be incorporated into a phase adjusting circuit, which uses gate propagation delays to selectively phase adjust an input signal. The phase adjusting circuit can be tuned by incorporating non-salicided resistances and additional capacitance at various positions on the gate structure. The phase adjusting circuit can further be modified into a phase adjusting mixer circuit that enables a phase adjusted signal to be combined with an additional signal.
摘要翻译：公开了具有多个源极区域的可变延迟场效应晶体管（FET）的设计结构的实施例，其可被单独地和选择性地偏置以提供到单个漏极区域的电连接。延迟是多个源极区域中的哪一个被选择性偏置以及栅极电阻和电容的函数的函数。这样的可变延迟FET可以并入相位调整电路中，该相位调整电路使用栅极传播延迟来选择性地相位调整输入信号。相位调整电路可以通过在栅极结构上的各个位置并入非水银电阻和附加电容来调节。相位调整电路可以进一步修改为使相位调整信号与附加信号组合的相位调整混频器电路。

2. 发明申请

US20100019816A1 MICRO-PHASE ADJUSTING AND MICRO-PHASE ADJUSTING MIXER CIRCUITS DESIGNED WITH STANDARD FIELD EFFECT TRANSISTOR STRUCTURES 失效
标题翻译：具有标准场效应晶体管结构的微相调节和微相调节混频器电路
公开(公告)号：US20100019816A1
公开(公告)日：2010-01-28
申请号：US12573910
申请日：2009-10-06
申请人： Wagdi W. Abadeer , Anthony R. Bonaccio , Joseph A. Iadanza
发明人： Wagdi W. Abadeer , Anthony R. Bonaccio , Joseph A. Iadanza
IPC分类号： H03K5/13
CPC分类号： H03K5/06 , H03K2005/00052 , H03K2005/00058
摘要： Disclosed herein are embodiments of a programmable phase adjusting circuit, a programmable phase adjusting mixer circuit and design structures for these circuits. These circuits comprise a variable delay device connected between input and output nodes. The device includes multiple FETs with input diffusion regions that are connected to a voltage rail via switches so that they can be selectively biased, gates that are connected in series to the input node so that a periodic input signal can be propagated sequentially through each of the gates and output diffusion regions that are connected in parallel to the output node. A current source is connected between the output node and another voltage rail for biasing the output node when the variable delay device is off. The variable delay device enables a circuit in which small increments of selectable phase adjustments can be made to the periodic input signal as a function of propagation delay.
摘要翻译：这里公开了可编程相位调整电路，可编程相位调整混频器电路和这些电路的设计结构的实施例。这些电路包括连接在输入和输出节点之间的可变延迟器件。该器件包括多个FET，其输入扩散区通过开关连接到电压轨，使得它们可以被选择性偏置，与输入节点串联连接的栅极，使得周期性输入信号可以顺序地传播通过门和输出扩散区域并联连接到输出节点。当可变延迟装置关闭时，电流源连接在输出节点和另一个电压轨道之间，用于偏置输出节点。可变延迟装置使得能够作为传播延迟的函数对周期性输入信号进行可选相位调整的小增量的电路。

3. 发明申请

US20090106707A1 Multiple Source-Single Drain Field Effect Semiconductor Device and Circuit 有权
标题翻译：多源单漏极场效应半导体器件与电路
公开(公告)号：US20090106707A1
公开(公告)日：2009-04-23
申请号：US11873515
申请日：2007-10-17
申请人： Wagdi W. Abadeer , Anthony R. Bonaccio , Joseph A. Iadanza
发明人： Wagdi W. Abadeer , Anthony R. Bonaccio , Joseph A. Iadanza
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Disclosed are embodiments of a design structure for a variable-delay field effect transistor (FET) having multiple source regions that can be individually and selectively biased to provide an electrical connection to a single drain region. Delay is a function of which of the multiple source regions is/are selectively biased as well as a function of gate resistance and capacitance. Such a variable-delay FET can be incorporated into a phase adjusting circuit, which uses gate propagation delays to selectively phase adjust an input signal. The phase adjusting circuit can be tuned by incorporating non-salicided resistances and additional capacitance at various positions on the gate structure. The phase adjusting circuit can further be modified into a phase adjusting mixer circuit that enables a phase adjusted signal to be combined with an additional signal.
摘要翻译：公开了具有多个源极区域的可变延迟场效应晶体管（FET）的设计结构的实施例，其可被单独地和选择性地偏置以提供到单个漏极区域的电连接。延迟是多个源极区域中的哪一个被选择性偏置以及栅极电阻和电容的函数的函数。这样的可变延迟FET可以并入相位调整电路中，该相位调整电路使用栅极传播延迟来选择性地相位调整输入信号。相位调整电路可以通过在栅极结构上的各个位置并入非水银电阻和附加电容来调节。相位调整电路可以进一步修改为使相位调整信号与附加信号组合的相位调整混频器电路。

4. 发明授权

US07932552B2 Multiple source-single drain field effect semiconductor device and circuit 有权
标题翻译：多源单漏极场效应半导体器件和电路
公开(公告)号：US07932552B2
公开(公告)日：2011-04-26
申请号：US11833538
申请日：2007-08-03
申请人： Wagdi W. Abadeer , Anthony R. Bonaccio , Joseph A. Iadanza
发明人： Wagdi W. Abadeer , Anthony R. Bonaccio , Joseph A. Iadanza
IPC分类号： H01L29/66
CPC分类号： H01L27/0705 , H01L21/823418
摘要： Disclosed are embodiments of a variable-delay field effect transistor (FET) having multiple source regions that can be individually and selectively biased to provide an electrical connection to a single drain region. Delay is a function of which of the multiple source regions is/are selectively biased as well as a function of gate resistance and capacitance. Such a variable-delay FET can be incorporated into a phase adjusting circuit, which uses gate propagation delays to selectively phase adjust an input signal. The phase adjusting circuit can be tuned by incorporating non-salicided resistances and additional capacitance at various positions on the gate structure. The phase adjusting circuit can further be modified into a phase adjusting mixer circuit that enables a phase adjusted signal to be combined with an additional signal.
摘要翻译：公开了具有多个源极区域的可变延迟场效应晶体管（FET）的实施例，其可被单独和选择性地偏置以提供到单个漏极区域的电连接。延迟是多个源极区域中的哪一个被选择性偏置以及栅极电阻和电容的函数的函数。这样的可变延迟FET可以并入相位调整电路中，该相位调整电路使用栅极传播延迟来选择性地相位调整输入信号。相位调整电路可以通过在栅极结构上的各个位置并入非水银电阻和附加电容来调节。相位调整电路可以进一步修改为使相位调整信号与附加信号组合的相位调整混频器电路。

5. 发明授权

US07795940B2 Micro-phase adjusting and micro-phase adjusting mixer circuits designed with standard field effect transistor structures 失效
标题翻译：微相调节和微相调谐混频器电路采用标准场效应晶体管结构设计
公开(公告)号：US07795940B2
公开(公告)日：2010-09-14
申请号：US12573910
申请日：2009-10-06
申请人： Wagdi W. Abadeer , Anthony R. Bonaccio , Joseph A. Iadanza
发明人： Wagdi W. Abadeer , Anthony R. Bonaccio , Joseph A. Iadanza
IPC分类号： H03K3/00 , H03H11/16 , H03K5/13
CPC分类号： H03K5/06 , H03K2005/00052 , H03K2005/00058
摘要： Disclosed herein are embodiments of a programmable phase adjusting circuit, a programmable phase adjusting mixer circuit and design structures for these circuits. These circuits comprise a variable delay device connected between input and output nodes. The device includes multiple FETs with input diffusion regions that are connected to a voltage rail via switches so that they can be selectively biased, gates that are connected in series to the input node so that a periodic input signal can be propagated sequentially through each of the gates and output diffusion regions that are connected in parallel to the output node. A current source is connected between the output node and another voltage rail for biasing the output node when the variable delay device is off. The variable delay device enables a circuit in which small increments of selectable phase adjustments can be made to the periodic input signal as a function of propagation delay.
摘要翻译：这里公开了可编程相位调整电路，可编程相位调整混频器电路和这些电路的设计结构的实施例。这些电路包括连接在输入和输出节点之间的可变延迟器件。该器件包括多个FET，其输入扩散区通过开关连接到电压轨，使得它们可以被选择性偏置，与输入节点串联连接的栅极，使得周期性输入信号可以顺序地传播通过门和输出扩散区域并联连接到输出节点。当可变延迟装置关闭时，电流源连接在输出节点和另一个电压轨道之间，用于偏置输出节点。可变延迟装置使得能够作为传播延迟的函数对周期性输入信号进行可选相位调整的小增量的电路。

6. 发明申请

US20090033395A1 MULTIPLE SOURCE-SINGLE DRAIN FIELD EFFECT SEMICONDUCTOR DEVICE AND CIRCUIT 有权
标题翻译：多源单向漏磁场效应半导体器件与电路
公开(公告)号：US20090033395A1
公开(公告)日：2009-02-05
申请号：US11833538
申请日：2007-08-03
申请人： Wagdi W. Abadeer , Anthony R. Bonaccio , Joseph A. Iadanza
发明人： Wagdi W. Abadeer , Anthony R. Bonaccio , Joseph A. Iadanza
IPC分类号： H03H11/16 , H03H11/26
CPC分类号： H01L27/0705 , H01L21/823418
摘要： Disclosed are embodiments of a variable-delay field effect transistor (FET) having multiple source regions that can be individually and selectively biased to provide an electrical connection to a single drain region. Delay is a function of which of the multiple source regions is/are selectively biased as well as a function of gate resistance and capacitance. Such a variable-delay FET can be incorporated into a phase adjusting circuit, which uses gate propagation delays to selectively phase adjust an input signal. The phase adjusting circuit can be tuned by incorporating non-salicided resistances and additional capacitance at various positions on the gate structure. The phase adjusting circuit can further be modified into a phase adjusting mixer circuit that enables a phase adjusted signal to be combined with an additional signal.
摘要翻译：公开了具有多个源极区域的可变延迟场效应晶体管（FET）的实施例，其可被单独和选择性地偏置以提供到单个漏极区域的电连接。延迟是多个源极区域中的哪一个被选择性偏置以及栅极电阻和电容的函数的函数。这样的可变延迟FET可以并入相位调整电路中，该相位调整电路使用栅极传播延迟来选择性地相位调整输入信号。相位调整电路可以通过在栅极结构上的各个位置并入非水银电阻和附加电容来调节。相位调整电路可以进一步修改为使相位调整信号与附加信号组合的相位调整混频器电路。

7. 发明申请

US20090033389A1 MICRO-PHASE ADJUSTING AND MICRO-PHASE ADJUSTING MIXER CIRCUITS DESIGNED WITH STANDARD FIELD EFFECT TRANSISTOR STRUCTURES 审中-公开
标题翻译：具有标准场效应晶体管结构的微相调节和微相调节混频器电路
公开(公告)号：US20090033389A1
公开(公告)日：2009-02-05
申请号：US11833567
申请日：2007-08-03
申请人： Wagdi W. Abadeer , Anthony R. Bonaccio , Joseph A. Iadanza
发明人： Wagdi W. Abadeer , Anthony R. Bonaccio , Joseph A. Iadanza
IPC分类号： H03L7/00 , G06F17/50
CPC分类号： H03K5/06 , H03K2005/00052 , H03K2005/00058
摘要： Disclosed herein are embodiments of a programmable phase adjusting circuit, a programmable phase adjusting mixer circuit and design structures for these circuits. These circuits comprise a variable delay device connected between input and output nodes. The device includes multiple FETs with input diffusion regions that are connected to a voltage rail via switches so that they can be selectively biased, gates that are connected in series to the input node so that a periodic input signal can be propagated sequentially through each of the gates and output diffusion regions that are connected in parallel to the output node. A current source is connected between the output node and another voltage rail for biasing the output node when the variable delay device is off. The variable delay device enables a circuit in which small increments of selectable phase adjustments can be made to the periodic input signal as a function of propagation delay.
摘要翻译：这里公开了可编程相位调整电路，可编程相位调整混频器电路和这些电路的设计结构的实施例。这些电路包括连接在输入和输出节点之间的可变延迟器件。该器件包括多个FET，其输入扩散区通过开关连接到电压轨，使得它们可以被选择性偏置，与输入节点串联连接的栅极，使得周期性输入信号可以顺序地传播通过门和输出扩散区域并联连接到输出节点。当可变延迟装置关闭时，电流源连接在输出节点和另一个电压轨道之间，用于偏置输出节点。可变延迟装置使得能够作为传播延迟的函数对周期性输入信号进行可选相位调整的小增量的电路。

8. 发明授权

US07167053B2 Integrated circuit amplifier device and method using FET tunneling gate current 失效
标题翻译：集成电路放大器器件及使用FET隧道栅极电流的方法
公开(公告)号：US07167053B2
公开(公告)日：2007-01-23
申请号：US10904238
申请日：2004-10-29
申请人： Wagdi W. Abadeer , Anthony R. Bonaccio , Kiran V. Chatty , John A. Fifield
发明人： Wagdi W. Abadeer , Anthony R. Bonaccio , Kiran V. Chatty , John A. Fifield
IPC分类号： H03F3/16 , H03F3/45 , H03G3/12
CPC分类号： H03F3/16 , H03F3/45179 , H03F3/505 , H03F2203/45468
摘要： An integrated circuit amplifier includes, in an exemplary embodiment, a first field effect transistor (FET) device configured as a common source amplifier with source degeneration and a second FET device configured as a tunneling gate FET, the tunneling gate FET coupled to the source follower. The tunneling gate FET is further configured so as to set a transconductance of the amplifier and the common source amplifier with source degeneration is configured so as to set an output conductance of the amplifier.
摘要翻译：在示例性实施例中，集成电路放大器包括被配置为具有源极退化的公共源极放大器的第一场效应晶体管（FET）器件和被配置为隧道栅极FET的第二FET器件，所述隧道栅极FET耦合到源极跟随器。隧道栅极FET进一步配置为设置放大器的跨导，并且配置源极退化的公共源极放大器，以便设置放大器的输出电导。

9. 发明授权

US07477541B2 Memory elements and methods of using the same 失效
标题翻译：内存元素和使用方法
公开(公告)号：US07477541B2
公开(公告)日：2009-01-13
申请号：US11353493
申请日：2006-02-14
申请人： Wagdi W. Abadeer , Anthony R. Bonaccio , Jack A. Mandelman , William R. Tonti , Sebastian T. Ventrone
发明人： Wagdi W. Abadeer , Anthony R. Bonaccio , Jack A. Mandelman , William R. Tonti , Sebastian T. Ventrone
IPC分类号： G11C11/34
CPC分类号： G11C16/0466
摘要： In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one or more MOSFETs. The control logic is adapted to (a) cause the memory element to operate in a first mode to store data; and (b) cause the memory element to operate in a second mode to change a threshold voltage of at least one of the one or more MOSFETs from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects data stored by the memory element when operated in the first mode. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种第一装置。第一装置是存储元件，其包括（1）一个或多个MOSFET，每个MOSFET包括具有约3.9至约25的介电常数的电介质材料; 和（2）耦合到所述一个或多个MOSFET中的至少一个的控制逻辑。控制逻辑适于（a）使存储元件以第一模式操作以存储数据; 和（b）使存储元件在第二模式下操作以将一个或多个MOSFET中的至少一个的阈值电压从原始阈值电压改变到改变的阈值电压，使得改变的阈值电压影响由存储元件在第一模式下操作。提供了许多其他方面。

10. 发明申请

US20090147568A1 Memory Elements and Methods of Using the Same 有权
标题翻译：内存元素及其使用方法
公开(公告)号：US20090147568A1
公开(公告)日：2009-06-11
申请号：US12351872
申请日：2009-01-12
申请人： Wagdi W. Abadeer , Anthony R. Bonaccio , Jack A. Mandelman , William R. Tonti , Sebastian T. Ventrone
发明人： Wagdi W. Abadeer , Anthony R. Bonaccio , Jack A. Mandelman , William R. Tonti , Sebastian T. Ventrone
IPC分类号： G11C11/34
CPC分类号： G11C16/0466
摘要： In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one or more MOSFETs. The control logic is adapted to (a) cause the memory element to operate in a first mode to store data; and (b) cause the memory element to operate in a second mode to change a threshold voltage of at least one of the one or more MOSFETs from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects data stored by the memory element when operated in the first mode. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种第一装置。第一装置是存储元件，其包括（1）一个或多个MOSFET，每个MOSFET包括具有约3.9至约25的介电常数的电介质材料; 和（2）耦合到所述一个或多个MOSFET中的至少一个的控制逻辑。控制逻辑适于（a）使存储元件以第一模式操作以存储数据; 和（b）使存储元件在第二模式下操作以将一个或多个MOSFET中的至少一个的阈值电压从原始阈值电压改变到改变的阈值电压，使得改变的阈值电压影响由存储元件在第一模式下操作。提供了许多其他方面。

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