专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08841893B2 Dual-loop voltage regulator architecture with high DC accuracy and fast response time 有权
标题翻译：双回路稳压器架构，具有高直流精度和响应时间快
公开(公告)号：US08841893B2
公开(公告)日：2014-09-23
申请号：US13213578
申请日：2011-08-19
申请人： John F. Bulzacchelli , Carrie E. Cox , Zeynep Toprak-Deniz , Daniel J. Friedman , Joseph A. Iadanza , Todd M. Rasmus
发明人： John F. Bulzacchelli , Carrie E. Cox , Zeynep Toprak-Deniz , Daniel J. Friedman , Joseph A. Iadanza , Todd M. Rasmus
IPC分类号： G05F1/575
CPC分类号： G05F1/575
摘要： Dual-loop voltage regulator circuits and methods in which a dual-loop voltage regulation framework is implemented with a first inner loop having a bang-bang voltage regulator to achieve nearly instantaneous response time, and a second outer loop, which is slower in operating speed than the first inner loop, to controllably adjust a trip point of the bang-bang voltage regulator to achieve high DC accuracy.
摘要翻译：双环路电压调节器电路和方法，其中使用具有爆轰电压调节器的第一内环实现双回路电压调节框架以实现几乎瞬时的响应时间，以及第二外环，其操作速度较慢比第一个内环，可控地调节砰砰电压调节器的跳闸点，以实现高直流精度。

2. 发明申请

US20120153910A1 DUAL-LOOP VOLTAGE REGULATOR ARCHITECTURE WITH HIGH DC ACCURACY AND FAST RESPONSE TIME 有权
标题翻译：具有高直流精度和快速响应时间的双环电压调节器架构
公开(公告)号：US20120153910A1
公开(公告)日：2012-06-21
申请号：US13213578
申请日：2011-08-19
申请人： John F. Bulzacchelli , Carrie E. Cox , Zeynep Toprak-Deniz , Daniel J. Friedman , Joseph A. Iadanza , Todd M. Rasmus
发明人： John F. Bulzacchelli , Carrie E. Cox , Zeynep Toprak-Deniz , Daniel J. Friedman , Joseph A. Iadanza , Todd M. Rasmus
IPC分类号： G05F1/10
CPC分类号： G05F1/575
摘要： Dual-loop voltage regulator circuits and methods in which a dual-loop voltage regulation framework is implemented with a first inner loop having a bang-bang voltage regulator to achieve nearly instantaneous response time, and a second outer loop, which is slower in operating speed than the first inner loop, to controllably adjust a trip point of the bang-bang voltage regulator to achieve high DC accuracy.
摘要翻译：双环路电压调节器电路和方法，其中使用具有爆轰电压调节器的第一内环实现双回路电压调节框架以实现几乎瞬时的响应时间，以及第二外环，其操作速度较慢比第一个内环，可控地调节砰砰电压调节器的跳闸点，以实现高直流精度。

3. 发明申请

US20120153909A1 HYBRID FAST-SLOW PASSGATE CONTROL METHODS FOR VOLTAGE REGULATORS EMPLOYING HIGH SPEED COMPARATORS 审中-公开
标题翻译：采用高速比较器的电压调节器的混合快速低通控制方法
公开(公告)号：US20120153909A1
公开(公告)日：2012-06-21
申请号：US13213368
申请日：2011-08-19
申请人： William L. Bucossi , John F. Bulzacchelli , Mohak Chhabra , Zeynep Toprak-Deniz , Daniel J. Friedman , Joseph A. Iadanza , Todd M. Rasmus
发明人： William L. Bucossi , John F. Bulzacchelli , Mohak Chhabra , Zeynep Toprak-Deniz , Daniel J. Friedman , Joseph A. Iadanza , Todd M. Rasmus
IPC分类号： G05F1/10
CPC分类号： H02M3/1563 , H02M1/15 , H02M2003/1566
摘要： Voltage regulator circuits and methods implementing hybrid fast-slow passgate control circuitry are provided to minimize the ripple amplitude of a regulated voltage output. In one aspect, a voltage regulator circuit includes a comparator, a first passgate device, a second passgate device, and a bandwidth limiting control circuit. The comparator compares a reference voltage to a regulated voltage at an output node of the voltage regulator circuit and generates a first control signal on a first gate control path based on a result of the comparing. The first and second passgate devices are connected to the output node of the regulator circuit. The first passgate device is controlled in a bang-bang mode of operation by the first control signal to supply current to the output node. The bandwidth limiting control circuit has an input connected to the first gate control path and an output connected to the second passgate device. The bandwidth limiting control circuit generates a second control signal based on the first control signal, wherein the second control signal is a slew rate limited version of the first control signal, and wherein the second passgate is controlled by the second control signal to supply current to the output node.
摘要翻译：提供了实现混合快速慢门控制电路的稳压器电路和方法，以最小化稳压电压输出的纹波幅度。在一个方面，电压调节器电路包括比较器，第一通道门，第二通道器件和带宽限制控制电路。比较器将参考电压与调节器电路的输出节点处的调节电压进行比较，并且基于比较的结果在第一门控制路径上产生第一控制信号。第一和第二传递门装置连接到调节器电路的输出节点。第一传递门装置通过第一控制信号被控制在爆炸操作模式中，以向输出节点提供电流。带宽限制控制电路具有连接到第一门控制路径的输入端和连接到第二通道门装置的输出端。带宽限制控制电路基于第一控制信号产生第二控制信号，其中第二控制信号是第一控制信号的转换速率限制版本，并且其中第二传递门由第二控制信号控制以将电流提供给输出节点。

4. 发明申请

US20100328130A1 TIME-TO-DIGITAL BASED ANALOG-TO-DIGITAL CONVERTER ARCHITECTURE 有权
标题翻译：基于时间到数字的模拟到数字转换器架构
公开(公告)号：US20100328130A1
公开(公告)日：2010-12-30
申请号：US12494496
申请日：2009-06-30
申请人： John F. Bulzacchelli , Daniel J. Friedman , Shahrzad Naraghi , Sergey V. Rylov , Alexander V. Rylyakov , Zeynep Toprak-Deniz
发明人： John F. Bulzacchelli , Daniel J. Friedman , Shahrzad Naraghi , Sergey V. Rylov , Alexander V. Rylyakov , Zeynep Toprak-Deniz
IPC分类号： H03M1/50
CPC分类号： H03M1/20 , H03M1/1215 , H03M1/502
摘要： Apparatus and methods are provided relating to time-to-digital based analog-to-digital converter. An apparatus includes a time-to-digital converter based analog-to-digital converter for generating a first signal and a second signal having a timing relationship between a rising edge of the first signal and a rising edge of the second signal based on a sampled input analog voltage level, and converting the timing relationship into a corresponding time-to-digital representation. The time-to-digital representation is obtained without any voltage comparison and current comparison.
摘要翻译：提供了关于基于时间到数字的模数转换器的装置和方法。一种装置包括：基于时间 - 数字转换器的模数转换器，用于产生第一信号;以及第二信号，其具有基于采样的第一信号的上升沿和第二信号的上升沿之间的定时关系输入模拟电压电平，并将定时关系转换成相应的时间 - 数字表示。在没有任何电压比较和电流比较的情况下获得时间到数字表示。

5. 发明授权

US08138840B2 Optimal dithering of a digitally controlled oscillator with clock dithering for gain and bandwidth control 有权
标题翻译：具有时钟抖动的数字控制振荡器的最佳抖动，用于增益和带宽控制
公开(公告)号：US08138840B2
公开(公告)日：2012-03-20
申请号：US12358736
申请日：2009-01-23
申请人： Herschel A. Ainspan , John F. Bulzacchelli , Zeynep Toprak Deniz , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
发明人： Herschel A. Ainspan , John F. Bulzacchelli , Zeynep Toprak Deniz , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
IPC分类号： H03L7/085 , H03L7/089
CPC分类号： H03L7/081 , H03L7/085 , H03L7/099
摘要： A digital phase locked loop (DPLL) and method include an adjustable delay line configured to receive a reference clock as an input and to output a dithered reference clock signal. A phase and frequency detector (PFD) is configured to compare the dithered reference clock signal with a feedback clock signal to determine phase and frequency differences between the dithered reference clock signal and the feedback clock signal. A digitally controlled oscillator (DCO) is configured to receive early or late determinations from the PFD to adjust an output in accordance therewith, wherein the dithered reference clock signal distributes jitter response to enhance overall operation of the DPLL.
摘要翻译：数字锁相环（DPLL）和方法包括可调延迟线，其配置为接收参考时钟作为输入并输出抖动参考时钟信号。相位和频率检测器（PFD）被配置为将抖动参考时钟信号与反馈时钟信号进行比较，以确定抖动参考时钟信号和反馈时钟信号之间的相位和频率差。数字控制振荡器（DCO）被配置为接收来自PFD的早期或晚期确定以根据其调整输出，其中抖动参考时钟信号分配抖动响应以增强DPLL的整体操作。

6. 发明申请

US20100188158A1 OPTIMAL DITHERING OF A DIGITALLY CONTROLLED OSCILLATOR WITH CLOCK DITHERING FOR GAIN AND BANDWIDTH CONTROL 有权
标题翻译：数字控制振荡器的最佳抖动，具有时钟抖动，用于增益和带宽控制
公开(公告)号：US20100188158A1
公开(公告)日：2010-07-29
申请号：US12358736
申请日：2009-01-23
申请人： Herschel A. Ainspan , John F. Bulzacchelli , Zeynep Toprak Deniz , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
发明人： Herschel A. Ainspan , John F. Bulzacchelli , Zeynep Toprak Deniz , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
IPC分类号： H03L7/099
CPC分类号： H03L7/081 , H03L7/085 , H03L7/099
摘要： A digital phase locked loop (DPLL) and method include an adjustable delay line configured to receive a reference clock as an input and to output a dithered reference clock signal. A phase and frequency detector (PFD) is configured to compare the dithered reference clock signal with a feedback clock signal to determine phase and frequency differences between the dithered reference clock signal and the feedback clock signal. A digitally controlled oscillator (DCO) is configured to receive early or late determinations from the PFD to adjust an output in accordance therewith, wherein the dithered reference clock signal distributes jitter response to enhance overall operation of the DPLL.
摘要翻译：数字锁相环（DPLL）和方法包括可调延迟线，其配置为接收参考时钟作为输入并输出抖动参考时钟信号。相位和频率检测器（PFD）被配置为将抖动参考时钟信号与反馈时钟信号进行比较，以确定抖动参考时钟信号和反馈时钟信号之间的相位和频率差。数字控制振荡器（DCO）被配置为接收来自PFD的早期或晚期确定以根据其调整输出，其中抖动参考时钟信号分配抖动响应以增强DPLL的整体操作。

7. 发明授权

US07893861B2 Time-to-digital based analog-to-digital converter architecture 有权
标题翻译：基于时间到数字的模数转换器架构
公开(公告)号：US07893861B2
公开(公告)日：2011-02-22
申请号：US12494496
申请日：2009-06-30
申请人： John F. Bulzacchelli , Daniel J. Friedman , Shahrzad Naraghi , Sergey V. Rylov , Alexander V. Rylyakov , Zeynep Toprak-Deniz
发明人： John F. Bulzacchelli , Daniel J. Friedman , Shahrzad Naraghi , Sergey V. Rylov , Alexander V. Rylyakov , Zeynep Toprak-Deniz
IPC分类号： H03M1/50
CPC分类号： H03M1/20 , H03M1/1215 , H03M1/502
摘要： Apparatus and methods are provided relating to time-to-digital based analog-to-digital converter. An apparatus includes a time-to-digital converter based analog-to-digital converter for generating a first signal and a second signal having a timing relationship between a rising edge of the first signal and a rising edge of the second signal based on a sampled input analog voltage level, and converting the timing relationship into a corresponding time-to-digital representation. The time-to-digital representation is obtained without any voltage comparison and current comparison.
摘要翻译：提供了关于基于时间到数字的模数转换器的装置和方法。一种装置包括：基于时间 - 数字转换器的模数转换器，用于产生第一信号;以及第二信号，其具有基于采样的第一信号的上升沿和第二信号的上升沿之间的定时关系输入模拟电压电平，并将定时关系转换成相应的时间 - 数字表示。在没有任何电压比较和电流比较的情况下获得时间到数字表示。

8. 发明授权

US08183948B2 Ultra-compact PLL with wide tuning range and low noise 有权
标题翻译：超紧凑型PLL，调谐范围宽，噪音低
公开(公告)号：US08183948B2
公开(公告)日：2012-05-22
申请号：US12702798
申请日：2010-02-09
申请人： Herschel A. Ainspan , John F. Bulzacchelli , Daniel J. Friedman , Ankush Goel , Alexander V. Rylyakov
发明人： Herschel A. Ainspan , John F. Bulzacchelli , Daniel J. Friedman , Ankush Goel , Alexander V. Rylyakov
IPC分类号： H03B5/12 , H03B5/18
CPC分类号： H03B5/1212 , H03B5/1215 , H03B5/1228 , H03B5/1253 , H03B5/1256 , H03B5/1265 , H03B2200/0088 , H03L7/099 , H03L7/10 , H03L7/18 , H03L2207/06 , H03L2207/50
摘要： A design for an oscillator, and a PLL incorporating such an oscillator, which takes up little physical area but maintains a large tuning range and low phase noise. Two LC-tanks are nested and switched. Through tuning the inactive tank, the range of the active tank may be increased and finer tuning becomes possible.
摘要翻译：振荡器的设计，以及包含这种振荡器的PLL，其占用很小的物理面积，但保持较大的调谐范围和低的相位噪声。两个LC坦克被嵌套和切换。通过调节不活动的水箱，可以增加活动水箱的范围，并可以进行更精细的调节。

9. 发明申请

US20110063038A1 ULTRA-COMPACT PLL WITH WIDE TUNING RANGE AND LOW NOISE 有权
标题翻译：具有宽调谐范围和低噪声的超紧凑型PLL
公开(公告)号：US20110063038A1
公开(公告)日：2011-03-17
申请号：US12702798
申请日：2010-02-09
申请人： Herschel A. Ainspan , John F. Bulzacchelli , Daniel J. Friedman , Ankush Goel , Alexander V. Rylyakov
发明人： Herschel A. Ainspan , John F. Bulzacchelli , Daniel J. Friedman , Ankush Goel , Alexander V. Rylyakov
IPC分类号： H03L9/00 , H03B5/08
CPC分类号： H03B5/1212 , H03B5/1215 , H03B5/1228 , H03B5/1253 , H03B5/1256 , H03B5/1265 , H03B2200/0088 , H03L7/099 , H03L7/10 , H03L7/18 , H03L2207/06 , H03L2207/50
摘要： A design for an oscillator, and a PLL incorporating such an oscillator, which takes up little physical area but maintains a large tuning range and low phase noise. Two LC-tanks are nested and switched. Through tuning the inactive tank, the range of the active tank may be increased and finer tuning becomes possible.
摘要翻译：振荡器的设计，以及包含这种振荡器的PLL，其占用很小的物理面积，但保持较大的调谐范围和低的相位噪声。两个LC坦克被嵌套和切换。通过调节不活动的水箱，可以增加活动水箱的范围，并可以进行更精细的调节。

10. 发明授权

US07822114B2 Decision feedback equalizer using soft decisions 失效
标题翻译：决策反馈均衡器使用软判决
公开(公告)号：US07822114B2
公开(公告)日：2010-10-26
申请号：US11761586
申请日：2007-06-12
申请人： John F. Bulzacchelli , Daniel J. Friedman , Alexander Rylyakov , Koon Lun Jackie Wong
发明人： John F. Bulzacchelli , Daniel J. Friedman , Alexander Rylyakov , Koon Lun Jackie Wong
IPC分类号： H03H7/30
CPC分类号： H04L25/03057 , H04L25/067 , H04L2025/0349
摘要： A decision feedback equalizer (DFE) and method include at least two paths. Each path includes the following. An adder is configured to sum an input with a first feedback tap fed back from a different path. A latch is coupled to the adder to receive a summation signal as input. The latch includes a transparent state, and an output of the latch is employed as the first tap in a feedback path to an adder of a different path, wherein a partially resolved first tap in the feedback path is employed during the transparent state to provide a soft decision to supply correction information in advance of a hard decision of the latch.
摘要翻译：决策反馈均衡器（DFE）和方法包括至少两个路径。每个路径包括以下内容。加法器被配置为将输入与从不同路径反馈的第一反馈分接相加。锁存器耦合到加法器以接收加法信号作为输入。锁存器包括透明状态，并且锁存器的输出被用作到到不同路径的加法器的反馈路径中的第一抽头，其中在透明状态期间采用反馈路径中的部分分辨的第一抽头以提供一个软判决在锁存器的硬判决之前提供校正信息。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式