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1. 发明申请

US20080157858A1 DESIGN STRUCTURE FOR IMPLEMENTING OXIDE LEAKAGE BASED VOLTAGE DIVIDER NETWORK FOR INTEGRATED CIRCUIT DEVICES 失效
标题翻译：用于集成电路设备实现基于氧化物泄漏的电压分压网络的设计结构
公开(公告)号：US20080157858A1
公开(公告)日：2008-07-03
申请号：US11872743
申请日：2007-10-16
申请人： Kenneth J. Goodnow , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout
发明人： Kenneth J. Goodnow , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H03K17/687 , H03K2017/6878
摘要： A design structure embodied in a machine readable medium used in a design process includes a voltage divider device, including a double gate field effect transistor (FET) having a first gate and a second gate disposed at opposite sides of a body region; the first and second gates configured to have an input voltage coupled thereacross; and at least one of a source of the FET and a drain of the FET configured to have an output voltage taken therefrom; wherein the output voltage represents a divided voltage with respect to the input voltage.
摘要翻译：体现在设计过程中使用的机器可读介质中的设计结构包括分压器件，其包括具有第一栅极的双栅场效应晶体管（FET）和设置在体区相对侧的第二栅极; 所述第一和第二栅极配置成具有耦合到其上的输入电压; 并且所述FET的源极和所述FET的漏极中的至少一个被配置为具有从其获取的输出电压; 其中输出电压表示相对于输入电压的分压。

2. 发明授权

US07307467B2 Structure and method for implementing oxide leakage based voltage divider network for integrated circuit devices 有权
标题翻译：用于集成电路器件实现基于氧化物泄漏的分压网络的结构和方法
公开(公告)号：US07307467B2
公开(公告)日：2007-12-11
申请号：US11380799
申请日：2006-04-28
申请人： Kenneth J. Goodnow , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout
发明人： Kenneth J. Goodnow , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H01L29/42384 , H01L21/823842 , H01L21/823857 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/785 , H01L29/78645 , H01L29/78648
摘要： A voltage divider device includes a double gate field effect transistor (FET) having a first gate and a second gate disposed at opposite sides of a body region. An input voltage is coupled between the first and second gates, and an output voltage is taken from at least one of a source of the FET and a drain of the FET, wherein the output voltage represents a divided voltage with respect to the input voltage.
摘要翻译：分压器装置包括具有第一栅极的双栅场效应晶体管（FET）和设置在体区相对侧的第二栅极。输入电压耦合在第一和第二栅极之间，并且输出电压取自FET的源极和FET的漏极中的至少一个，其中输出电压表示相对于输入电压的分压。

3. 发明授权

US07579897B2 Design structure for implementing oxide leakage based voltage divider network for integrated circuit devices 失效
标题翻译：用于集成电路器件实现基于氧化物泄漏的分压网络的设计结构
公开(公告)号：US07579897B2
公开(公告)日：2009-08-25
申请号：US11872743
申请日：2007-10-16
申请人： Kenneth J. Goodnow , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout
发明人： Kenneth J. Goodnow , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout
IPC分类号： H03K17/687
CPC分类号： H03K17/687 , H03K2017/6878
摘要： A design structure embodied in a machine readable medium used in a design process includes a voltage divider device, including a double gate field effect transistor (FET) having a first gate and a second gate disposed at opposite sides of a body region; the first and second gates configured to have an input voltage coupled thereacross; and at least one of a source of the FET and a drain of the FET configured to have an output voltage taken therefrom; wherein the output voltage represents a divided voltage with respect to the input voltage.
摘要翻译：体现在设计过程中使用的机器可读介质中的设计结构包括分压器件，其包括具有第一栅极的双栅场效应晶体管（FET）和设置在体区相对侧的第二栅极; 所述第一和第二栅极配置成具有耦合到其上的输入电压; 并且所述FET的源极和所述FET的漏极中的至少一个被配置为具有从其获取的输出电压; 其中输出电压表示相对于输入电压的分压。

4. 发明授权

US09070791B2 Tunable capacitor 有权
标题翻译：可调谐电容
公开(公告)号：US09070791B2
公开(公告)日：2015-06-30
申请号：US11923864
申请日：2007-10-25
申请人： Corey K. Barrows , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout , Mark S. Styduhar
发明人： Corey K. Barrows , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout , Mark S. Styduhar
IPC分类号： H01L29/94
CPC分类号： H01L29/94
摘要： Disclosed are embodiments of a design structure transistor that operates as a capacitor and an associated method of tuning capacitance within such a capacitor. The embodiments of the capacitor comprise a field effect transistor with front and back gates above and below a semiconductor layer, respectively. The capacitance value exhibited by the capacitor can be selectively varied between two different values by changing the voltage condition in a source/drain region of the transistor, e.g., using a switch or resistor between the source/drain region and a voltage supply. Alternatively, the capacitance value exhibited by the capacitor can be selectively varied between multiple different values by changing voltage conditions in one or more of multiple channel regions that are flanked by multiple source/drain regions within the transistor. The capacitor will exhibit different capacitance values depending upon the conductivity in each of the channel regions.
摘要翻译：公开了作为电容器操作的设计结构晶体管的实施例以及在这种电容器内调谐电容的相关方法。电容器的实施例包括分别在半导体层上方和下方具有前栅极和后栅极的场效应晶体管。通过改变晶体管的源极/漏极区域中的电压条件，例如使用源极/漏极区域和电压源之间的开关或电阻器，可以通过改变晶体管的源极/漏极区域中的电压条件来选择性地在两个不同的值之间改变电容器所呈现的电容值。或者，可以通过改变在晶体管内侧面有多个源极/漏极区域的多个沟道区域中的一个或多个中的电压条件来选择性地在多个不同值之间变化由电容器呈现的电容值。根据每个通道区域中的电导率，电容器将呈现不同的电容值。

5. 发明授权

US07821053B2 Tunable capacitor 有权
标题翻译：可调谐电容
公开(公告)号：US07821053B2
公开(公告)日：2010-10-26
申请号：US11560126
申请日：2006-11-15
申请人： Corey K. Barrows , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout , Mark S. Styduhar
发明人： Corey K. Barrows , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout , Mark S. Styduhar
IPC分类号： H01L29/93
CPC分类号： H01L29/94
摘要： Disclosed are embodiments of a transistor that operates as a capacitor and an associated method of tuning capacitance within such a capacitor. The embodiments of the capacitor comprise a field effect transistor with front and back gates above and below a semiconductor layer, respectively. The capacitance value exhibited by the capacitor can be selectively varied between two different values by changing the voltage condition in a source/drain region of the transistor, e.g., using a switch or resistor between the source/drain region and a voltage supply. Alternatively, the capacitance value exhibited by the capacitor can be selectively varied between multiple different values by changing voltage conditions in one or more of multiple channel regions that are flanked by multiple source/drain regions within the transistor. The capacitor will exhibit different capacitance values depending upon the conductivity in each of the channel regions.
摘要翻译：公开了用作电容器的晶体管的实施例以及在这种电容器内调谐电容的相关联的方法。电容器的实施例包括分别在半导体层上方和下方具有前栅极和后栅极的场效应晶体管。通过改变晶体管的源极/漏极区域中的电压条件，例如使用源极/漏极区域和电压源之间的开关或电阻器，可以通过改变晶体管的源极/ 或者，可以通过改变在晶体管内侧面有多个源极/漏极区域的多个沟道区域中的一个或多个中的电压条件来选择性地在多个不同值之间变化由电容器呈现的电容值。根据每个通道区域中的电导率，电容器将呈现不同的电容值。

6. 发明申请

US20090108320A1 TUNABLE CAPACITOR 有权
标题翻译： TUNABLE电容器
公开(公告)号：US20090108320A1
公开(公告)日：2009-04-30
申请号：US11923864
申请日：2007-10-25
申请人： Corey K. Barrows , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout , Mark S. Styduhar
发明人： Corey K. Barrows , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout , Mark S. Styduhar
IPC分类号： H01L29/94
CPC分类号： H01L29/94
摘要： Disclosed are embodiments of a design structure transistor that operates as a capacitor and an associated method of tuning capacitance within such a capacitor. The embodiments of the capacitor comprise a field effect transistor with front and back gates above and below a semiconductor layer, respectively. The capacitance value exhibited by the capacitor can be selectively varied between two different values by changing the voltage condition in a source/drain region of the transistor, e.g., using a switch or resistor between the source/drain region and a voltage supply. Alternatively, the capacitance value exhibited by the capacitor can be selectively varied between multiple different values by changing voltage conditions in one or more of multiple channel regions that are flanked by multiple source/drain regions within the transistor. The capacitor will exhibit different capacitance values depending upon the conductivity in each of the channel regions.
摘要翻译：公开了作为电容器操作的设计结构晶体管的实施例以及在这种电容器内调谐电容的相关方法。电容器的实施例包括分别在半导体层上方和下方具有前栅极和后栅极的场效应晶体管。通过改变晶体管的源极/漏极区域中的电压条件，例如使用源极/漏极区域和电压源之间的开关或电阻器，可以通过改变晶体管的源极/ 或者，可以通过改变在晶体管内侧面有多个源极/漏极区域的多个沟道区域中的一个或多个中的电压条件来选择性地在多个不同值之间变化由电容器呈现的电容值。根据每个通道区域中的电导率，电容器将呈现不同的电容值。

7. 发明申请

US20090101940A1 DUAL GATE FET STRUCTURES FOR FLEXIBLE GATE ARRAY DESIGN METHODOLOGIES 审中-公开
标题翻译：用于柔性门阵列设计方法的双门FET结构
公开(公告)号：US20090101940A1
公开(公告)日：2009-04-23
申请号：US11874957
申请日：2007-10-19
申请人： Corey K. Barrows , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout
发明人： Corey K. Barrows , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout
IPC分类号： H01L29/76 , H01L21/82 , G06F17/50
CPC分类号： H03K19/1778 , H01L29/785 , H01L29/78648
摘要： A gate array cell adapted for standard cell design methodology or programmable gate array that incorporates a dual gate FET device to offer a range of performance options within the same unit cell area. The conductivity and drive strength of the dual gate device may be selectively tuned through independent processing of manufacturing parameters to provide an asymmetric circuit response for the device or a symmetric response as dictated by the circuit application.
摘要翻译：适用于标准单元设计方法的门阵列单元或包括双栅极FET器件的可编程门阵列，以在相同单元单元区域内提供一系列性能选项。可以通过制造参数的独立处理来选择性地调节双栅极器件的导电性和驱动强度，以为器件提供不对称电路响应或由电路应用所指示的对称响应。

8. 发明申请

US20080111176A1 TUNABLE CAPACITOR 有权
标题翻译： TUNABLE电容器
公开(公告)号：US20080111176A1
公开(公告)日：2008-05-15
申请号：US11560126
申请日：2006-11-15
申请人： Corey K. Barrows , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout , Mark S. Styduhar
发明人： Corey K. Barrows , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout , Mark S. Styduhar
IPC分类号： H01L29/93
CPC分类号： H01L29/94
摘要： Disclosed are embodiments of a transistor that operates as a capacitor and an associated method of tuning capacitance within such a capacitor. The embodiments of the capacitor comprise a field effect transistor with front and back gates above and below a semiconductor layer, respectively. The capacitance value exhibited by the capacitor can be selectively varied between two different values by changing the voltage condition in a source/drain region of the transistor, e.g., using a switch or resistor between the source/drain region and a voltage supply. Alternatively, the capacitance value exhibited by the capacitor can be selectively varied between multiple different values by changing voltage conditions in one or more of multiple channel regions that are flanked by multiple source/drain regions within the transistor. The capacitor will exhibit different capacitance values depending upon the conductivity in each of the channel regions.
摘要翻译：公开了用作电容器的晶体管的实施例以及在这种电容器内调谐电容的相关联的方法。电容器的实施例包括分别在半导体层上方和下方具有前栅极和后栅极的场效应晶体管。通过改变晶体管的源极/漏极区域中的电压条件，例如使用源极/漏极区域和电压源之间的开关或电阻器，可以通过改变晶体管的源极/ 或者，可以通过改变在晶体管内侧面有多个源极/漏极区域的多个沟道区域中的一个或多个中的电压条件来选择性地在多个不同值之间变化由电容器呈现的电容值。根据每个通道区域中的电导率，电容器将呈现不同的电容值。

9. 发明授权

US07107469B2 Power down processing islands 失效
标题翻译：关闭加工岛屿
公开(公告)号：US07107469B2
公开(公告)日：2006-09-12
申请号：US10604328
申请日：2003-07-11
申请人： Rafael Blanco , John M. Cohn , Kenneth J. Goodnow , Douglas W. Stout , Sebastian T. Ventrone
发明人： Rafael Blanco , John M. Cohn , Kenneth J. Goodnow , Douglas W. Stout , Sebastian T. Ventrone
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/3203 , G06F1/3287 , G11C5/144 , G11C5/147 , G11C2207/2227 , Y02D10/171
摘要： A structure and associated method of processing data on a semi-conductor device comprising an input island, a processing island, and an output island formed on the semiconductor device. The input island is adapted to accept a specified amount of data and enable a means for providing a first specified voltage for powering the processing island after accepting the specified amount of data. The processing island is adapted to receive and process the specified amount of data from the input island upon powering the processing island by the first specified voltage. The output island is adapted to be powered by a second specified voltage. The processing island is further adapted to transmit the processed data to the output island upon said powering by the second specified voltage. The first specified voltage is adapted to be disabled thereby removing power from processing island upon completion of transmission of the processed data to the output island.
摘要翻译：一种在半导体器件上处理数据的结构和相关方法，包括形成在半导体器件上的输入岛，处理岛和输出岛。输入岛适于接收指定数量的数据，并且能够在接受指定数量的数据之后启用用于提供用于为处理岛供电的第一指定电压的装置。处理岛适于在对处理岛供电第一指定电压时从输入岛接收和处理指定量的数据。输出岛适于由第二规定电压供电。处理岛还适于在所述第二规定电压的供电时将经处理的数据发送到输出岛。第一指定电压适于被禁用，从而在完成将处理的数据传输到输出岛时从处理岛去除功率。

10. 发明授权

US06825711B2 Power reduction by stage in integrated circuit 有权
标题翻译：集成电路中的功耗降低
公开(公告)号：US06825711B2
公开(公告)日：2004-11-30
申请号：US10249684
申请日：2003-04-30
申请人： John M. Cohn , Kenneth J. Goodnow , Scott W. Gould , Douglas W. Stout , Sebastian T. Ventrone
发明人： John M. Cohn , Kenneth J. Goodnow , Scott W. Gould , Douglas W. Stout , Sebastian T. Ventrone
IPC分类号： G05F110
CPC分类号： G06F1/3296 , G06F1/3203 , Y02D10/172
摘要： An integrated circuit, method and system providing finer granularity dynamic voltage control without performance loss. The invention provides a means for dynamically changing a voltage level of at least one stage on a critical path for a particular cycle. In this way, optimum voltages can be provided to the stages for the given expectation.
摘要翻译：一种集成电路，方法和系统，提供更精细的粒度动态电压控制，无需性能损失。本发明提供了用于在特定周期中动态地改变关键路径上的至少一个级的电压电平的装置。以这种方式，可以为给定期望的阶段提供最佳电压。

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