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1. 发明申请

US20080273373A1 APPARATUS FOR IMPROVED SRAM DEVICE PERFORMANCE THROUGH DOUBLE GATE TOPOLOGY 有权
标题翻译：通过双门拓扑改进SRAM设备性能的设备
公开(公告)号：US20080273373A1
公开(公告)日：2008-11-06
申请号：US12146554
申请日：2008-06-26
申请人： George M. Braceras , Wilfried E. A. Haensch , Joseph A. Iadanza
发明人： George M. Braceras , Wilfried E. A. Haensch , Joseph A. Iadanza
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A static random access memory (SRAM) device a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data, a first pair of transfer gates configured to couple complementary internal nodes of the storage cell to a corresponding pair of bitlines during a read operation of the device; and a second pair of transfer gates configured to couple the storage cell nodes to the pair of bitlines during a write operation of the device, wherein impedance between the bitlines and the storage cell nodes during the write operation is less than that for the read operation, wherein impedance between the bitlines and the storage cell nodes during the write operation is less than that for the read operation.
摘要翻译：一种静态随机存取存储器（SRAM）装置，被配置为用于数据位的存储单元的一对交叉耦合的互补金属氧化物半导体（CMOS）反相器，第一对传输门，被配置为耦合所述存储器的互补的内部节点在设备的读取操作期间，单元到相应的位线对; 以及第二对传输门，其被配置为在所述器件的写入操作期间将所述存储单元节点耦合到所述一对位线，其中在所述写入操作期间所述位线和所述存储单元节点之间的阻抗小于所述读操作的阻抗，其中在写入操作期间位线和存储单元节点之间的阻抗小于读取操作的阻抗。

2. 发明授权

US07408800B1 Apparatus and method for improved SRAM device performance through double gate topology 有权
标题翻译：通过双栅拓扑改善SRAM器件性能的装置和方法
公开(公告)号：US07408800B1
公开(公告)日：2008-08-05
申请号：US11743686
申请日：2007-05-03
申请人： George M. Braceras , Wilfried E. A. Haensch , Joseph A. Iadanza
发明人： George M. Braceras , Wilfried E. A. Haensch , Joseph A. Iadanza
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A static random access memory (SRAM) device a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data, a first pair of transfer gates configured to couple complementary internal nodes of the storage cell to a corresponding pair of bitlines during a read operation of the device; and a second pair of transfer gates configured to couple the storage cell nodes to the pair of bitlines during a write operation of the device, wherein impedance between the bitlines and the storage cell nodes during the write operation is less than that for the read operation, wherein impedance between the bitlines and the storage cell nodes during the write operation is less than that for the read operation.
摘要翻译：一种静态随机存取存储器（SRAM）装置，被配置为用于数据位的存储单元的一对交叉耦合的互补金属氧化物半导体（CMOS）反相器，第一对传输门，被配置为耦合所述存储器的互补的内部节点在设备的读取操作期间，单元到相应的位线对; 以及第二对传输门，其被配置为在所述器件的写入操作期间将所述存储单元节点耦合到所述一对位线，其中在所述写入操作期间所述位线和所述存储单元节点之间的阻抗小于所述读操作的阻抗，其中在写入操作期间位线和存储单元节点之间的阻抗小于读取操作的阻抗。

3. 发明授权

US07729159B2 Apparatus for improved SRAM device performance through double gate topology 有权
标题翻译：通过双门拓扑提高SRAM器件性能的器件
公开(公告)号：US07729159B2
公开(公告)日：2010-06-01
申请号：US12146554
申请日：2008-06-26
申请人： George M. Braceras , Wilfried E. A. Haensch , Joseph A. Iadanza
发明人： George M. Braceras , Wilfried E. A. Haensch , Joseph A. Iadanza
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A static random access memory (SRAM) device a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data, a first pair of transfer gates configured to couple complementary internal nodes of the storage cell to a corresponding pair of bitlines during a read operation of the device; and a second pair of transfer gates configured to couple the storage cell nodes to the pair of bitlines during a write operation of the device, wherein impedance between the bitlines and the storage cell nodes during the write operation is less than that for the read operation, wherein impedance between the bitlines and the storage cell nodes during the write operation is less than that for the read operation.
摘要翻译：一种静态随机存取存储器（SRAM）装置，被配置为用于数据位的存储单元的一对交叉耦合的互补金属氧化物半导体（CMOS）反相器，第一对传输门，被配置为耦合所述存储器的互补的内部节点在设备的读取操作期间，单元到相应的位线对; 以及第二对传输门，其被配置为在所述器件的写入操作期间将所述存储单元节点耦合到所述一对位线，其中在所述写入操作期间所述位线和所述存储单元节点之间的阻抗小于所述读操作的阻抗，其中在写入操作期间位线和存储单元节点之间的阻抗小于读取操作的阻抗。

4. 发明授权

US08445371B2 Self-aligned contacts 有权
公开(公告)号：US08445371B2
公开(公告)日：2013-05-21
申请号：US12755752
申请日：2010-04-07
申请人： Dechao Guo , Wilfried E. A. Haensch , Shu-Jen Han , Chung-Hsun Lin
发明人： Dechao Guo , Wilfried E. A. Haensch , Shu-Jen Han , Chung-Hsun Lin
IPC分类号： H01L21/3205
CPC分类号： H01L21/28008 , H01L21/28052 , H01L21/28097 , H01L21/76897 , H01L29/517 , H01L29/66507 , H01L29/66545
摘要： A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer.

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