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41. 发明授权

US08203894B2 Current cancellation for non-volatile memory 有权
标题翻译：当前取消非易失性存储器
公开(公告)号：US08203894B2
公开(公告)日：2012-06-19
申请号：US13081170
申请日：2011-04-06
申请人： Chulmin Jung , Insik Jin , YoungPil Kim , Yong Lu , Harry Hongyue Liu , Andrew John Carter
发明人： Chulmin Jung , Insik Jin , YoungPil Kim , Yong Lu , Harry Hongyue Liu , Andrew John Carter
IPC分类号： G11C7/22
CPC分类号： G11C11/1673
摘要： A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns that are each controlled by a line driver. A read circuit is provided that is capable of reading a logical state of a predetermined memory cell by differentiating a non-integrated first reference value from a non-integrated second reference value. Further, each reference value is measured immediately after configuring the column corresponding to the predetermined memory cell to produce a first and second amount of current.
摘要翻译：一种用于从非易失性存储单元读取数据的方法和装置。在一些实施例中，非易失性存储器单元的交叉点阵列被布置成行和列，每个行和列都由线驱动器控制。提供读取电路，其能够通过将非积分的第一参考值与非积分的第二参考值进行微分来读取预定存储器单元的逻辑状态。此外，在配置与预定存储单元相对应的列之后立即测量每个参考值以产生第一和第二电流量。

42. 发明申请

US20120147665A1 Predictive Thermal Preconditioning and Timing Control for Non-Volatile Memory Cells 有权
标题翻译：非易失性记忆体的预测热预处理和时序控制
公开(公告)号：US20120147665A1
公开(公告)日：2012-06-14
申请号：US13400515
申请日：2012-02-20
申请人： Yiran Chen , Hai Li , Harry Hongyue Liu , Dimitar V. Dimitrov , Alan Xuguang Wang , Xiaobin Wang
发明人： Yiran Chen , Hai Li , Harry Hongyue Liu , Dimitar V. Dimitrov , Alan Xuguang Wang , Xiaobin Wang
IPC分类号： G11C11/16 , G11C7/00
CPC分类号： G11C11/1675 , G11C11/1659
摘要： Method and apparatus for using thermal preconditioning to write data to a non-volatile memory cell. In accordance with some embodiments, a semiconductor memory has an array of non-volatile memory cells, and a control circuit which stores a first write command from a host to write data to said array. A write circuit flows a write current through an unconditioned first selected cell having a first block address associated with the first write command to write the first selected cell to a selected data state, and concurrently passes a thermal preconditioning current through a second selected cell having a second block address associated with the first block address. The write circuit further passes a thermal preconditioning current through a third selected cell having a third block address associated with the second block address in response to receipt by the control circuit of a second write command from the host associated with the second block address.
摘要翻译：使用热预处理将数据写入非易失性存储单元的方法和装置。根据一些实施例，半导体存储器具有非易失性存储器单元的阵列，以及存储来自主机的第一写命令以将数据写入所述阵列的控制电路。写入电路通过具有与第一写入命令相关联的第一块地址的无条件的第一选定单元流动写入电流，以将第一选定单元写入所选择的数据状态，并且同时通过热预处理电流通过具有与第一块地址相关联的第二块地址。响应于控制电路接收到与第二块地址相关联的主机的第二写入命令，写入电路进一步传递热预处理电流通过具有与第二块地址相关联的第三块地址的第三选定单元。

43. 发明申请

US20110292716A1 Asymmetric Write Current Compensation Using Gate Overdrive for Resistive Sense Memory Cells 有权
公开(公告)号：US20110292716A1
公开(公告)日：2011-12-01
申请号：US13206749
申请日：2011-08-10
申请人： Yong Lu , Harry Hongyue Liu
发明人： Yong Lu , Harry Hongyue Liu
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C11/1659 , G11C11/1675 , G11C13/0069 , G11C2013/0071 , G11C2013/0073 , G11C2013/0078 , G11C2213/32 , G11C2213/79
摘要： Apparatus and associated method for asymmetric write current compensation for resistive sense memory (RSM) cells, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) cells. In accordance with some embodiments, an RSM cell includes an RSM element coupled to a switching device. The switching device has a plurality of terminals. A control circuit compensates for asymmetric write characteristics of the RSM cell by limiting a range of voltage differentials across the terminals so as to be equal to or less than a magnitude of a source voltage applied to the switching device, thereby providing bi-directional write currents of substantially equal magnitude through the RSM element.

44. 发明授权

US08045412B2 Multi-stage parallel data transfer 有权
标题翻译：多级并行数据传输
公开(公告)号：US08045412B2
公开(公告)日：2011-10-25
申请号：US12487165
申请日：2009-06-18
申请人： Yong Lu , Harry Hongyue Liu , Hai Li , Andrew John Carter , Daniel Reed
发明人： Yong Lu , Harry Hongyue Liu , Hai Li , Andrew John Carter , Daniel Reed
IPC分类号： G11C7/00
CPC分类号： G11C13/0064 , G11C11/1675 , G11C11/56 , G11C13/0069 , G11C2013/0078 , G11C2013/0088 , G11C2211/5622 , G11C2211/5642 , G11C2211/5643 , G11C2213/79
摘要： Apparatus and associated method for transferring data to memory, such as resistive sense memory (RSM). In accordance with some embodiments, input data comprising a sequence of logical states are transferred to a block of memory by concurrently writing a first logical state from the sequence to each of a first plurality of unit cells during a first write step, and concurrently writing a second logical state from the sequence to each of a second non-overlapping plurality of unit cells during a second write step.
摘要翻译：用于将数据传送到存储器的装置和相关方法，例如电阻读出存储器（RSM）。根据一些实施例，包括逻辑状态序列的输入数据通过在第一写入步骤期间同时向第一多个单位单元中的每个单元写入第一逻辑状态而将第一逻辑状态写入存储器块，并且同时写入在第二写入步骤期间从序列到第二非重叠多个单位单元中的每一个的第二逻辑状态。

45. 发明授权

US07936625B2 Pipeline sensing using voltage storage elements to read non-volatile memory cells 有权
标题翻译：管道感应使用电压存储元件来读取非易失性存储单元
公开(公告)号：US07936625B2
公开(公告)日：2011-05-03
申请号：US12409671
申请日：2009-03-24
申请人： Yiran Chen , Hai Li , Harry Hongyue Liu , KangYong Kim , Henry F. Huang
发明人： Yiran Chen , Hai Li , Harry Hongyue Liu , KangYong Kim , Henry F. Huang
IPC分类号： G11C7/00
CPC分类号： G11C7/1039 , G11C7/08 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C11/56 , G11C11/5607 , G11C13/00 , G11C13/004 , G11C13/0061 , G11C2013/0054
摘要： Various embodiments are generally directed to a method and apparatus for carrying out a pipeline sensing operation. In some embodiments, a read voltage from a first memory cell is stored in a voltage storage element (VSE) and compared to a reference voltage to identify a corresponding memory state of the first memory cell while a second read voltage from a second memory cell is stored in a second VSE. In other embodiments, bias currents are simultaneously applied to a first set of memory cells from the array while read voltages generated thereby are stored in a corresponding first set of VSEs. The read voltages are sequentially compared with at least one reference value to serially output a logical sequence corresponding to the memory states of the first set of memory cells while read voltages are stored for a second set of memory cells in a second set of VSEs.
摘要翻译：各种实施例通常涉及用于执行流水线检测操作的方法和装置。在一些实施例中，来自第一存储器单元的读取电压被存储在电压存储元件（VSE）中并与参考电压进行比较，以识别第一存储器单元的相应存储器状态，而来自第二存储器单元的第二读取电压为存储在第二个VSE中。在其他实施例中，偏置电流同时从阵列施加到第一组存储器单元，而由此产生的读取电压被存储在对应的第一组VSE中。读取电压与至少一个参考值顺序地比较，以串行输出对应于第一组存储器单元的存储器状态的逻辑序列，而在第二组VSE中为第二组存储器单元存储读取电压。

46. 发明授权

US07936622B2 Defective bit scheme for multi-layer integrated memory device 有权
标题翻译：多层集成存储器件的不良位方案
公开(公告)号：US07936622B2
公开(公告)日：2011-05-03
申请号：US12502194
申请日：2009-07-13
申请人： Hai Li , Yiran Chen , Dadi Setiadi , Harry Hongyue Liu , Brian Lee
发明人： Hai Li , Yiran Chen , Dadi Setiadi , Harry Hongyue Liu , Brian Lee
IPC分类号： G11C29/00
CPC分类号： G11C5/04 , G11C5/02 , G11C5/025 , G11C29/44 , G11C29/808 , G11C2029/0403
摘要： Various embodiments of the present invention are generally directed to an apparatus and associated method for handling defective bits in a multi-layer integrated memory device. In accordance with some embodiments, the multi-layer integrated memory device is formed from a plurality of vertically stacked semiconductor layers each having a number of storage sub-arrays and redundant sub-arrays. Each semiconductor layer is tested to determine a defect rate for each array, and a defective portion of a first semiconductor layer having a relatively higher defect rate is stored to a redundant sub-array of a second semiconductor layer having a relatively lower defect rate.
摘要翻译：本发明的各种实施例一般涉及用于处理多层集成存储器件中的不良位的装置和相关方法。根据一些实施例，多层集成存储器件由多个垂直堆叠的半导体层形成，每个半导体层具有多个存储子阵列和冗余子阵列。测试每个半导体层以确定每个阵列的缺陷率，并且将具有相对较高缺陷率的第一半导体层的缺陷部分存储到具有相对较低缺陷率的第二半导体层的冗余子阵列中。

47. 发明申请

US20110007597A1 Semiconductor Control Line Address Decoding Circuit 有权
标题翻译：半导体控制线地址解码电路
公开(公告)号：US20110007597A1
公开(公告)日：2011-01-13
申请号：US12502219
申请日：2009-07-13
申请人： Chulmin Jung , Dadi Setiadi , YoungPil Kim , Harry Hongyue Liu , Hyung-Kyu Lee
发明人： Chulmin Jung , Dadi Setiadi , YoungPil Kim , Harry Hongyue Liu , Hyung-Kyu Lee
IPC分类号： G11C8/10
CPC分类号： G11C8/10
摘要： Apparatus and method for decoding addresses of control lines in a semiconductor device, such as a solid state memory (SSM). In accordance with some embodiments, a switching circuit includes an array of switching devices coupled to 2N output lines and M input lines, wherein M and N are respective non-zero integers and each output line has a unique N-bit address. A decoder circuit coupled to the switching circuit divides the N-bit address for a selected output line into a plurality of multi-bit subgroup addresses, and asserts the M input lines in relation to respective bit values of said subgroup addresses to apply a first voltage to the selected output line and to concurrently apply a second voltage to the remaining 2N-1 output lines.
摘要翻译：用于解码诸如固态存储器（SSM）的半导体器件中的控制线的地址的装置和方法。根据一些实施例，开关电路包括耦合到2N个输出线和M个输入线的开关器件阵列，其中M和N分别是非零整数，并且每个输出线具有唯一的N位地址。耦合到开关电路的解码器电路将所选择的输出线的N位地址划分为多个多位子组地址，并且相对于所述子组地址的各个位值断言M个输入线，以施加第一电压并且向剩余的2N-1个输出线同时施加第二电压。

48. 发明申请

US20100302849A1 NAND FLASH MEMORY WITH INTEGRATED BIT LINE CAPACITANCE 有权
标题翻译：具有集成位线电容的NAND闪存
公开(公告)号：US20100302849A1
公开(公告)日：2010-12-02
申请号：US12474463
申请日：2009-05-29
申请人： Chulmin Jung , Harry Hongyue Liu , Brian Lee , Yong Lu , Dadi Setiadi
发明人： Chulmin Jung , Harry Hongyue Liu , Brian Lee , Yong Lu , Dadi Setiadi
IPC分类号： G11C14/00 , G11C16/04
CPC分类号： G11C11/005 , G11C16/26 , G11C2216/14
摘要： Method and apparatus for outputting data from a memory array having a plurality of non-volatile memory cells arranged into rows and columns. In accordance with various embodiments, charge is stored in a volatile memory cell connected to the memory array, and the stored charge is subsequently discharged from the volatile memory cell through a selected column. In some embodiments, the volatile memory cell is a dynamic random access memory (DRAM) cell from a row of said cells with each DRAM cell along the row coupled to a respective column in the memory array, and each column of non-volatile memory cells comprises Flash memory cells connected in a NAND configuration.
摘要翻译：用于从具有排列成行和列的多个非易失性存储单元的存储器阵列输出数据的方法和装置。根据各种实施例，电荷被存储在连接到存储器阵列的易失性存储单元中，并且随后通过所选择的列从易失性存储器单元中释放存储的电荷。在一些实施例中，易失性存储器单元是来自所述单元的行的动态随机存取存储器（DRAM）单元，其中每个DRAM单元沿着与存储器阵列中的相应列耦合的行，并且每列非易失性存储单元包括以NAND配置连接的闪存单元。

49. 发明申请

US20100246250A1 Pipeline Sensing Using Voltage Storage Elements to Read Non-Volatile Memory Cells 有权
标题翻译：使用电压存储元件读取非易失性存储单元的管道感应
公开(公告)号：US20100246250A1
公开(公告)日：2010-09-30
申请号：US12409671
申请日：2009-03-24
申请人： Yiran Chen , Hai Li , Harry Hongyue Liu , KangYong Kim , Henry F. Huang
发明人： Yiran Chen , Hai Li , Harry Hongyue Liu , KangYong Kim , Henry F. Huang
IPC分类号： G11C11/14 , G11C7/00
CPC分类号： G11C7/1039 , G11C7/08 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C11/56 , G11C11/5607 , G11C13/00 , G11C13/004 , G11C13/0061 , G11C2013/0054
摘要： Various embodiments are generally directed to a method and apparatus for carrying out a pipeline sensing operation. In some embodiments, a read voltage from a first memory cell is stored in a voltage storage element (VSE) and compared to a reference voltage to identify a corresponding memory state of the first memory cell while a second read voltage from a second memory cell is stored in a second VSE. In other embodiments, bias currents are simultaneously applied to a first set of memory cells from the array while read voltages generated thereby are stored in a corresponding first set of VSEs. The read voltages are sequentially compared with at least one reference value to serially output a logical sequence corresponding to the memory states of the first set of memory cells while read voltages are stored for a second set of memory cells in a second set of VSEs.
摘要翻译：各种实施例通常涉及用于执行流水线检测操作的方法和装置。在一些实施例中，来自第一存储器单元的读取电压被存储在电压存储元件（VSE）中并与参考电压进行比较，以识别第一存储器单元的相应存储器状态，而来自第二存储器单元的第二读取电压为存储在第二个VSE中。在其他实施例中，偏置电流同时从阵列施加到第一组存储器单元，而由此产生的读取电压被存储在对应的第一组VSE中。读取电压与至少一个参考值顺序地比较，以串行输出对应于第一组存储器单元的存储器状态的逻辑序列，而在第二组VSE中为第二组存储器单元存储读取电压。

50. 发明申请

US20100177562A1 COMPUTER MEMORY DEVICE WITH MULTIPLE INTERFACES 有权
标题翻译：具有多个接口的计算机存储器件
公开(公告)号：US20100177562A1
公开(公告)日：2010-07-15
申请号：US12352713
申请日：2009-01-13
申请人： Yiran Chen , Daniel S. Reed , Yong Lu , Harry Hongyue Liu , Hai Li , Rod V. Bowman
发明人： Yiran Chen , Daniel S. Reed , Yong Lu , Harry Hongyue Liu , Hai Li , Rod V. Bowman
IPC分类号： G11C11/14 , G11C7/00
CPC分类号： G11C11/22
摘要： Various embodiments are generally directed to a method and apparatus associated with operating a first memory device with multiple interfaces and a status register. In some embodiments, a first interface is engaged by a host. A memory device that has a plurality of memory cells comprised of at least a magnetic tunneling junction and a spin polarizing magnetic material is connected to a second interface. A status register is maintained by logging at least an error or busy signal during data transfer operations through the first and second interfaces.
摘要翻译：各种实施例通常涉及与操作具有多个接口和状态寄存器的第一存储器件相关联的方法和装置。在一些实施例中，主机接合第一接口。具有由至少磁性隧道结和自旋极化磁性材料构成的多个存储单元的存储器件连接到第二接口。通过在数据传输操作期间通过第一和第二接口记录至少一个错误或忙信号来维护状态寄存器。

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