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1. 发明授权

US08363449B2 Floating source line architecture for non-volatile memory 有权
标题翻译：用于非易失性存储器的浮动源线架构
公开(公告)号：US08363449B2
公开(公告)日：2013-01-29
申请号：US13206550
申请日：2011-08-10
申请人： Chulmin Jung , Yong Lu , Harry Hongyue Liu
发明人： Chulmin Jung , Yong Lu , Harry Hongyue Liu
IPC分类号： G11C11/00
CPC分类号： G11C13/0002 , G11C7/12 , G11C11/16 , G11C11/1673 , G11C11/1675 , G11C13/0069
摘要： A method and apparatus for writing data to a non-volatile memory cell, such as an STRAM memory cell or an RRAM memory cell. In some embodiments, a plurality of N non-volatile memory cells, where N is a greater than two, are connected to a common floating source line. A write circuit is adapted to program a selected memory cell of the plurality to a selected data state by passing a write current of selected magnitude through the selected memory cell and concurrently passing a portion of the write current in parallel through each of the remaining N−1 memory cells of the plurality via the common floating source line.
摘要翻译：用于将数据写入诸如STRAM存储器单元或RRAM存储器单元的非易失性存储单元的方法和装置。在一些实施例中，其中N大于2的多个N个非易失性存储器单元连接到公共的浮动源线。写入电路适于通过将所选择的大小的写入电流通过所选择的存储器单元来编程所选择的数据状态的所选择的存储单元，并且并行地通过所述剩余的N- 1个存储单元经由公共浮动源线。

2. 发明授权

US08004872B2 Floating source line architecture for non-volatile memory 有权
标题翻译：用于非易失性存储器的浮动源线架构
公开(公告)号：US08004872B2
公开(公告)日：2011-08-23
申请号：US12272507
申请日：2008-11-17
申请人： Chulmin Jung , Yong Lu , Harry Hongyue Liu
发明人： Chulmin Jung , Yong Lu , Harry Hongyue Liu
IPC分类号： G11C11/10
CPC分类号： G11C13/0002 , G11C7/12 , G11C11/16 , G11C11/1673 , G11C11/1675 , G11C13/0069
摘要： A method and apparatus for writing data to a non-volatile memory cell, such as an RRAM memory cell. In some embodiments, a semiconductor array of non-volatile memory cells comprises a resistive sense element (RSE) and a switching device. A RSE of a plurality of memory cells is connected to a bit line while the switching device of a plurality of memory cells is connected to a word line and operated to select a memory cell. A source line is connected to the switching device and connects a series of memory cells together. Further, a driver circuit is connected to the bit line and writes a selected RSE of a selected source line to a selected resistive state by passing a write current along a write current path that passes through the selected RSE and through at least a portion of the remaining RSE connected to the selected source line.
摘要翻译：一种将数据写入诸如RRAM存储单元的非易失性存储单元的方法和装置。在一些实施例中，非易失性存储单元的半导体阵列包括电阻感测元件（RSE）和开关器件。多个存储单元的RSE连接到位线，而多个存储单元的开关器件连接到字线并被操作以选择存储器单元。源极线连接到开关器件，并将一系列存储器单元连接在一起。此外，驱动器电路连接到位线，并且通过使写入电流沿着通过所选择的RSE的写入电流路径并且通过至少一部分所述选择的RSE而将所选择的源极线的选定RSE写入所选择的电阻状态剩余的RSE连接到所选择的源线。

3. 发明申请

US20110194337A1 Non-Volatile Memory Cell With Precessional Switching 有权
标题翻译：具有进动切换的非易失性存储单元
公开(公告)号：US20110194337A1
公开(公告)日：2011-08-11
申请号：US13091372
申请日：2011-04-21
申请人： Xiaobin Wang , Yong Lu , Haiwen Xi , Yuankai Zheng , Yiran Chen , Harry Hongyue Liu , Dimitar Dimitrov , Wei Tian , Brian Seungwhan Lee
发明人： Xiaobin Wang , Yong Lu , Haiwen Xi , Yuankai Zheng , Yiran Chen , Harry Hongyue Liu , Dimitar Dimitrov , Wei Tian , Brian Seungwhan Lee
IPC分类号： G11C11/00
CPC分类号： H01F10/329 , B82Y25/00 , G06F7/588 , G11C11/161 , G11C11/1675 , G11C11/1677 , G11C11/1693 , H01F10/3254 , H01F10/3286
摘要： A method and apparatus for writing data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a selected resistive state is written to a magnetic tunneling structure by applying a succession of indeterminate write pulses thereto until the selected resistive state is verified.
摘要翻译：一种将数据写入非易失性存储单元的方法和装置，例如自旋转矩传递随机存取存储器（STRAM）存储单元。在一些实施例中，通过将一系列不确定的写入脉冲施加到磁性隧道结构中来将所选择的电阻状态写入到所选择的电阻状态。

4. 发明授权

US07936592B2 Non-volatile memory cell with precessional switching 有权
标题翻译：具有进动切换的非易失性存储单元
公开(公告)号：US07936592B2
公开(公告)日：2011-05-03
申请号：US12364589
申请日：2009-02-03
申请人： Xiaobin Wang , Yong Lu , Haiwen Xi , Yuankai Zheng , Yiran Chen , Harry Hongyue Liu , Dimitar Dimitrov , Wei Tan , Brian Seungwhan Lee
发明人： Xiaobin Wang , Yong Lu , Haiwen Xi , Yuankai Zheng , Yiran Chen , Harry Hongyue Liu , Dimitar Dimitrov , Wei Tan , Brian Seungwhan Lee
IPC分类号： G11C11/00
CPC分类号： H01F10/329 , B82Y25/00 , G06F7/588 , G11C11/161 , G11C11/1675 , G11C11/1677 , G11C11/1693 , H01F10/3254 , H01F10/3286
摘要： A method and apparatus for writing data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a selected resistive state is written to a magnetic tunneling structure by applying a succession of indeterminate write pulses thereto until the selected resistive state is verified.
摘要翻译：一种将数据写入非易失性存储单元的方法和装置，例如自旋转矩传递随机存取存储器（STRAM）存储单元。在一些实施例中，通过将一系列不确定的写入脉冲施加到磁性隧道结构中来将所选择的电阻状态写入到所选择的电阻状态。

5. 发明申请

US20110029714A1 RESISTIVE SENSE MEMORY ARRAY WITH PARTIAL BLOCK UPDATE CAPABILITY 有权
标题翻译：具有部分块更新能力的电阻式感知存储器阵列
公开(公告)号：US20110029714A1
公开(公告)日：2011-02-03
申请号：US12904653
申请日：2010-10-14
申请人： Yiran Chen , Daniel S. Reed , Yong Lu , Harry Hongyue Liu , Hai Li
发明人： Yiran Chen , Daniel S. Reed , Yong Lu , Harry Hongyue Liu , Hai Li
IPC分类号： G06F12/00 , G11C11/21 , G11C11/16
CPC分类号： G11C8/12 , G11C11/1653 , G11C11/1673 , G11C11/1675 , G11C13/0007 , G11C13/0069 , G11C2013/0088 , G11C2013/009 , G11C2213/32 , G11C2213/34 , G11C2213/79
摘要： Various embodiments of the present invention are generally directed to a method and apparatus for carrying out a partial block update operation upon a resistive sense memory (RSM) array, such as formed from STRAM or RRAM cells. The RSM array is arranged into multi-cell blocks (sectors), each block having a physical block address (PBA). A first set of user data is written to a selected block at a first PBA. A partial block update operation is performed by writing a second set of user data to a second block at a second PBA, the second set of user data updating a portion of the first set of user data in the first PBA. The first and second blocks are thereafter read to retrieve the second set of user data and a remaining portion of the first set of user data.
摘要翻译：本发明的各种实施例总体上涉及一种用于在诸如由STRAM或RRAM单元形成的电阻式感测存储器（RSM）阵列上执行部分块更新操作的方法和装置。 RSM阵列被布置成多小区块（扇区），每个块具有物理块地址（PBA）。第一组用户数据在第一PBA被写入所选择的块。通过在第二PBA将第二组用户数据写入第二块来执行部分块更新操作，第二组用户数据更新第一PBA中第一组用户数据的一部分。然后读取第一和第二块以检索第二组用户数据和第一组用户数据的剩余部分。

6. 发明授权

US07830708B1 Compensating for variations in memory cell programmed state distributions 有权
标题翻译：补偿存储单元编程状态分布的变化
公开(公告)号：US07830708B1
公开(公告)日：2010-11-09
申请号：US12428002
申请日：2009-04-22
申请人： Chulmin Jung , Yong Lu , Harry Hongyue Liu
发明人： Chulmin Jung , Yong Lu , Harry Hongyue Liu
IPC分类号： G11C16/00
CPC分类号： G11C11/5642 , G11C16/0483 , G11C2211/5631 , G11C2211/5632
摘要： Method and apparatus for compensating for variations in memory cell programmed state distributions, such as but not limited to a non-volatile memory formed of NAND configured Flash memory cells. In accordance with various embodiments, a memory block is formed from a plurality of memory cells that are arranged into rows and columns within the memory block, each memory cell configured to have a programmed state. A selected row of the memory block is read by concurrently applying a stepped sequence of threshold voltages to each memory cell along the selected row while sequentially decoupling read current from groups of memory cells along the selected row as the programmed states of said groups of cells are successively determined.
摘要翻译：用于补偿存储器单元编程状态分布的变化的方法和装置，例如但不限于由NAND配置的闪存单元形成的非易失性存储器。根据各种实施例，存储器块由多个存储器单元形成，多个存储器单元被布置成存储器块内的行和列，每个存储器单元被配置为具有编程状态。存储器块的选定行通过沿着所选择的行并行地向每个存储器单元施加阶梯式序列来读取，同时沿着所选行的顺序地将读取电流与存储器单元组分离，因为所述单元组的编程状态为先后确定。

7. 发明申请

US20100177551A1 BIT SET MODES FOR A RESISTIVE SENSE MEMORY CELL ARRAY 有权
标题翻译：用于电阻式感应存储器单元阵列的位设置模式
公开(公告)号：US20100177551A1
公开(公告)日：2010-07-15
申请号：US12352693
申请日：2009-01-13
申请人： Yiran Chen , Daniel S. Reed , Yong Lu , Harry Hongyue Liu , Hai Li , Rod V. Bowman
发明人： Yiran Chen , Daniel S. Reed , Yong Lu , Harry Hongyue Liu , Hai Li , Rod V. Bowman
IPC分类号： G11C11/00 , G11C11/416
CPC分类号： G11C11/16 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/5685 , G11C13/0007 , G11C13/0026 , G11C13/0069
摘要： Various embodiments of the present invention are generally directed to a method and apparatus for providing different bit set modes for a resistive sense memory (RSM) array, such as a spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) array. In accordance with some embodiments, a group of RSM cells in a non-volatile semiconductor memory array is identified for application of a bit set operation. A bit set value is selected from a plurality of bit set values each separately writable to the RSM cells to place said cells in a selected resistive state. The selected bit set value is thereafter written to at least a portion of the RSM cells in the identified group.
摘要翻译：本发明的各种实施例一般涉及一种用于为电阻式感测存储器（RSM）阵列提供不同的比特设置模式的方法和装置，诸如自旋转矩传递随机存取存储器（STRAM）或电阻随机存取存储器（RRAM））数组。根据一些实施例，识别非易失性半导体存储器阵列中的一组RSM单元用于位设置操作的应用。从对RSM单元分别写入的多个位设置值中选择位设置值，以将所述单元置于选择的电阻状态。所选位设定值此后被写入所识别的组中的RSM单元的至少一部分。

8. 发明申请

US20100118602A1 DOUBLE SOURCE LINE-BASED MEMORY ARRAY AND MEMORY CELLS THEREOF 审中-公开
标题翻译：基于线路的双重存储器阵列和存储器单元
公开(公告)号：US20100118602A1
公开(公告)日：2010-05-13
申请号：US12270056
申请日：2008-11-13
申请人： Andrew John Carter , Yiran Chen , Yong Lu , Harry Hongyue Liu
发明人： Andrew John Carter , Yiran Chen , Yong Lu , Harry Hongyue Liu
IPC分类号： G11C11/14
CPC分类号： G11C5/063 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C2213/72 , G11C2213/74
摘要： A memory array includes a plurality of first and second source, lines overlapping a plurality of bit lines, and a plurality of magnetic storage elements, each coupled to a corresponding first and second source line and to a corresponding bit line. Current may be driven, in first and second directions, through each magnetic element, for example, to program the elements. Diodes may be incorporated to avert sneak paths in the memory array. A first diode may be coupled between each magnetic element and the corresponding first source line, the first diode being biased to allow read and write current flow through the magnetic element, from the corresponding first source line; and a second diode may be coupled between each magnetic element and the corresponding second source line, the second diode being reverse-biased to block read and write current flow through the magnetic element, from the corresponding second source line.
摘要翻译：存储器阵列包括多个第一和第二源，与多个位线重叠的线，以及多个磁存储元件，每个磁存储元件分别耦合到对应的第一和第二源极线以及相应的位线。电流可以在第一和第二方向上通过每个磁性元件被驱动，例如编程元件。可以并入二极管以避免存储器阵列中的潜行路径。第一二极管可以耦合在每个磁性元件和对应的第一源极线之间，第一二极管被偏置以允许读取和写入电流从相应的第一源极线流过磁性元件; 并且第二二极管可以耦合在每个磁性元件和对应的第二源极线之间，所述第二二极管被反向偏置以阻挡从对应的第二源极线读取和写入通过磁性元件的电流。

9. 发明授权

US08125819B2 Asymmetric write current compensation using gate overdrive for resistive sense memory cells 有权
公开(公告)号：US08125819B2
公开(公告)日：2012-02-28
申请号：US13206749
申请日：2011-08-10
申请人： Yong Lu , Harry Hongyue Liu
发明人： Yong Lu , Harry Hongyue Liu
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C11/1659 , G11C11/1675 , G11C13/0069 , G11C2013/0071 , G11C2013/0073 , G11C2013/0078 , G11C2213/32 , G11C2213/79
摘要： Apparatus and associated method for asymmetric write current compensation for resistive sense memory (RSM) cells, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) cells. In accordance with some embodiments, an RSM cell includes an RSM element coupled to a switching device. The switching device has a plurality of terminals. A control circuit compensates for asymmetric write characteristics of the RSM cell by limiting a range of voltage differentials across the terminals so as to be equal to or less than a magnitude of a source voltage applied to the switching device, thereby providing bi-directional write currents of substantially equal magnitude through the RSM element.

10. 发明申请

US20120039112A1 Hierarchical Cross-Point Array of Non-Volatile Memory 有权
标题翻译：非易失性存储器的分层交叉点阵列
公开(公告)号：US20120039112A1
公开(公告)日：2012-02-16
申请号：US13280109
申请日：2011-10-24
申请人： Chulmin Jung , Yong Lu , Insik Jin , YoungPil Kim , Harry Hongyue Liu
发明人： Chulmin Jung , Yong Lu , Insik Jin , YoungPil Kim , Harry Hongyue Liu
IPC分类号： G11C11/00
CPC分类号： A01H6/14 , A01H5/02
摘要： A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns. A selection circuit is provided that is capable of activating the first block of memory cells while deactivating the second block of memory cells. Further, a read circuit is provided that is capable of reading a logical state of a predetermined memory cell in the first block of memory cells with a reduced leak current by programming a first resistive state to the block selection elements corresponding to the first block of memory cells while programming a second resistive state to the block selection elements corresponding to the second block of memory cells.
摘要翻译：一种用于从非易失性存储单元读取数据的方法和装置。在一些实施例中，非易失性存储器单元的交叉点阵列被布置成行和列。提供了选择电路，其能够在禁用第二存储单元块的同时激活存储器单元的第一块。此外，提供一种读取电路，其能够通过对与第一存储器块相对应的块选择元件编程第一电阻状态，以减小的漏电流来读取存储器单元的第一块中的预定存储器单元的逻辑状态同时将第二电阻状态编程到对应于存储器单元的第二块的块选择元件。

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