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1. 发明申请

US20100177562A1 COMPUTER MEMORY DEVICE WITH MULTIPLE INTERFACES 有权
标题翻译：具有多个接口的计算机存储器件
公开(公告)号：US20100177562A1
公开(公告)日：2010-07-15
申请号：US12352713
申请日：2009-01-13
申请人： Yiran Chen , Daniel S. Reed , Yong Lu , Harry Hongyue Liu , Hai Li , Rod V. Bowman
发明人： Yiran Chen , Daniel S. Reed , Yong Lu , Harry Hongyue Liu , Hai Li , Rod V. Bowman
IPC分类号： G11C11/14 , G11C7/00
CPC分类号： G11C11/22
摘要： Various embodiments are generally directed to a method and apparatus associated with operating a first memory device with multiple interfaces and a status register. In some embodiments, a first interface is engaged by a host. A memory device that has a plurality of memory cells comprised of at least a magnetic tunneling junction and a spin polarizing magnetic material is connected to a second interface. A status register is maintained by logging at least an error or busy signal during data transfer operations through the first and second interfaces.
摘要翻译：各种实施例通常涉及与操作具有多个接口和状态寄存器的第一存储器件相关联的方法和装置。在一些实施例中，主机接合第一接口。具有由至少磁性隧道结和自旋极化磁性材料构成的多个存储单元的存储器件连接到第二接口。通过在数据传输操作期间通过第一和第二接口记录至少一个错误或忙信号来维护状态寄存器。

2. 发明申请

US20100095050A1 COMPUTER MEMORY DEVICE WITH STATUS REGISTER 有权
标题翻译：具有状态寄存器的计算机存储器件
公开(公告)号：US20100095050A1
公开(公告)日：2010-04-15
申请号：US12252170
申请日：2008-10-15
申请人： Yiran Chen , Daniel S. Reed , Yong Lu , Hongyue Liu , Hai Li
发明人： Yiran Chen , Daniel S. Reed , Yong Lu , Hongyue Liu , Hai Li
IPC分类号： G06F12/02
CPC分类号： G11C7/24 , G11C5/143 , G11C11/16 , G11C13/0002
摘要： Method and apparatus for operating a memory device with a status register. In some embodiments, the memory device has a plurality of individually programmable non-volatile memory cells comprised of at least a resistive sense memory. The memory device engages an interface and maintains a status register in some embodiments by logging at least an error or busy signal during data transfer operations.
摘要翻译：用于操作具有状态寄存器的存储器件的方法和装置。在一些实施例中，存储器件具有由至少电阻式感测存储器组成的多个单独可编程的非易失性存储器单元。在一些实施例中，存储器装置接合接口并维持状态寄存器，在数据传输操作期间至少记录错误或忙信号。

3. 发明授权

US08213259B2 Non-volatile memory cell with resistive sense element block erase and uni-directional write 有权
标题翻译：具有电阻感测元件块擦除和单向写入的非易失性存储单元
公开(公告)号：US08213259B2
公开(公告)日：2012-07-03
申请号：US12903011
申请日：2010-10-12
申请人： Daniel S. Reed , Yong Lu , Andrew John Carter , Hai Li
发明人： Daniel S. Reed , Yong Lu , Andrew John Carter , Hai Li
IPC分类号： G11C7/12 , G11C8/08 , G11C11/21 , G11C11/02 , G11C7/22
CPC分类号： G11C13/0097 , G11C11/1659 , G11C11/1675 , G11C13/0004 , G11C13/0011 , G11C13/003 , G11C13/0069 , G11C2013/009 , G11C2213/76
摘要： A non-volatile memory cell and associated method of use. In accordance with some embodiments, the memory cell includes a transistor comprising source and drain regions spanned by a gate region, and a resistive sense element (RSE) connected to the drain region of the transistor. The RSE is programmed to a first resistance by flowing a first write current through the RSE and then through the drain and source regions of the transistor. The RSE is programmed to a second resistance by flowing a second write current through the drain region and then through the RSE, the second write current bypassing the source region.
摘要翻译：非易失性存储单元及相关联的使用方法。根据一些实施例，存储器单元包括晶体管，其包括由栅极区域跨越的源极和漏极区域，以及连接到晶体管的漏极区域的电阻感测元件（RSE）。通过使第一写入电流流过RSE然后通过晶体管的漏极和源极区域将RSE编程为第一电阻。通过使第二写入电流流经漏极区域，然后通过RSE，将第二电阻编程为第二电阻，第二写入电流绕过源极区域。

4. 发明授权

US07885097B2 Non-volatile memory array with resistive sense element block erase and uni-directional write 有权
标题翻译：具有电阻感测元件块擦除和单向写入的非易失性存储器阵列
公开(公告)号：US07885097B2
公开(公告)日：2011-02-08
申请号：US12501077
申请日：2009-07-10
申请人： Daniel S. Reed , Yong Lu , Andrew John Carter , Hai Li
发明人： Daniel S. Reed , Yong Lu , Andrew John Carter , Hai Li
IPC分类号： G11C7/12 , G11C8/12 , G11C11/16 , G11C11/02 , G11C11/14
CPC分类号： G11C13/0097 , G11C11/1659 , G11C11/1675 , G11C13/0004 , G11C13/0011 , G11C13/003 , G11C13/0069 , G11C2013/009 , G11C2213/76
摘要： In accordance with various embodiments, a column of non-volatile memory cells is connected between opposing first and second control lines. A fixed reference voltage is applied to the second control line. The memory cells are simultaneously programmed to a first resistive state by applying a first voltage to the first control line that is greater than the fixed reference voltage. Less than all of the memory cells are subsequently simultaneously programmed to a different, second resistive state by applying a second voltage to the first control line that is less than the fixed reference voltage, so that at the conclusion of the respective programming steps a first portion of the memory cells along said column are at the first resistive state and a second portion of the memory cells along said column are at the second resistive state.
摘要翻译：根据各种实施例，一列非易失性存储单元连接在相对的第一和第二控制线之间。将固定的参考电压施加到第二控制线。通过向第一控制线施加大于固定参考电压的第一电压，将存储单元同时编程为第一电阻状态。随后通过向小于固定参考电压的第一控制线施加第二电压而将小于所有存储单元的数据同时编程为不同的第二电阻状态，使得在相应编程步骤结束时，第一部分沿着所述列的存储器单元处于第一电阻状态，并且沿着所述列的存储单元的第二部分处于第二电阻状态。

5. 发明申请

US20110029714A1 RESISTIVE SENSE MEMORY ARRAY WITH PARTIAL BLOCK UPDATE CAPABILITY 有权
标题翻译：具有部分块更新能力的电阻式感知存储器阵列
公开(公告)号：US20110029714A1
公开(公告)日：2011-02-03
申请号：US12904653
申请日：2010-10-14
申请人： Yiran Chen , Daniel S. Reed , Yong Lu , Harry Hongyue Liu , Hai Li
发明人： Yiran Chen , Daniel S. Reed , Yong Lu , Harry Hongyue Liu , Hai Li
IPC分类号： G06F12/00 , G11C11/21 , G11C11/16
CPC分类号： G11C8/12 , G11C11/1653 , G11C11/1673 , G11C11/1675 , G11C13/0007 , G11C13/0069 , G11C2013/0088 , G11C2013/009 , G11C2213/32 , G11C2213/34 , G11C2213/79
摘要： Various embodiments of the present invention are generally directed to a method and apparatus for carrying out a partial block update operation upon a resistive sense memory (RSM) array, such as formed from STRAM or RRAM cells. The RSM array is arranged into multi-cell blocks (sectors), each block having a physical block address (PBA). A first set of user data is written to a selected block at a first PBA. A partial block update operation is performed by writing a second set of user data to a second block at a second PBA, the second set of user data updating a portion of the first set of user data in the first PBA. The first and second blocks are thereafter read to retrieve the second set of user data and a remaining portion of the first set of user data.
摘要翻译：本发明的各种实施例总体上涉及一种用于在诸如由STRAM或RRAM单元形成的电阻式感测存储器（RSM）阵列上执行部分块更新操作的方法和装置。 RSM阵列被布置成多小区块（扇区），每个块具有物理块地址（PBA）。第一组用户数据在第一PBA被写入所选择的块。通过在第二PBA将第二组用户数据写入第二块来执行部分块更新操作，第二组用户数据更新第一PBA中第一组用户数据的一部分。然后读取第一和第二块以检索第二组用户数据和第一组用户数据的剩余部分。

6. 发明申请

US20100177551A1 BIT SET MODES FOR A RESISTIVE SENSE MEMORY CELL ARRAY 有权
标题翻译：用于电阻式感应存储器单元阵列的位设置模式
公开(公告)号：US20100177551A1
公开(公告)日：2010-07-15
申请号：US12352693
申请日：2009-01-13
申请人： Yiran Chen , Daniel S. Reed , Yong Lu , Harry Hongyue Liu , Hai Li , Rod V. Bowman
发明人： Yiran Chen , Daniel S. Reed , Yong Lu , Harry Hongyue Liu , Hai Li , Rod V. Bowman
IPC分类号： G11C11/00 , G11C11/416
CPC分类号： G11C11/16 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/5685 , G11C13/0007 , G11C13/0026 , G11C13/0069
摘要： Various embodiments of the present invention are generally directed to a method and apparatus for providing different bit set modes for a resistive sense memory (RSM) array, such as a spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) array. In accordance with some embodiments, a group of RSM cells in a non-volatile semiconductor memory array is identified for application of a bit set operation. A bit set value is selected from a plurality of bit set values each separately writable to the RSM cells to place said cells in a selected resistive state. The selected bit set value is thereafter written to at least a portion of the RSM cells in the identified group.
摘要翻译：本发明的各种实施例一般涉及一种用于为电阻式感测存储器（RSM）阵列提供不同的比特设置模式的方法和装置，诸如自旋转矩传递随机存取存储器（STRAM）或电阻随机存取存储器（RRAM））数组。根据一些实施例，识别非易失性半导体存储器阵列中的一组RSM单元用于位设置操作的应用。从对RSM单元分别写入的多个位设置值中选择位设置值，以将所述单元置于选择的电阻状态。所选位设定值此后被写入所识别的组中的RSM单元的至少一部分。

7. 发明申请

US20100091548A1 Non-Volatile Memory Array with Resistive Sense Element Block Erase and Uni-Directional Write 有权
标题翻译：具有电阻感应元件块擦除和单向写入的非易失性存储器阵列
公开(公告)号：US20100091548A1
公开(公告)日：2010-04-15
申请号：US12501077
申请日：2009-07-10
申请人： Daniel S. Reed , Yong Lu , Andrew John Carter , Hai Li
发明人： Daniel S. Reed , Yong Lu , Andrew John Carter , Hai Li
IPC分类号： G11C11/00 , G11C11/14 , G11C7/00
CPC分类号： G11C13/0097 , G11C11/1659 , G11C11/1675 , G11C13/0004 , G11C13/0011 , G11C13/003 , G11C13/0069 , G11C2013/009 , G11C2213/76
摘要： A non-volatile memory cell and associated method of use are disclosed. In accordance with various embodiments, the memory cell includes a switching device and a resistive sense element (RSE) connected in series between first and second control lines. The first control line is supplied with a variable voltage and the second control line is maintained at a fixed reference voltage. A first resistive state of the RSE is programmed by lowering the variable voltage of the first control line below the fixed reference voltage of the second control line to flow a body-drain current through the switching device. A different, second resistive state of the RSE is programmed by raising the variable voltage of the first control line above the fixed reference voltage to flow a drain-source current through the switching device.
摘要翻译：公开了一种非易失性存储单元及其相关使用方法。根据各种实施例，存储单元包括串联连接在第一和第二控制线之间的开关装置和电阻感测元件（RSE）。第一控制线被提供可变电压，第二控制线保持在固定的参考电压。 RSE的第一电阻状态通过将第一控制线的可变电压降低到第二控制线的固定参考电压以下来编程，以使体电流流过开关器件。 RSE的不同的第二电阻状态通过将第一控制线的可变电压升高到固定参考电压以上而使漏源电流流过开关器件来编程。

8. 发明授权

US07474569B2 Two-element magnetic memory cell 有权
标题翻译：双元磁记忆体
公开(公告)号：US07474569B2
公开(公告)日：2009-01-06
申请号：US11440966
申请日：2006-05-25
申请人： Daniel S. Reed
发明人： Daniel S. Reed
IPC分类号： G11C7/00
CPC分类号： G11C11/15
摘要： A magnetic memory cell that includes at least two magnetoresistive memory bits is presented. The memory cell is capable of storing at least two logical states. The first logical state occurs when the bits share the same orientation, such as a parallel orientation or an antiparallel orientation. The second logical state occurs when the bits have opposite orientations. In the second logical state one of the bits has a parallel orientation and the other bit has an antiparallel orientation.
摘要翻译：提出了包括至少两个磁阻存储器位的磁存储单元。存储器单元能够存储至少两个逻辑状态。当位共享相同的方向时，例如平行取向或反平行方向，发生第一逻辑状态。当位具有相反的方向时，发生第二逻辑状态。在第二逻辑状态中，位之一具有并行取向，而另一位具有反平行取向。

9. 发明授权

US07383626B2 Methods for fabricating giant magnetoresistive (GMR) devices 失效
标题翻译：制造巨磁阻（GMR）器件的方法
公开(公告)号：US07383626B2
公开(公告)日：2008-06-10
申请号：US11508671
申请日：2006-08-22
申请人： Daniel L. Baseman , Lonny L. Berg , Romney R. Katti , Daniel S. Reed , Gordon A. Shaw , Wei D. Z. Zou
发明人： Daniel L. Baseman , Lonny L. Berg , Romney R. Katti , Daniel S. Reed , Gordon A. Shaw , Wei D. Z. Zou
IPC分类号： G11B5/127 , H04R31/00
CPC分类号： G11C11/16 , G11B5/39 , H01L43/12 , Y10T29/49032 , Y10T29/49041 , Y10T29/49043 , Y10T29/49044 , Y10T29/49046 , Y10T29/49048 , Y10T29/49052 , Y10T29/49155
摘要： In a method of fabricating a giant magnetoresistive (GMR) device a plurality of magnetoresistive device layers is deposited on a first silicon nitride layer formed on a silicon oxide layer. An etch stop is formed on the magnetoresistive device layers, and a second layer of silicon nitride is formed on the etch stop. The magnetoresistive device layers are patterned to define a plurality of magnetic bits having sidewalls. The second silicon nitride layer is patterned to define electrical contact portions on the etch stop in each magnetic bit. The sidewalls of the magnetic bits are covered with a photoresist layer. A reactive ion etch (RIE) process is used to etch into the first silicon nitride and silicon oxide layers to expose electrical contacts. The photoresist layer and silicon nitride layers protect the magnetoresistive layers from exposure to oxygen during the etching into the silicon oxide layer.
摘要翻译：在制造巨磁阻（GMR）器件的方法中，多个磁阻器件层沉积在形成于氧化硅层上的第一氮化硅层上。在磁阻器件层上形成蚀刻停止层，在蚀刻停止层上形成第二氮化硅层。图案化磁阻器件层以限定具有侧壁的多个磁性位。将第二氮化硅层图案化以限定每个磁头中蚀刻停止点上的电接触部分。磁头的侧壁被光致抗蚀剂层覆盖。使用反应离子蚀刻（RIE）工艺来蚀刻到第一氮化硅和氧化硅层中以暴露电触点。在蚀刻到氧化硅层期间，光致抗蚀剂层和氮化硅层保护磁阻层免受暴露于氧气。

10. 发明授权

US07114240B2 Method for fabricating giant magnetoresistive (GMR) devices 失效
标题翻译：制造巨磁阻（GMR）器件的方法
公开(公告)号：US07114240B2
公开(公告)日：2006-10-03
申请号：US10706531
申请日：2003-11-12
申请人： Daniel L. Baseman , Lonny L. Berg , Romney R. Katti , Daniel S. Reed , Gordon A. Shaw , Wei D. Z. Zou
发明人： Daniel L. Baseman , Lonny L. Berg , Romney R. Katti , Daniel S. Reed , Gordon A. Shaw , Wei D. Z. Zou
IPC分类号： G11B5/127 , H04R31/00
CPC分类号： G11C11/16 , G11B5/39 , H01L43/12 , Y10T29/49032 , Y10T29/49041 , Y10T29/49043 , Y10T29/49044 , Y10T29/49046 , Y10T29/49048 , Y10T29/49052 , Y10T29/49155
摘要： In a method of fabricating a giant magnetoresistive (GMR) device a plurality of magnetoresistive device layers is deposited on a first silicon nitride layer formed on a silicon oxide layer. An etch stop is formed on the magnetoresistive device layers, and a second layer of silicon nitride is formed on the etch stop. The magnetoresistive device layers are patterned to define a plurality of magnetic bits having sidewalls. The second silicon nitride layer is patterned to define electrical contact portions on the etch stop in each magnetic bit. The sidewalls of the magnetic bits are covered with a photoresist layer. A reactive ion etch (RIE) process is used to etch into the first silicon nitride and silicon oxide layers to expose electrical contacts. The photoresist layer and silicon nitride layers protect the magnetoresistive layers from exposure to oxygen during the etching into the silicon oxide layer.
摘要翻译：在制造巨磁阻（GMR）器件的方法中，多个磁阻器件层沉积在形成于氧化硅层上的第一氮化硅层上。在磁阻器件层上形成蚀刻停止层，在蚀刻停止层上形成第二氮化硅层。图案化磁阻器件层以限定具有侧壁的多个磁性位。将第二氮化硅层图案化以限定每个磁头中蚀刻停止点上的电接触部分。磁头的侧壁被光致抗蚀剂层覆盖。使用反应离子蚀刻（RIE）工艺来蚀刻到第一氮化硅和氧化硅层中以暴露电触点。在蚀刻到氧化硅层期间，光致抗蚀剂层和氮化硅层保护磁阻层免受暴露于氧气。

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