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1. 发明申请

US20110007597A1 Semiconductor Control Line Address Decoding Circuit 有权
标题翻译：半导体控制线地址解码电路
公开(公告)号：US20110007597A1
公开(公告)日：2011-01-13
申请号：US12502219
申请日：2009-07-13
申请人： Chulmin Jung , Dadi Setiadi , YoungPil Kim , Harry Hongyue Liu , Hyung-Kyu Lee
发明人： Chulmin Jung , Dadi Setiadi , YoungPil Kim , Harry Hongyue Liu , Hyung-Kyu Lee
IPC分类号： G11C8/10
CPC分类号： G11C8/10
摘要： Apparatus and method for decoding addresses of control lines in a semiconductor device, such as a solid state memory (SSM). In accordance with some embodiments, a switching circuit includes an array of switching devices coupled to 2N output lines and M input lines, wherein M and N are respective non-zero integers and each output line has a unique N-bit address. A decoder circuit coupled to the switching circuit divides the N-bit address for a selected output line into a plurality of multi-bit subgroup addresses, and asserts the M input lines in relation to respective bit values of said subgroup addresses to apply a first voltage to the selected output line and to concurrently apply a second voltage to the remaining 2N-1 output lines.
摘要翻译：用于解码诸如固态存储器（SSM）的半导体器件中的控制线的地址的装置和方法。根据一些实施例，开关电路包括耦合到2N个输出线和M个输入线的开关器件阵列，其中M和N分别是非零整数，并且每个输出线具有唯一的N位地址。耦合到开关电路的解码器电路将所选择的输出线的N位地址划分为多个多位子组地址，并且相对于所述子组地址的各个位值断言M个输入线，以施加第一电压并且向剩余的2N-1个输出线同时施加第二电压。

2. 发明授权

US08289804B2 Semiconductor control line address decoding circuit 有权
标题翻译：半导体控制线地址解码电路
公开(公告)号：US08289804B2
公开(公告)日：2012-10-16
申请号：US13100967
申请日：2011-05-04
申请人： Chulmin Jung , Dadi Setiadi , YoungPil Kim , Harry Hongyue Liu , Hyung-Kyu Lee
发明人： Chulmin Jung , Dadi Setiadi , YoungPil Kim , Harry Hongyue Liu , Hyung-Kyu Lee
IPC分类号： G11C8/00
CPC分类号： G11C8/10
摘要： Apparatus and method for decoding addresses of control lines in a semiconductor device, such as a solid state memory (SSM). In accordance with some embodiments, a switching circuit includes an array of switching devices coupled to 2N output lines and M input lines, wherein M and N are respective non-zero integers and each output line has a unique N-bit address. A decoder circuit coupled to the switching circuit divides the N-bit address for a selected output line into a plurality of multi-bit subgroup addresses, and asserts the M input lines in relation to respective bit values of said subgroup addresses to apply a first voltage to the selected output line and to concurrently apply a second voltage to the remaining 2N−1 output lines.
摘要翻译：用于解码诸如固态存储器（SSM）的半导体器件中的控制线的地址的装置和方法。根据一些实施例，开关电路包括耦合到2N个输出线和M个输入线的开关器件阵列，其中M和N分别是非零整数，并且每个输出线具有唯一的N位地址。耦合到开关电路的解码器电路将所选择的输出线的N位地址划分为多个多位子组地址，并且相对于所述子组地址的各个位值断言M个输入线，以施加第一电压并且向剩余的2N-1个输出线同时施加第二电压。

3. 发明申请

US20110205830A1 Semiconductor Control Line Address Decoding Circuit 有权
标题翻译：半导体控制线地址解码电路
公开(公告)号：US20110205830A1
公开(公告)日：2011-08-25
申请号：US13100967
申请日：2011-05-04
申请人： Chulmin Jung , Dadi Setiadi , YoungPil Kim , Harry Hongyue Liu , Hyung-Kyu Lee
发明人： Chulmin Jung , Dadi Setiadi , YoungPil Kim , Harry Hongyue Liu , Hyung-Kyu Lee
IPC分类号： G11C8/10
CPC分类号： G11C8/10
摘要： Apparatus and method for decoding addresses of control lines in a semiconductor device, such as a solid state memory (SSM). In accordance with some embodiments, a switching circuit includes an array of switching devices coupled to 2N output lines and M input lines, wherein M and N are respective non-zero integers and each output line has a unique N-bit address. A decoder circuit coupled to the switching circuit divides the N-bit address for a selected output line into a plurality of multi-bit subgroup addresses, and asserts the M input lines in relation to respective bit values of said subgroup addresses to apply a first voltage to the selected output line and to concurrently apply a second voltage to the remaining 2N−1 output lines.
摘要翻译：用于解码诸如固态存储器（SSM）的半导体器件中的控制线的地址的装置和方法。根据一些实施例，开关电路包括耦合到2N个输出线和M个输入线的开关器件阵列，其中M和N分别是非零整数，并且每个输出线具有唯一的N位地址。耦合到开关电路的解码器电路将所选择的输出线的N位地址划分为多个多位子组地址，并且相对于所述子组地址的各个位值断言M个输入线，以施加第一电压并且向剩余的2N-1个输出线同时施加第二电压。

4. 发明授权

US07969812B2 Semiconductor control line address decoding circuit 有权
标题翻译：半导体控制线地址解码电路
公开(公告)号：US07969812B2
公开(公告)日：2011-06-28
申请号：US12502219
申请日：2009-07-13
申请人： Chulmin Jung , Dadi Setiadi , YoungPil Kim , Harry Hongyue Liu , Hyung-Kyu Lee
发明人： Chulmin Jung , Dadi Setiadi , YoungPil Kim , Harry Hongyue Liu , Hyung-Kyu Lee
IPC分类号： G11C8/00
CPC分类号： G11C8/10
摘要： Apparatus and method for decoding addresses of control lines in a semiconductor device, such as a solid state memory (SSM). In accordance with some embodiments, a switching circuit includes an array of switching devices coupled to 2N output lines and M input lines, wherein M and N are respective non-zero integers and each output line has a unique N-bit address. A decoder circuit coupled to the switching circuit divides the N-bit address for a selected output line into a plurality of multi-bit subgroup addresses, and asserts the M input lines in relation to respective bit values of said subgroup addresses to apply a first voltage to the selected output line and to concurrently apply a second voltage to the remaining 2N-1 output lines.
摘要翻译：用于解码诸如固态存储器（SSM）的半导体器件中的控制线的地址的装置和方法。根据一些实施例，开关电路包括耦合到2N个输出线和M个输入线的开关器件阵列，其中M和N分别是非零整数，并且每个输出线具有唯一的N位地址。耦合到开关电路的解码器电路将所选择的输出线的N位地址划分为多个多位子组地址，并且相对于所述子组地址的各个位值断言M个输入线，以施加第一电压并且向剩余的2N-1个输出线同时施加第二电压。

5. 发明授权

US08183126B2 Patterning embedded control lines for vertically stacked semiconductor elements 有权
标题翻译：为垂直堆叠的半导体元件绘制嵌入式控制线
公开(公告)号：US08183126B2
公开(公告)日：2012-05-22
申请号：US12502178
申请日：2009-07-13
申请人： Hyung-Kyu Lee , YoungPil Kim , Peter Nicholas Manos , Maroun Khoury , Dadi Setiadi , Chulmin Jung , Hsing-Kuen Liou , Paramasiyan Kamatchi Subramanian , Yongchul Ahn , Jinyoung Kim , Antoine Khoueir
发明人： Hyung-Kyu Lee , YoungPil Kim , Peter Nicholas Manos , Maroun Khoury , Dadi Setiadi , Chulmin Jung , Hsing-Kuen Liou , Paramasiyan Kamatchi Subramanian , Yongchul Ahn , Jinyoung Kim , Antoine Khoueir
IPC分类号： H01L21/30
CPC分类号： H01L27/101 , H01L27/228 , H01L27/2454 , H01L27/2463 , H01L43/08 , H01L45/04 , H01L45/085 , H01L45/1233 , H01L45/1675
摘要： Various embodiments of the present invention are generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements, and a method for forming the same. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.
摘要翻译：本发明的各种实施例通常涉及一种用于垂直堆叠的半导体元件的嵌入式（底侧）控制线的设备及其形成方法。根据各种实施例，第一半导体晶片设置有第一面对表面，其上形成有第一导电层。第一半导体晶片被附接到第二半导体晶片以形成多晶片结构，第二半导体晶片具有形成第二导电晶片的第二相对表面。所述第一导电层与所述第二导电层接触地接合以在所述结构内形成嵌入的组合导电层。去除组合导电层的部分以形成多个间隔开的控制线，其以选定的长度或宽度尺寸延伸穿过所述结构。

6. 发明申请

US20120199915A1 Patterning Embedded Control Lines for Vertically Stacked Semiconductor Elements 审中-公开
标题翻译：用于垂直堆叠半导体元件的嵌入式控制线图案化
公开(公告)号：US20120199915A1
公开(公告)日：2012-08-09
申请号：US13446462
申请日：2012-04-13
申请人： Hyung-Kyu Lee , YoungPil Kim , Peter Nicholas Manos , Maroun Khoury , Dadi Setiadi , Chulmin Jung , Hsing-Kuen Liou , Paramasiyan Kamatchi Subramanian , Yongchul Ahn , Jinyoung Kim , Antoine Khoueir
发明人： Hyung-Kyu Lee , YoungPil Kim , Peter Nicholas Manos , Maroun Khoury , Dadi Setiadi , Chulmin Jung , Hsing-Kuen Liou , Paramasiyan Kamatchi Subramanian , Yongchul Ahn , Jinyoung Kim , Antoine Khoueir
IPC分类号： H01L27/105
CPC分类号： H01L27/101 , H01L27/228 , H01L27/2454 , H01L27/2463 , H01L43/08 , H01L45/04 , H01L45/085 , H01L45/1233 , H01L45/1675
摘要： The present invention is generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.
摘要翻译：本发明一般涉及用于垂直堆叠的半导体元件的具有嵌入式（底侧）控制线的装置。根据各种实施例，第一半导体晶片设置有第一面对表面，其上形成有第一导电层。第一半导体晶片被附接到第二半导体晶片以形成多晶片结构，第二半导体晶片具有形成第二导电晶片的第二相对表面。所述第一导电层与所述第二导电层接触地接合以在所述结构内形成嵌入的组合导电层。去除组合导电层的部分以形成多个间隔开的控制线，其以选定的长度或宽度尺寸延伸穿过所述结构。

7. 发明授权

US08896070B2 Patterning embedded control lines for vertically stacked semiconductor elements 有权
标题翻译：为垂直堆叠的半导体元件绘制嵌入式控制线
公开(公告)号：US08896070B2
公开(公告)日：2014-11-25
申请号：US13446462
申请日：2012-04-13
申请人： Hyung-Kyu Lee , YoungPil Kim , Peter Nicholas Manos , Maroun Khoury , Dadi Setiadi , Chulmin Jung , Hsing-Kuen Liou , Paramasiyan Kamatchi Subramanian , Yongchul Ahn , Jinyoung Kim , Antoine Khoueir
发明人： Hyung-Kyu Lee , YoungPil Kim , Peter Nicholas Manos , Maroun Khoury , Dadi Setiadi , Chulmin Jung , Hsing-Kuen Liou , Paramasiyan Kamatchi Subramanian , Yongchul Ahn , Jinyoung Kim , Antoine Khoueir
IPC分类号： H01L45/00 , H01L27/24 , H01L27/22 , H01L43/08 , H01L27/10
CPC分类号： H01L27/101 , H01L27/228 , H01L27/2454 , H01L27/2463 , H01L43/08 , H01L45/04 , H01L45/085 , H01L45/1233 , H01L45/1675
摘要： The present invention is generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.
摘要翻译：本发明一般涉及用于垂直堆叠的半导体元件的具有嵌入式（底侧）控制线的装置。根据各种实施例，第一半导体晶片设置有第一面对表面，其上形成有第一导电层。第一半导体晶片被附接到第二半导体晶片以形成多晶片结构，第二半导体晶片具有形成第二导电晶片的第二相对表面。所述第一导电层与所述第二导电层接触地接合以在所述结构内形成嵌入的组合导电层。去除组合导电层的部分以形成多个间隔开的控制线，其以选定的长度或宽度尺寸延伸穿过所述结构。

8. 发明申请

US20110006377A1 Patterning Embedded Control Lines for Vertically Stacked Semiconductor Elements 有权
标题翻译：用于垂直堆叠半导体元件的嵌入式控制线图案化
公开(公告)号：US20110006377A1
公开(公告)日：2011-01-13
申请号：US12502178
申请日：2009-07-13
申请人： Hyung-Kyu Lee , YoungPil Kim , Peter Nicholas Manos , Maroun Khoury , Dadi Setiadi , Chulmin Jung , Hsing-Kuen Liou , Paramasiyan Kamatchi Subramanian , Yongchul Ahn , Jinyoung Kim , Antoine Khoueir
发明人： Hyung-Kyu Lee , YoungPil Kim , Peter Nicholas Manos , Maroun Khoury , Dadi Setiadi , Chulmin Jung , Hsing-Kuen Liou , Paramasiyan Kamatchi Subramanian , Yongchul Ahn , Jinyoung Kim , Antoine Khoueir
IPC分类号： H01L27/105 , H01L21/18
CPC分类号： H01L27/101 , H01L27/228 , H01L27/2454 , H01L27/2463 , H01L43/08 , H01L45/04 , H01L45/085 , H01L45/1233 , H01L45/1675
摘要： Various embodiments of the present invention are generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements, and a method for forming the same. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.
摘要翻译：本发明的各种实施例通常涉及一种用于垂直堆叠的半导体元件的嵌入式（底侧）控制线的设备及其形成方法。根据各种实施例，第一半导体晶片设置有第一面对表面，其上形成有第一导电层。第一半导体晶片被附接到第二半导体晶片以形成多晶片结构，第二半导体晶片具有形成第二导电晶片的第二相对表面。所述第一导电层与所述第二导电层接触地接合以在所述结构内形成嵌入的组合导电层。去除组合导电层的部分以形成多个间隔开的控制线，其以选定的长度或宽度尺寸延伸穿过所述结构。

9. 发明申请

US20120074488A1 VERTICAL TRANSISTOR WITH HARDENING IMPLATATION 有权
标题翻译：具硬化强度的垂直晶体管
公开(公告)号：US20120074488A1
公开(公告)日：2012-03-29
申请号：US12891966
申请日：2010-09-28
申请人： Young Pil Kim , Hyung-Kyu Lee , Peter Nicholas Manos , Chulmin Jung , Maroun Georges Khoury , Dadi Setiadi
发明人： Young Pil Kim , Hyung-Kyu Lee , Peter Nicholas Manos , Chulmin Jung , Maroun Georges Khoury , Dadi Setiadi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L45/1233 , H01L27/228 , H01L27/2454 , H01L45/1206
摘要： A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. Each pillar structure forms a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface. Then a hardening species is implanted into the vertical pillar transistor top surface. Then the vertical pillar transistor side surface is oxidized to form a side surface oxide layer. The side surface oxide layer is removed to form vertical pillar transistor having rounded side surfaces.
摘要翻译：一种方法包括提供具有从半导体晶片正交延伸的多个柱结构的半导体晶片。每个柱结构形成具有与顶表面正交的顶表面和侧表面的垂直柱晶体管。然后将硬化物质注入垂直柱晶体管顶表面。然后，垂直柱状晶体管侧面被氧化，形成侧面氧化层。去除侧面氧化物层以形成具有圆形侧表面的垂直柱状晶体管。

10. 发明申请

US20120074466A1 3D MEMORY ARRAY WITH VERTICAL TRANSISTOR 审中-公开
标题翻译：具有垂直晶体管的3D存储阵列
公开(公告)号：US20120074466A1
公开(公告)日：2012-03-29
申请号：US12891982
申请日：2010-09-28
申请人： Dadi Setiadi , Peter Nicholas Manos , Hsing-Kuen Liou , Paramasivan Kamatchi Subramanian , Young Pil Kim , Hyung-Kyu Lee , Maroun Georges Khoury , Chulmin Jung
发明人： Dadi Setiadi , Peter Nicholas Manos , Hsing-Kuen Liou , Paramasivan Kamatchi Subramanian , Young Pil Kim , Hyung-Kyu Lee , Maroun Georges Khoury , Chulmin Jung
IPC分类号： H01L27/088 , H01L21/8239
CPC分类号： H01L21/8239 , H01L21/823487 , H01L27/1052 , H01L27/228 , H01L27/2454 , H01L27/2481
摘要： A memory array includes a base circuitry layer and a plurality of memory array layers stacked sequentially to form the memory array. Each memory array layer is electrically coupled to the base circuitry layer. Each memory array layer includes a plurality of memory units. Each memory unit includes a vertical pillar transistor electrically coupled to a memory cell.
摘要翻译：存储器阵列包括基本电路层和顺序堆叠以形成存储器阵列的多个存储器阵列层。每个存储器阵列层电耦合到基极电路层。每个存储器阵列层包括多个存储器单元。每个存储单元包括电耦合到存储单元的垂直柱状晶体管。

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