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1. 发明授权

US08125819B2 Asymmetric write current compensation using gate overdrive for resistive sense memory cells 有权
公开(公告)号：US08125819B2
公开(公告)日：2012-02-28
申请号：US13206749
申请日：2011-08-10
申请人： Yong Lu , Harry Hongyue Liu
发明人： Yong Lu , Harry Hongyue Liu
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C11/1659 , G11C11/1675 , G11C13/0069 , G11C2013/0071 , G11C2013/0073 , G11C2013/0078 , G11C2213/32 , G11C2213/79
摘要： Apparatus and associated method for asymmetric write current compensation for resistive sense memory (RSM) cells, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) cells. In accordance with some embodiments, an RSM cell includes an RSM element coupled to a switching device. The switching device has a plurality of terminals. A control circuit compensates for asymmetric write characteristics of the RSM cell by limiting a range of voltage differentials across the terminals so as to be equal to or less than a magnitude of a source voltage applied to the switching device, thereby providing bi-directional write currents of substantially equal magnitude through the RSM element.

2. 发明申请

US20120039112A1 Hierarchical Cross-Point Array of Non-Volatile Memory 有权
标题翻译：非易失性存储器的分层交叉点阵列
公开(公告)号：US20120039112A1
公开(公告)日：2012-02-16
申请号：US13280109
申请日：2011-10-24
申请人： Chulmin Jung , Yong Lu , Insik Jin , YoungPil Kim , Harry Hongyue Liu
发明人： Chulmin Jung , Yong Lu , Insik Jin , YoungPil Kim , Harry Hongyue Liu
IPC分类号： G11C11/00
CPC分类号： A01H6/14 , A01H5/02
摘要： A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns. A selection circuit is provided that is capable of activating the first block of memory cells while deactivating the second block of memory cells. Further, a read circuit is provided that is capable of reading a logical state of a predetermined memory cell in the first block of memory cells with a reduced leak current by programming a first resistive state to the block selection elements corresponding to the first block of memory cells while programming a second resistive state to the block selection elements corresponding to the second block of memory cells.
摘要翻译：一种用于从非易失性存储单元读取数据的方法和装置。在一些实施例中，非易失性存储器单元的交叉点阵列被布置成行和列。提供了选择电路，其能够在禁用第二存储单元块的同时激活存储器单元的第一块。此外，提供一种读取电路，其能够通过对与第一存储器块相对应的块选择元件编程第一电阻状态，以减小的漏电流来读取存储器单元的第一块中的预定存储器单元的逻辑状态同时将第二电阻状态编程到对应于存储器单元的第二块的块选择元件。

3. 发明申请

US20110299323A1 Floating Source Line Architecture for Non-Volatile Memory 有权
标题翻译：非易失性存储器的浮动源线架构
公开(公告)号：US20110299323A1
公开(公告)日：2011-12-08
申请号：US13206550
申请日：2011-08-10
申请人： Chulmin Jung , Yong Lu , Harry Hongyue Liu
发明人： Chulmin Jung , Yong Lu , Harry Hongyue Liu
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0002 , G11C7/12 , G11C11/16 , G11C11/1673 , G11C11/1675 , G11C13/0069
摘要： A method and apparatus for writing data to a non-volatile memory cell, such as an RRAM memory cell. In some embodiments, a semiconductor array of non-volatile memory cells comprises a resistive sense element (RSE) and a switching device. A RSE of a plurality of memory cells is connected to a bit line while the switching device of a plurality of memory cells is connected to a word line and operated to select a memory cell. A source line is connected to the switching device and connects a series of memory cells together. Further, a driver circuit is connected to the bit line and writes a selected RSE of a selected source line to a selected resistive state by passing a write current along a write current path that passes through the selected RSE and through at least a portion of the remaining RSE connected to the selected source line.
摘要翻译：一种用于将数据写入诸如RRAM存储器单元的非易失性存储单元的方法和装置。在一些实施例中，非易失性存储单元的半导体阵列包括电阻感测元件（RSE）和开关器件。多个存储单元的RSE连接到位线，而多个存储单元的开关器件连接到字线并被操作以选择存储器单元。源极线连接到开关器件，并将一系列存储器单元连接在一起。此外，驱动器电路连接到位线，并且通过使写入电流沿着通过所选择的RSE的写入电流路径并通过至少一部分剩余的RSE连接到所选择的源线。

4. 发明授权

US08009457B2 Write current compensation using word line boosting circuitry 有权
公开(公告)号：US08009457B2
公开(公告)日：2011-08-30
申请号：US12967802
申请日：2010-12-14
申请人： Hai Li , Yiran Chen , Harry Hongyue Liu , Henry Huang , Ran Wang
发明人： Hai Li , Yiran Chen , Harry Hongyue Liu , Henry Huang , Ran Wang
IPC分类号： G11C11/00 , G11C17/00 , G11C5/14 , G11C8/00
CPC分类号： G11C8/08 , G11C11/1659 , G11C11/1675 , G11C13/0028 , G11C13/0069 , G11C2013/0071
摘要： Apparatus and method for write current compensation in a non-volatile memory cell, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM). In accordance with some embodiments, a non-volatile memory cell has a resistive sense element (RSE) coupled to a switching device, the RSE having a hard programming direction and an easy programming direction opposite the hard programming direction. A voltage boosting circuit includes a capacitor which adds charge to a nominal non-zero voltage supplied by a voltage source to a node to generate a temporarily boosted voltage. The boosted voltage is applied to the switching device when the RSE is programmed in the hard programming direction.

5. 发明申请

US20110182106A1 Current Cancellation for Non-Volatile Memory 有权
标题翻译：非易失性存储器的当前取消
公开(公告)号：US20110182106A1
公开(公告)日：2011-07-28
申请号：US13081170
申请日：2011-04-06
申请人： Chulmin Jung , Insik Jin , YoungPil Kim , Yong Lu , Harry Hongyue Liu , Andrew John Carter
发明人： Chulmin Jung , Insik Jin , YoungPil Kim , Yong Lu , Harry Hongyue Liu , Andrew John Carter
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C11/1673
摘要： A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns that are each controlled by a line driver. A read circuit is provided that is capable of reading a logical state of a predetermined memory cell by differentiating a non-integrated first reference value from a non-integrated second reference value. Further, each reference value is measured immediately after configuring the column corresponding to the predetermined memory cell to produce a first and second amount of current.
摘要翻译：一种用于从非易失性存储单元读取数据的方法和装置。在一些实施例中，非易失性存储器单元的交叉点阵列被布置成行和列，每个行和列都由线驱动器控制。提供读取电路，其能够通过将非积分的第一参考值与非积分的第二参考值进行微分来读取预定存储器单元的逻辑状态。此外，在配置与预定存储单元相对应的列之后立即测量每个参考值以产生第一和第二电流量。

6. 发明授权

US07974121B2 Write current compensation using word line boosting circuitry 有权
标题翻译：使用字线升压电路写入电流补偿
公开(公告)号：US07974121B2
公开(公告)日：2011-07-05
申请号：US12967743
申请日：2010-12-14
申请人： Hai Li , Yiran Chen , Harry Hongyue Liu , Henry Huang , Ran Wang
发明人： Hai Li , Yiran Chen , Harry Hongyue Liu , Henry Huang , Ran Wang
IPC分类号： G11C11/00 , G11C11/14 , G11C5/14 , G11C8/00
CPC分类号： G11C8/08 , G11C11/1659 , G11C11/1675 , G11C13/0028 , G11C13/0069 , G11C2013/0071
摘要： Apparatus and method for write current compensation in a non-volatile memory cell, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM). In accordance with some embodiments, a non-volatile memory cell has a resistive sense element (RSE) coupled to a switching device, the RSE having a hard programming direction and an easy programming direction opposite the hard programming direction. A voltage boosting circuit includes a capacitor which adds charge to a nominal non-zero voltage supplied by a voltage source to a node to generate a temporarily boosted voltage. The boosted voltage is applied to the switching device when the RSE is programmed in the hard programming direction.
摘要翻译：非易失性存储单元中的写入电流补偿的装置和方法，例如但不限于自旋转矩传递随机存取存储器（STRAM）或电阻随机存取存储器（RRAM）。根据一些实施例，非易失性存储器单元具有耦合到开关器件的电阻感测元件（RSE），RSE具有硬编程方向和与硬编程方向相反的简单编程方向。升压电路包括电容器，该电容器将电压加到由电压源向节点提供的标称非零电压以产生暂时提升的电压。当RSE在硬编程方向编程时，升压电压施加到开关器件。

7. 发明授权

US07965565B2 Current cancellation for non-volatile memory 有权
标题翻译：当前取消非易失性存储器
公开(公告)号：US07965565B2
公开(公告)日：2011-06-21
申请号：US12502208
申请日：2009-07-13
申请人： Chulmin Jung , Insik Jin , YoungPil Kim , Yong Lu , Harry Hongyue Liu , Andrew John Carter
发明人： Chulmin Jung , Insik Jin , YoungPil Kim , Yong Lu , Harry Hongyue Liu , Andrew John Carter
IPC分类号： G11C7/00
CPC分类号： G11C11/1673
摘要： A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns that are each controlled by a line driver. A read circuit is provided that is capable of reading a logical state of a predetermined memory cell by differentiating a non-integrated first reference value from a non-integrated second reference value. Further, each reference value is measured immediately after configuring the column corresponding to the predetermined memory cell to produce a first and second amount of current.
摘要翻译：一种用于从非易失性存储单元读取数据的方法和装置。在一些实施例中，非易失性存储器单元的交叉点阵列被布置成行和列，每个行和列都由线驱动器控制。提供读取电路，其能够通过将非积分的第一参考值与非积分的第二参考值进行微分来读取预定存储器单元的逻辑状态。此外，在配置与预定存储单元相对应的列之后立即测量每个参考值以产生第一和第二电流量。

8. 发明申请

US20110116302A1 Asymmetric Write Current Compensation Using Gate Overdrive for Resistive Sense Memory Cells 有权
标题翻译：电阻式感应存储器单元使用栅极超速驱动的非对称写入电流补偿
公开(公告)号：US20110116302A1
公开(公告)日：2011-05-19
申请号：US13014757
申请日：2011-01-27
申请人： Yong Lu , Harry Hongyue Liu
发明人： Yong Lu , Harry Hongyue Liu
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C11/1659 , G11C11/1675 , G11C13/0069 , G11C2013/0071 , G11C2013/0073 , G11C2013/0078 , G11C2213/32 , G11C2213/79
摘要： Apparatus and associated method for asymmetric write current compensation for resistive sense memory (RSM) cells, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) cells. In accordance with some embodiments, an RSM cell includes an RSM element coupled to a switching device. The switching device has a plurality of terminals. A control circuit compensates for asymmetric write characteristics of the RSM cell by limiting a range of voltage differentials across the terminals so as to be equal to or less than a magnitude of a source voltage applied to the switching device, thereby providing bi-directional write currents of substantially equal magnitude through the RSM element.
摘要翻译：用于电阻感测存储器（RSM）单元的非对称写入电流补偿的装置和相关方法，例如但不限于自旋转矩传递随机存取存储器（STRAM）或电阻随机存取存储器（RRAM）单元。根据一些实施例，RSM单元包括耦合到开关装置的RSM元件。开关装置具有多个端子。控制电路通过限制端子两端的电压差的范围来补偿RSM单元的不对称写入特性，以便等于或小于施加到开关器件的源极电压的幅度，由此提供双向写入电流通过RSM元件具有基本相等的幅度。

9. 发明申请

US20110058405A1 Memory Cell With Proportional Current Self-Reference Sensing 有权
标题翻译：具有比例电流自参考检测的存储单元
公开(公告)号：US20110058405A1
公开(公告)日：2011-03-10
申请号：US12946582
申请日：2010-11-15
申请人： Yiran Chen , Hai Li , Wenzhong Zhu , Xiaobin Wang , Ran Wang , Harry Hongyue Liu
发明人： Yiran Chen , Hai Li , Wenzhong Zhu , Xiaobin Wang , Ran Wang , Harry Hongyue Liu
IPC分类号： G11C11/16 , G11C11/21 , G11C7/06
CPC分类号： G11C7/062 , G11C11/1673 , G11C11/1693 , G11C13/004 , G11C2013/0057 , G11C2207/063
摘要： Various embodiments of the present invention are generally directed to a method and apparatus for sensing a programmed state of a memory cell, such as a spin-torque transfer random access memory (STRAM) cell. A first read current is applied to the memory cell to generate a first voltage. A second read current is subsequently applied to the memory cell to generate a second voltage, with the second read current being proportional in magnitude to the first read current. A comparison is made between the first and second voltages to determine the programmed state of the memory cell.
摘要翻译：本发明的各种实施例通常涉及用于感测诸如自旋扭矩传递随机存取存储器（STRAM）单元的存储器单元的编程状态的方法和装置。将第一读取电流施加到存储器单元以产生第一电压。随后将第二读取电流施加到存储器单元以产生第二电压，其中第二读取电流在幅度上与第一读取电流成比例。在第一和第二电压之间进行比较以确定存储器单元的编程状态。

10. 发明申请

US20110032749A1 NAND Based Resistive Sense Memory Cell Architecture 有权
标题翻译：基于NAND的电阻式感应存储器单元架构
公开(公告)号：US20110032749A1
公开(公告)日：2011-02-10
申请号：US12903716
申请日：2010-10-13
申请人： Harry Hongyue Liu , Haiwen Xi , Antoine Khoueir , Song Xue
发明人： Harry Hongyue Liu , Haiwen Xi , Antoine Khoueir , Song Xue
IPC分类号： G11C11/34 , H01L45/00
CPC分类号： H01L27/24 , G11C11/1659 , G11C13/0007 , G11C13/003 , G11C2213/32 , G11C2213/34 , G11C2213/75 , H01L27/228
摘要： Various embodiments are directed to an apparatus comprising a semiconductor memory array with non-volatile memory unit cells arranged into a NAND block. Each of the unit cells comprises a resistive sense element connected in parallel with a switching element. The resistive sense elements are connected in series to form a first serial path, and the switching elements are connected in series to form a second serial path parallel to the first serial path. Each resistive sense element is serially connected to an adjacent resistive sense element in the block by a tortuous conductive path having a portion that extends substantially vertically between said elements to provide operational isolation therefor.
摘要翻译：各种实施例涉及一种包括具有布置在NAND块中的非易失性存储器单元的半导体存储器阵列的装置。每个单元电池包括与开关元件并联连接的电阻感测元件。电阻感测元件串联连接以形成第一串行路径，并且开关元件串联连接以形成平行于第一串行路径的第二串行路径。每个电阻感测元件通过具有在所述元件之间基本上垂直延伸的部分的曲折导电路径串联连接到块中的相邻电阻感测元件，以提供对其的操作隔离。

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