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31. 发明授权

US5514350A Apparatus for making nanostructured ceramic powders and whiskers 失效
标题翻译：用于制造纳米结构陶瓷粉末和晶须的装置
公开(公告)号：US5514350A
公开(公告)日：1996-05-07
申请号：US231026
申请日：1994-04-22
申请人： Bernard H. Kear , Weng Chang , Ganesh Skandan , Horst W. Hahn
发明人： Bernard H. Kear , Weng Chang , Ganesh Skandan , Horst W. Hahn
IPC分类号： B01J12/02 , B01J19/18 , B01J19/24 , C01B21/068 , C01B21/082 , C01B31/36 , C04B35/626 , C30B25/00 , F25B29/00
CPC分类号： B82Y30/00 , B01J12/02 , B01J19/18 , B01J19/2415 , C01B21/068 , C01B21/0828 , C01B31/36 , C04B35/626 , C30B25/005 , C30B29/36 , C30B29/38 , B01J2219/00085 , B01J2219/00094 , B01J2219/00162 , B01J2219/00164 , C01P2002/72 , C01P2004/10 , C01P2004/50 , C01P2004/64 , C01P2006/10 , C01P2006/12 , C01P2006/60 , C01P2006/80 , F02B2275/14 , Y02T10/123 , Y10S977/776 , Y10S977/835 , Y10S977/84
摘要： An apparatus of forming non-agglomerated nanostructured ceramic (n-ceramic) powders from metalorganic precursors combines rapid thermal decomposition of a precursor/carrier gas stream in a hot tubular reactor with rapid condensation of the product particles on a cold substrate under a reduced inert gas pressure of 1-50 mbar. A wide variety of metalorganic precursors is available. The apparatus is particularly suitable for formation of n-SiC.sub.x N.sub.y powders from hexamethyl-disilizane or the formation of n-ZrO.sub.x C.sub.y powders from zirconium tertiary butoxide. The n-SiC.sub.x N.sub.y compounds can be further reacted to form SiC or Si.sub.3 N.sub.4 whiskers, individually or in random-weave form, by heating in a hydrogen or ammonia atmosphere. The non-agglomerated n-ceramic powders form uniformly dense powder compacts by cold pressing which can be sintered to theoretical density at temperatures as low as 0.5 Tm. By appropriate choice of precursor compound and carrier gas, this apparatus can be used to produce nanoosized powders of almost any desired material, including metals, intermetallics, semiconductors, superconductors, ferro-electrics, optically active materials and magnetic materials, as well as their composites.
摘要翻译：从金属有机前体形成非凝聚的纳米结构陶瓷（n-陶瓷）粉末的装置将热管式反应器中的前体/载气流的快速热分解与产物颗粒在还原惰性气体下在冷的基底上快速冷凝压力为1-50毫巴。有各种各样的金属有机前体可用。该装置特别适用于从六甲基二硅氮烷形成n-SiCxNy粉末或由叔丁醇锆形成正ZrOxCy粉末。可以通过在氢气或氨气氛中加热，使n-SiC x N y化合物单独地或以无规方式形成SiC或Si 3 N 4晶须。未凝聚的n型陶瓷粉末通过冷压形成均匀致密的粉末压坯，其可以在低至0.5Tm的温度下烧结至理论密度。通过适当选择前体化合物和载气，该装置可用于生产几乎任何所需材料的纳米尺寸粉末，包括金属，金属间化合物，半导体，超导体，铁电，光学活性材料和磁性材料，以及它们的复合材料。

32. 发明申请

US20070284677A1 Metal oxynitride gate 审中-公开
标题翻译：金属氮氧化物门
公开(公告)号：US20070284677A1
公开(公告)日：2007-12-13
申请号：US11796164
申请日：2007-04-26
申请人： Weng Chang , Boq-Kang Hu , Jamie Schaeffer , David C. Gilmer , Phil Tobin
发明人： Weng Chang , Boq-Kang Hu , Jamie Schaeffer , David C. Gilmer , Phil Tobin
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L21/28088 , H01L29/4966 , H01L29/517 , H01L29/665
摘要： A metal-oxide-semiconductor (MOS) transistor having a gate electrode comprising a metal oxynitride and a method of forming the same are provided. The metal oxynitride preferably comprises molybdenum oxynitride and/or iridium oxynitride. The gate electrode may further comprise carbon and/or silicon. The gate electrode is preferably formed in a chamber containing nitrogen, oxygen and a carbon-containing gas. The gate electrode of the MOS transistor has a high work function and a low equivalent oxide thickness.
摘要翻译：提供具有包含金属氮氧化物的栅电极的金属氧化物半导体（MOS）晶体管及其形成方法。金属氮氧化物优选包含氮氧化钼和/或氮氧化铱。栅极可以进一步包括碳和/或硅。栅电极优选形成在含有氮，氧和含碳气体的室中。 MOS晶体管的栅电极具有高功函数和低当量氧化物厚度。

33. 发明授权

US07115974B2 Silicon oxycarbide and silicon carbonitride based materials for MOS devices 有权
标题翻译：用于MOS器件的碳氧化硅和碳氮化硅基材料
公开(公告)号：US07115974B2
公开(公告)日：2006-10-03
申请号：US10895514
申请日：2004-07-21
申请人： Zhen-Cheng Wu , Hung Chun Tsai , Da-Wen Lin , Weng Chang , Shwang-Ming Cheng , Mong Song Liang
发明人： Zhen-Cheng Wu , Hung Chun Tsai , Da-Wen Lin , Weng Chang , Shwang-Ming Cheng , Mong Song Liang
IPC分类号： H01L23/58
CPC分类号： H01L29/4983 , H01L21/02126 , H01L21/02167 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/314 , H01L21/3148 , H01L21/31633 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/3192 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L2924/0002 , H01L2924/19041 , H01L2924/00
摘要： In the preferred embodiment, a gate dielectric and an electrode are formed on a substrate. A pair of spacers is formed along opposite sidewalls of the gate electrode and the gate dielectric. Spacers are preferably formed of SiCO based material or SiCN based material. The source and drain are then formed. A contact etch stop (CES) layer is formed on the source/drain regions and the spacers. The CES layer is preferably formed of SiCO based material or SiCN based material. An Inter-Level Dielectric (ILD) is then formed on the CES layer.
摘要翻译：在优选实施例中，在基板上形成栅极电介质和电极。在栅电极和栅极电介质的相对侧壁上形成一对间隔物。间隔物优选由SiCO基材料或SiCN基材料形成。然后形成源极和漏极。在源极/漏极区域和间隔物上形成接触蚀刻停止层（CES）层。 CES层优选由SiCO基材料或SiCN基材料形成。然后在CES层上形成级间介质（ILD）。

34. 发明授权

US06929533B2 Methods for enhancing within-wafer CMP uniformity 失效
标题翻译：提高晶片内CMP均匀性的方法
公开(公告)号：US06929533B2
公开(公告)日：2005-08-16
申请号：US10684288
申请日：2003-10-08
申请人： Weng Chang
发明人： Weng Chang
IPC分类号： B24B37/04 , B24B57/02 , B24B1/00
CPC分类号： B24B37/04 , B24B57/02
摘要： A method for enhancing uniformity in the polishing profile of a substrate during chemical mechanical polishing. According to a first embodiment, the method is adapted for a rotary-type chemical mechanical polisher and includes dispensing the polishing slurry onto the rotating polishing pad of the CMP apparatus in a polishing area on the polishing pad that contacts the entire surface area of the substrate. This facilitates substantially equal polishing rates and a substantially uniform polishing profile from the center to the edge regions on the surface of the substrate. According to a second embodiment, the method of the present invention is adapted for a linear-type chemical mechanical polisher and includes increasing the number of nozzles that dispense the slurry onto the polishing pad across the diameter or width of the substrate.
摘要翻译：一种用于在化学机械抛光期间增强基板的抛光轮廓的均匀性的方法。根据第一实施例，该方法适用于旋转式化学机械抛光机，并且包括将抛光浆料分配到抛光垫上抛光区域上的CMP设备的旋转抛光垫上，该抛光区域与基板的整个表面区域接触。这有利于从衬底表面上的中心到边缘区域的基本相同的抛光速率和基本均匀的抛光轮廓。根据第二实施例，本发明的方法适用于线性化学机械抛光机，并且包括增加在衬底的直径或宽度上将浆料分配到抛光垫上的喷嘴的数量。

35. 发明授权

US06403464B1 Method to reduce the moisture content in an organic low dielectric constant material 有权
标题翻译：降低有机低介电常数材料含水量的方法
公开(公告)号：US06403464B1
公开(公告)日：2002-06-11
申请号：US09433053
申请日：1999-11-03
申请人： Weng Chang
发明人： Weng Chang
IPC分类号： H01L214763
CPC分类号： H01L21/02118 , H01L21/02282 , H01L21/0234 , H01L21/312 , H01L21/3122 , H01L21/76826
摘要： A method of forming an organic low k layer, for use as an interlevel dielectric layer in semiconductor integrated circuits, has been developed. An organic low k layer, such as a poly arylene ether layer, with a dielectric constant between about 2.6 to 2.8, is applied on an underlying metal interconnect pattern. The moisture contained in the as applied, organic low k layer, or the moisture absorbed by the organic low k layer, due to exposure to the environment, is then reduced via a high density plasma treatment, performed in a nitrogen ambient. The reduction in moisture can be accomplished, even when the organic low k layer had been exposed to the environment for a period of time as great as three months. The dielectric constant, of the organic low k layer, remains unchanged, as a result of the high density plasma treatment.
摘要翻译：已经开发了形成用于半导体集成电路中的层间电介质层的有机低k层的方法。将介电常数在约2.6至2.8之间的有机低k层，例如聚亚芳基醚层施加在下面的金属互连图案上。然后，通过在氮气环境中进行的高密度等离子体处理，减少了所施加的有机低k层中含有的水分或由于暴露于环境而被有机低k层吸收的水分。即使当有机低k层暴露在环境中长达三个月的时间时，也可以实现湿度的降低。作为高密度等离子体处理的结果，有机低k层的介电常数保持不变。

36. 发明授权

US07834389B2 Triangular space element for semiconductor device 有权
标题翻译：半导体器件三角形空间元件
公开(公告)号：US07834389B2
公开(公告)日：2010-11-16
申请号：US11763566
申请日：2007-06-15
申请人： Yu-Lien Huang , Yi-Chen Huang , Jim Cy Huang , Weng Chang , Hun-Jan Tao
发明人： Yu-Lien Huang , Yi-Chen Huang , Jim Cy Huang , Weng Chang , Hun-Jan Tao
IPC分类号： H01L29/788
CPC分类号： H01L21/823425 , H01L21/823468 , Y10S438/981
摘要： Provided is a semiconductor device including a substrate. A gate formed on the substrate. The gate includes a sidewall. A spacer formed on the substrate and adjacent the sidewall of the gate. The spacer has a substantially triangular geometry. A contact etch stop layer (CESL) is formed on the first gate and the first spacer. The thickness of the CESL to the width of the first spacer is between approximately 0.625 and 16.
摘要翻译：提供了包括基板的半导体器件。形成在基板上的栅极。门包括侧壁。在衬底上形成并且邻近门的侧壁的间隔物。间隔件具有基本上三角形的几何形状。在第一栅极和第一间隔物上形成接触蚀刻停止层（CESL）。 CESL的厚度与第一间隔件的宽度在大约0.625和16之间。

37. 发明申请

US20060157776A1 System and method for contact module processing 审中-公开
标题翻译：接触模块处理系统和方法
公开(公告)号：US20060157776A1
公开(公告)日：2006-07-20
申请号：US11039159
申请日：2005-01-20
申请人： Cheng-Hung Chang , Hsiao-Tzu Lu , Chu-Yun Fu , Weng Chang , Shwang-Ming Jeng
发明人： Cheng-Hung Chang , Hsiao-Tzu Lu , Chu-Yun Fu , Weng Chang , Shwang-Ming Jeng
IPC分类号： H01L29/792
CPC分类号： H01L23/3192 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： System and method for improving the process performance of a contact module. A preferred embodiment comprises improving the process performance of a contact module by reducing surface variations of an interlayer dielectric. The interlayer dielectric comprises a plurality of layers, a first layer (for example, a contact etch stop layer 610) protects devices on a substrate from subsequent etching operations, while a second layer (for example, a first dielectric layer 620) covers the first layer. A third layer (for example, a second dielectric layer 630) fills gaps that may be due to the topography of the devices. A fourth layer (for example, a third dielectric layer 640), brings the interlayer dielectric layer to a desired thickness and is formed using a process that yields a very flat surface completes the interlayer dielectric. Using multiple layers permit the elimination of variations (filling gaps and leveling bumps) without resorting to chemical-mechanical polishing.
摘要翻译：提高接触模块工艺性能的系统和方法。优选实施例包括通过减少层间电介质的表面变化来提高接触模块的工艺性能。层间电介质包括多层，第一层（例如，接触蚀刻停止层610）保护衬底上的器件免受后续蚀刻操作，而第二层（例如，第一介电层620）覆盖第一层层。第三层（例如，第二介电层630）填充可能是由于器件的形貌造成的间隙。第四层（例如，第三介电层640）使得层间电介质层达到期望的厚度并且使用产生非常平坦的表面的工艺形成来完成层间电介质。使用多层可以消除变化（填充间隙和调平凸起），而无需采用化学机械抛光。

38. 发明申请

US20050260806A1 High performance strained channel mosfets by coupled stress effects 有权
标题翻译：高性能应变通道MOSFET通过耦合应力作用
公开(公告)号：US20050260806A1
公开(公告)日：2005-11-24
申请号：US10849689
申请日：2004-05-19
申请人： Cheng-Hung Chang , Weng Chang , Chu-Yun Fu
发明人： Cheng-Hung Chang , Weng Chang , Chu-Yun Fu
IPC分类号： H01L21/8238
CPC分类号： H01L29/7845 , H01L21/823807 , H01L21/823828 , H01L21/823878 , H01L29/7842 , H01L29/7843 , H01L29/7846
摘要： Strained channel transistors including a PMOS and NMOS device pair to improve an NMOS device performance without substantially degrading PMOS device performance and method for forming the same, the method including providing a semiconductor substrate; forming strained shallow trench isolation regions in the semiconductor substrate; forming PMOS and NMOS devices on the semiconductor substrate including doped source and drain regions; forming a tensile strained contact etching stop layer (CESL) over the PMOS and NMOS devices; and, forming a tensile strained dielectric insulating layer over the CESL layer.
摘要翻译：包括PMOS和NMOS器件对的应变沟道晶体管，以改善NMOS器件性能而不会使PMOS器件性能基本上降低，并且用于形成PMOS器件性能的方法，所述方法包括提供半导体衬底; 在半导体衬底中形成应变浅沟槽隔离区; 在包括掺杂源极和漏极区域的半导体衬底上形成PMOS和NMOS器件; 在PMOS和NMOS器件上形成拉伸应变接触蚀刻停止层（CESL）; 并在CESL层上形成拉伸应变电介质绝缘层。

39. 发明授权

US06767274B2 Method to reduce defect/slurry residue for copper CMP 失效
标题翻译：减少铜CMP的缺陷/浆料残留的方法
公开(公告)号：US06767274B2
公开(公告)日：2004-07-27
申请号：US10289709
申请日：2002-11-07
申请人： Chi-Chun Chen , Weng Chang , Shih-Chang Chen
发明人： Chi-Chun Chen , Weng Chang , Shih-Chang Chen
IPC分类号： B24B100
CPC分类号： H01L21/02074 , B24B37/042 , H01L21/3212
摘要： A new method and sequence is provided for the polishing of the surface of a layer of metal containing copper. The invention provides for an improved method of residue removal. The invention improves the removal of slurry as part of the step of applying DIW by, during the step of applying DIW, raising the wafer carrier, thus allowing uninhibited removal of the slurry from the surface that is being polished.
摘要翻译：提供了一种用于抛光含铜金属表面的新方法和顺序。本发明提供了一种改进的残留物去除方法。在施加DIW的步骤期间，本发明改进了作为施加DIW的步骤的一部分的浆料的去除，从而提高晶片载体，从而允许从被抛光的表面不受限制地除去浆料。

40. 发明授权

US06753249B1 Multilayer interface in copper CMP for low K dielectric 有权
标题翻译：用于低K电介质的铜CMP中的多层界面
公开(公告)号：US06753249B1
公开(公告)日：2004-06-22
申请号：US09759908
申请日：2001-01-16
申请人： Ying-Ho Chen , Jih-Churng Twu , Weng Chang
发明人： Ying-Ho Chen , Jih-Churng Twu , Weng Chang
IPC分类号： H01L214763
CPC分类号： H01L21/7684
摘要： An improved and new process, used for the elimination of copper line damage, copper defects, non-uniformity improvement, with low dishing and erosion, in damacene processing, is disclosed. This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the elimination of copper line damage for damascene processing, by depositing a multilayer interface material, consisting of a mechanically hard film and a soft film, over a low dielectric constant, interlevel metal dielectric (IMD), and subsequently chemical mechanical polishing (CMP) back the excess material to planarize the surface.
摘要翻译：公开了一种改进的新工艺，用于消除铜线损伤，铜缺陷，不均匀性改进，具有较低的凹陷和侵蚀。本发明涉及一种用于半导体集成电路器件的制造方法，更具体地说，涉及通过在低温下沉积由机械硬膜和软膜组成的多层界面材料来消除镶嵌加工中的铜线损伤介电常数，层间金属电介质（IMD）和随后的化学机械抛光（CMP）回退多余的材料以使表面平坦化。

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