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1. 发明授权

US07115974B2 Silicon oxycarbide and silicon carbonitride based materials for MOS devices 有权
标题翻译：用于MOS器件的碳氧化硅和碳氮化硅基材料
公开(公告)号：US07115974B2
公开(公告)日：2006-10-03
申请号：US10895514
申请日：2004-07-21
申请人： Zhen-Cheng Wu , Hung Chun Tsai , Da-Wen Lin , Weng Chang , Shwang-Ming Cheng , Mong Song Liang
发明人： Zhen-Cheng Wu , Hung Chun Tsai , Da-Wen Lin , Weng Chang , Shwang-Ming Cheng , Mong Song Liang
IPC分类号： H01L23/58
CPC分类号： H01L29/4983 , H01L21/02126 , H01L21/02167 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/314 , H01L21/3148 , H01L21/31633 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/3192 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L2924/0002 , H01L2924/19041 , H01L2924/00
摘要： In the preferred embodiment, a gate dielectric and an electrode are formed on a substrate. A pair of spacers is formed along opposite sidewalls of the gate electrode and the gate dielectric. Spacers are preferably formed of SiCO based material or SiCN based material. The source and drain are then formed. A contact etch stop (CES) layer is formed on the source/drain regions and the spacers. The CES layer is preferably formed of SiCO based material or SiCN based material. An Inter-Level Dielectric (ILD) is then formed on the CES layer.
摘要翻译：在优选实施例中，在基板上形成栅极电介质和电极。在栅电极和栅极电介质的相对侧壁上形成一对间隔物。间隔物优选由SiCO基材料或SiCN基材料形成。然后形成源极和漏极。在源极/漏极区域和间隔物上形成接触蚀刻停止层（CES）层。 CES层优选由SiCO基材料或SiCN基材料形成。然后在CES层上形成级间介质（ILD）。

2. 发明申请

US20050236694A1 Silicon oxycarbide and silicon carbonitride based materials for MOS devices 有权
标题翻译：用于MOS器件的碳氧化硅和碳氮化硅基材料
公开(公告)号：US20050236694A1
公开(公告)日：2005-10-27
申请号：US10895514
申请日：2004-07-21
申请人： Zhen-Cheng Wu , H. Tsai , Da-Wen Lin , Weng Chang , Shwang-Ming Cheng , Mong Liang
发明人： Zhen-Cheng Wu , H. Tsai , Da-Wen Lin , Weng Chang , Shwang-Ming Cheng , Mong Liang
IPC分类号： H01L21/31 , H01L21/314 , H01L21/316 , H01L21/336 , H01L21/768 , H01L23/31 , H01L23/58 , H01L29/49
CPC分类号： H01L29/4983 , H01L21/02126 , H01L21/02167 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/314 , H01L21/3148 , H01L21/31633 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/3192 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L2924/0002 , H01L2924/19041 , H01L2924/00
摘要： In the preferred embodiment, a gate dielectric and an electrode are formed on a substrate. A pair of spacers is formed along opposite sidewalls of the gate electrode and the gate dielectric. Spacers are preferably formed of SiCO based material or SiCN based material. The source and drain are then formed. A contact etch stop (CES) layer is formed on the source/drain regions and the spacers. The CES layer is preferably formed of SiCO based material or SiCN based material. An Inter-Level Dielectric (ILD) is then formed on the CES layer.
摘要翻译：在优选实施例中，在基板上形成栅极电介质和电极。在栅电极和栅极电介质的相对侧壁上形成一对间隔物。间隔物优选由SiCO基材料或SiCN基材料形成。然后形成源极和漏极。在源极/漏极区域和间隔物上形成接触蚀刻停止层（CES）层。 CES层优选由SiCO基材料或SiCN基材料形成。然后在CES层上形成级间介质（ILD）。

3. 发明授权

US07253524B2 Copper interconnects 有权
标题翻译：铜互连
公开(公告)号：US07253524B2
公开(公告)日：2007-08-07
申请号：US10797224
申请日：2004-03-10
申请人： Zhen-Cheng Wu , Tzu-Jen Chou , Weng Chang , Yung-Cheng Lu , Syun-Ming Jang , Mong-Song Liang
发明人： Zhen-Cheng Wu , Tzu-Jen Chou , Weng Chang , Yung-Cheng Lu , Syun-Ming Jang , Mong-Song Liang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76835 , H01L21/76807 , H01L21/76832 , H01L21/76834 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor substrate has a first copper layer, on which an etch stop layer and a dielectric layer are successively formed. A second copper layer penetrates the dielectric layer and the etch stop layer to electrically connect to the first metal layer. The etch stop layer has a dielectric constant smaller than 3.5, and the dielectric layer has a dielectric constant smaller than 3.0.
摘要翻译：半导体衬底具有第一铜层，其上依次形成有蚀刻停止层和电介质层。第二铜层穿透电介质层和蚀刻停止层以电连接到第一金属层。蚀刻停止层的介电常数小于3.5，电介质层的介电常数小于3.0。

4. 发明申请

US20050110153A1 Copper interconnects 有权
标题翻译：铜互连
公开(公告)号：US20050110153A1
公开(公告)日：2005-05-26
申请号：US10797224
申请日：2004-03-10
申请人： Zhen-Cheng Wu , Tzu-Jen Chou , Weng Chang , Yung-Cheng Lu , Syun-Ming Jang , Mong-Song Liang
发明人： Zhen-Cheng Wu , Tzu-Jen Chou , Weng Chang , Yung-Cheng Lu , Syun-Ming Jang , Mong-Song Liang
IPC分类号： H01L21/44 , H01L21/768 , H01L23/48 , H01L23/532
CPC分类号： H01L21/76835 , H01L21/76807 , H01L21/76832 , H01L21/76834 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor substrate has a first copper layer, on which an etch stop layer and a dielectric layer are successively formed. A second copper layer penetrates the dielectric layer and the etch stop layer to electrically connect to the first metal layer. The etch stop layer has a dielectric constant smaller than 3.5, and the dielectric layer has a dielectric constant smaller than 3.0.
摘要翻译：半导体衬底具有第一铜层，其上依次形成有蚀刻停止层和电介质层。第二铜层穿透电介质层和蚀刻停止层以电连接到第一金属层。蚀刻停止层的介电常数小于3.5，电介质层的介电常数小于3.0。

5. 发明授权

US07375040B2 Etch stop layer 有权
标题翻译：蚀刻停止层
公开(公告)号：US07375040B2
公开(公告)日：2008-05-20
申请号：US11325935
申请日：2006-01-05
申请人： Simon S. H. Lin , Weng Chang , Syun-Ming Jang , Mong Song Liang
发明人： Simon S. H. Lin , Weng Chang , Syun-Ming Jang , Mong Song Liang
IPC分类号： H01L21/205
CPC分类号： H01L21/76829 , H01L21/02126 , H01L21/02167 , H01L21/31116 , H01L21/3148 , H01L21/76801 , H01L21/76802 , H01L21/76807 , H01L21/76813
摘要： A SiOC layer and/or a SiC layer of an etch stop layer may be improved by altering the process used to form them. In a bi-layer structure, a SiOC layer and/or a SiC layer may be improved to provide better reliability. A silicon carbide (SiC) layer may be used to form a single-layer etch stop layer, while also acting as a glue layer to improve interface adhesion. Preferably, the SiC layer is formed in a reaction chamber having a flow of substantially pure trimetholsilane (3MS) streamed into and through the reaction chamber under a pressure of less than about 2 torr therein. Preferably, the reaction chamber is energized with high frequency RF power of about 100 watts or more. Preferably, the SiOC layer is formed in a reaction chamber having a flow of 3MS and CO2, and is energized with low frequency RF power of about 100 watts or more.
摘要翻译：蚀刻停止层的SiOC层和/或SiC层可以通过改变用于形成它们的工艺来改进。在双层结构中，可以改善SiOC层和/或SiC层以提供更好的可靠性。可以使用碳化硅（SiC）层来形成单层蚀刻停止层，同时还用作胶层以改善界面附着力。优选地，在反应室中形成具有基本上纯的三甲基硅烷（3MS）的流动的反应室，该三甲基硅烷（3MS）在小于约2托的压力下流入反应室并通过反应室。优选地，反应室以约100瓦或更高的高频RF功率通电。优选地，在具有3MS和CO 2 2的流量的反应室中形成SiOC层，并且以约100瓦特或更高的低频RF功率通电。

6. 发明申请

US20080242108A1 Method for fabricating semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20080242108A1
公开(公告)日：2008-10-02
申请号：US11730551
申请日：2007-04-02
申请人： Weng Chang , Fong-Yu Yen , Hun-Jan Tao , Mong-Song Liang
发明人： Weng Chang , Fong-Yu Yen , Hun-Jan Tao , Mong-Song Liang
IPC分类号： H01L21/46
CPC分类号： H01L21/28079 , H01L21/28088 , H01L21/67207
摘要： A method for fabricating a semiconductor device is disclosed. The method includes providing a first chamber and a second chamber. The first chamber and the second chamber are connected by a pressure differential unit, for depositing a metallic film over a substrate in the first chamber, transferring the substrate to the second chamber via the pressure differential unit without exposing the substrate to the ambient environment, and depositing a silicon-containing film on the metallic film in the second chamber.
摘要翻译：公开了一种制造半导体器件的方法。该方法包括提供第一室和第二室。第一室和第二室通过压力差单元连接，用于在第一室中的基板上沉积金属膜，经由压差单元将衬底转移到第二室，而不将衬底暴露于周围环境;以及在第二室中的金属膜上沉积含硅膜。

7. 发明申请

US20050050708A1 Embedded fastener apparatus and method for preventing particle contamination 审中-公开
标题翻译：嵌入式紧固件装置和防止颗粒污染的方法
公开(公告)号：US20050050708A1
公开(公告)日：2005-03-10
申请号：US10656586
申请日：2003-09-04
申请人： Yu-Lien Huang , Weng Chang , Syun-Ming Jang , Mong Song Liang
发明人： Yu-Lien Huang , Weng Chang , Syun-Ming Jang , Mong Song Liang
IPC分类号： B21D39/03 , B23P11/00 , C23C16/44
CPC分类号： C23C16/45565 , C23C16/4401 , Y10T29/49826 , Y10T29/49947
摘要： A novel embedded fastener apparatus and method for fastening components to the interior of a process chamber of a semiconductor fabrication apparatus. In one embodiment, an apparatus having a showerhead or gas distribution plate which is mounted to the interior of the process chamber using multiple fasteners which are embedded in respective fastener openings in the showerhead. In another embodiment, an apparatus having a showerhead which is mounted to the interior of the process chamber using multiple exterior fasteners which extend into the showerhead through the walls of the process chamber. Accordingly, the regions of the showerhead which surround the fasteners are physically separated from the interior of the process chamber.
摘要翻译：一种用于将部件固定到半导体制造装置的处理室的内部的新颖的嵌入式紧固装置和方法。在一个实施例中，一种具有喷头或气体分配板的装置，其使用嵌入在喷头中的相应紧固件开口中的多个紧固件安装到处理室的内部。在另一个实施例中，一种具有喷头的装置，其使用多个外部紧固件安装到处理室的内部，多个外部紧固件通过处理室的壁延伸到喷头中。因此，围绕紧固件的喷头的区域在物理上与处理室的内部分离。

8. 发明申请

US20050245100A1 Reliability improvement of SiOC etch with trimethylsilane gas passivation in Cu damascene interconnects 有权
标题翻译：在Cu大马士革互连中三甲基硅烷气体钝化的SiOC蚀刻的可靠性提高
公开(公告)号：US20050245100A1
公开(公告)日：2005-11-03
申请号：US10835788
申请日：2004-04-30
申请人： Zhen-Cheng Wu , Bi-Troug Chen , Weng Chang , Syun-Ming Jang , Su-Horng Lin
发明人： Zhen-Cheng Wu , Bi-Troug Chen , Weng Chang , Syun-Ming Jang , Su-Horng Lin
IPC分类号： H01L21/306 , H01L21/314 , H01L21/316 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/31633 , H01L21/02046 , H01L21/02126 , H01L21/02211 , H01L21/02274 , H01L21/02304 , H01L21/02315 , H01L21/3144 , H01L21/3145 , H01L21/3148 , H01L21/76807 , H01L21/76829 , H01L21/76832
摘要： A method of forming a SiCOH etch stop layer in a copper damascene process is described. A substrate with an exposed metal layer is treated with H2 or NH3 plasma to remove metal oxides. Trimethylsilane is flowed into a chamber with no RF power at about 350° C. to form at least a monolayer on the exposed metal layer. The SiCOH layer is formed by a PECVD process including trimethylsilane and CO2 source gases. Optionally, a composite SiCOH layer comprised of a low compressive stress layer on a high compressive stress layer is formed on the substrate. A conventional damascene sequence is then used to form a second metal layer on the exposed metal layer. Via Rc stability is improved and a lower leakage current is achieved with the trimethylsilane passivation layer. A composite SiCOH etch stop layer provides improved stress migration resistance compared to a single low stress SiCOH layer.
摘要翻译：描述了在铜镶嵌工艺中形成SiCOH蚀刻停止层的方法。具有暴露的金属层的衬底用H 2 N 3或NH 3 3等离子体处理以除去金属氧化物。三甲基硅烷在约350℃下流入没有RF功率的室，以在暴露的金属层上形成至少单层。 SiCOH层通过包括三甲基硅烷和CO 2原子气体的PECVD工艺形成。任选地，在基底上形成由高压缩应力层上的低压应力层构成的复合SiCOH层。然后使用常规的镶嵌序列在暴露的金属层上形成第二金属层。通过Rc稳定性提高，并且用三甲基硅烷钝化层实现较低的漏电流。与单个低应力SiCOH层相比，复合SiCOH蚀刻停止层提供改进的应力迁移阻力。

9. 发明授权

US07193325B2 Reliability improvement of SiOC etch with trimethylsilane gas passivation in Cu damascene interconnects 有权
标题翻译：在Cu大马士革互连中三甲基硅烷气体钝化的SiOC蚀刻的可靠性提高
公开(公告)号：US07193325B2
公开(公告)日：2007-03-20
申请号：US10835788
申请日：2004-04-30
申请人： Zhen-Cheng Wu , Bi-Troug Chen , Weng Chang , Syun-Ming Jang , Su-Horng Lin
发明人： Zhen-Cheng Wu , Bi-Troug Chen , Weng Chang , Syun-Ming Jang , Su-Horng Lin
IPC分类号： H01L23/48
CPC分类号： H01L21/31633 , H01L21/02046 , H01L21/02126 , H01L21/02211 , H01L21/02274 , H01L21/02304 , H01L21/02315 , H01L21/3144 , H01L21/3145 , H01L21/3148 , H01L21/76807 , H01L21/76829 , H01L21/76832
摘要： A method of forming a SiCOH etch stop layer in a copper damascene process is described. A substrate with an exposed metal layer is treated with H2 or NH3 plasma to remove metal oxides. Trimethylsilane is flowed into a chamber with no RF power at about 350° C. to form at least a monolayer on the exposed metal layer. The SiCOH layer is formed by a PECVD process including trimethylsilane and CO2 source gases. Optionally, a composite SiCOH layer comprised of a low compressive stress layer on a high compressive stress layer is formed on the substrate. A conventional damascene sequence is then used to form a second metal layer on the exposed metal layer. Via Rc stability is improved and a lower leakage current is achieved with the trimethylsilane passivation layer. A composite SiCOH etch stop layer provides improved stress migration resistance compared to a single low stress SiCOH layer.
摘要翻译：描述了在铜镶嵌工艺中形成SiCOH蚀刻停止层的方法。具有暴露的金属层的衬底用H 2 N 3或NH 3 3等离子体处理以除去金属氧化物。三甲基硅烷在约350℃下流入没有RF功率的室，以在暴露的金属层上形成至少单层。 SiCOH层通过包括三甲基硅烷和CO 2原子气体的PECVD工艺形成。任选地，在基底上形成由高压缩应力层上的低压应力层构成的复合SiCOH层。然后使用常规的镶嵌序列在暴露的金属层上形成第二金属层。通过Rc稳定性提高，并且用三甲基硅烷钝化层实现较低的漏电流。与单个低应力SiCOH层相比，复合SiCOH蚀刻停止层提供改进的应力迁移阻力。

10. 发明申请

US20080246057A1 Silicon layer for stopping dislocation propagation 有权
标题翻译：用于阻止位错传播的硅层
公开(公告)号：US20080246057A1
公开(公告)日：2008-10-09
申请号：US11732889
申请日：2007-04-05
申请人： Hsien-Hsin Lin , Weng Chang , Chien-Chang Su , Kuan-Yu Chen , Hsueh-Chang Sung , Ming-Hua Yu
发明人： Hsien-Hsin Lin , Weng Chang , Chien-Chang Su , Kuan-Yu Chen , Hsueh-Chang Sung , Ming-Hua Yu
IPC分类号： H01L29/78
CPC分类号： H01L29/66477 , H01L21/02532 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A composite semiconductor structure and method of forming the same are provided. The composite semiconductor structure includes a first silicon-containing compound layer comprising an element selected from the group consisting essentially of germanium and carbon; a silicon layer on the first silicon-containing compound layer, wherein the silicon layer comprises substantially pure silicon; and a second silicon-containing compound layer comprising the element on the silicon layer. The first and the second silicon-containing compound layers have substantially lower silicon concentrations than the silicon layer. The composite semiconductor structure may be formed as source/drain regions of metal-oxide-semiconductor (MOS) devices.
摘要翻译：提供一种复合半导体结构及其形成方法。复合半导体结构包括第一含硅化合物层，其包含选自基本上由锗和碳组成的组的元素; 所述第一含硅化合物层上的硅层，其中所述硅层包含基本上纯的硅; 以及在所述硅层上包含所述元素的第二含硅化合物层。第一和第二含硅化合物层具有比硅层低的硅浓度。复合半导体结构可以形成为金属氧化物半导体（MOS）器件的源极/漏极区域。

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