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1. 发明申请

US20060157776A1 System and method for contact module processing 审中-公开
标题翻译：接触模块处理系统和方法
公开(公告)号：US20060157776A1
公开(公告)日：2006-07-20
申请号：US11039159
申请日：2005-01-20
申请人： Cheng-Hung Chang , Hsiao-Tzu Lu , Chu-Yun Fu , Weng Chang , Shwang-Ming Jeng
发明人： Cheng-Hung Chang , Hsiao-Tzu Lu , Chu-Yun Fu , Weng Chang , Shwang-Ming Jeng
IPC分类号： H01L29/792
CPC分类号： H01L23/3192 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： System and method for improving the process performance of a contact module. A preferred embodiment comprises improving the process performance of a contact module by reducing surface variations of an interlayer dielectric. The interlayer dielectric comprises a plurality of layers, a first layer (for example, a contact etch stop layer 610) protects devices on a substrate from subsequent etching operations, while a second layer (for example, a first dielectric layer 620) covers the first layer. A third layer (for example, a second dielectric layer 630) fills gaps that may be due to the topography of the devices. A fourth layer (for example, a third dielectric layer 640), brings the interlayer dielectric layer to a desired thickness and is formed using a process that yields a very flat surface completes the interlayer dielectric. Using multiple layers permit the elimination of variations (filling gaps and leveling bumps) without resorting to chemical-mechanical polishing.
摘要翻译：提高接触模块工艺性能的系统和方法。优选实施例包括通过减少层间电介质的表面变化来提高接触模块的工艺性能。层间电介质包括多层，第一层（例如，接触蚀刻停止层610）保护衬底上的器件免受后续蚀刻操作，而第二层（例如，第一介电层620）覆盖第一层层。第三层（例如，第二介电层630）填充可能是由于器件的形貌造成的间隙。第四层（例如，第三介电层640）使得层间电介质层达到期望的厚度并且使用产生非常平坦的表面的工艺形成来完成层间电介质。使用多层可以消除变化（填充间隙和调平凸起），而无需采用化学机械抛光。

2. 发明授权

US07119404B2 High performance strained channel MOSFETs by coupled stress effects 有权
标题翻译：高性能应变通道MOSFET通过耦合应力效应
公开(公告)号：US07119404B2
公开(公告)日：2006-10-10
申请号：US10849689
申请日：2004-05-19
申请人： Cheng-Hung Chang , Weng Chang , Chu-Yun Fu
发明人： Cheng-Hung Chang , Weng Chang , Chu-Yun Fu
IPC分类号： H01L31/62 , H01L21/8238
CPC分类号： H01L29/7845 , H01L21/823807 , H01L21/823828 , H01L21/823878 , H01L29/7842 , H01L29/7843 , H01L29/7846
摘要： Strained channel transistors including a PMOS and NMOS device pair to improve an NMOS device performance without substantially degrading PMOS device performance and method for forming the same, the method including providing a semiconductor substrate; forming strained shallow trench isolation regions in the semiconductor substrate; forming PMOS and NMOS devices on the semiconductor substrate including doped source and drain regions; forming a tensile strained contact etching stop layer (CESL) over the PMOS and NMOS devices; and, forming a tensile strained dielectric insulating layer over the CESL layer.
摘要翻译：包括PMOS和NMOS器件对的应变沟道晶体管，以改善NMOS器件性能而不会使PMOS器件性能基本上降低，并且用于形成PMOS器件性能的方法，所述方法包括提供半导体衬底; 在半导体衬底中形成应变浅沟槽隔离区; 在包括掺杂源极和漏极区域的半导体衬底上形成PMOS和NMOS器件; 在PMOS和NMOS器件上形成拉伸应变接触蚀刻停止层（CESL）; 并在CESL层上形成拉伸应变电介质绝缘层。

3. 发明申请

US20050260806A1 High performance strained channel mosfets by coupled stress effects 有权
标题翻译：高性能应变通道MOSFET通过耦合应力作用
公开(公告)号：US20050260806A1
公开(公告)日：2005-11-24
申请号：US10849689
申请日：2004-05-19
申请人： Cheng-Hung Chang , Weng Chang , Chu-Yun Fu
发明人： Cheng-Hung Chang , Weng Chang , Chu-Yun Fu
IPC分类号： H01L21/8238
CPC分类号： H01L29/7845 , H01L21/823807 , H01L21/823828 , H01L21/823878 , H01L29/7842 , H01L29/7843 , H01L29/7846
摘要： Strained channel transistors including a PMOS and NMOS device pair to improve an NMOS device performance without substantially degrading PMOS device performance and method for forming the same, the method including providing a semiconductor substrate; forming strained shallow trench isolation regions in the semiconductor substrate; forming PMOS and NMOS devices on the semiconductor substrate including doped source and drain regions; forming a tensile strained contact etching stop layer (CESL) over the PMOS and NMOS devices; and, forming a tensile strained dielectric insulating layer over the CESL layer.
摘要翻译：包括PMOS和NMOS器件对的应变沟道晶体管，以改善NMOS器件性能而不会使PMOS器件性能基本上降低，并且用于形成PMOS器件性能的方法，所述方法包括提供半导体衬底; 在半导体衬底中形成应变浅沟槽隔离区; 在包括掺杂源极和漏极区域的半导体衬底上形成PMOS和NMOS器件; 在PMOS和NMOS器件上形成拉伸应变接触蚀刻停止层（CESL）; 并在CESL层上形成拉伸应变电介质绝缘层。

4. 发明申请

US20060049036A1 Method and apparatus for real-time control and monitor of deposition processes 审中-公开
标题翻译：用于实时控制和监测沉积过程的方法和装置
公开(公告)号：US20060049036A1
公开(公告)日：2006-03-09
申请号：US10936905
申请日：2004-09-09
申请人： Cheng-Hung Chang , Jhi-Cherng Lu , Joung-Wei Liou , Chu-Yun Fu , Weng Chang , Syung-Ming Jang
发明人： Cheng-Hung Chang , Jhi-Cherng Lu , Joung-Wei Liou , Chu-Yun Fu , Weng Chang , Syung-Ming Jang
IPC分类号： C23C14/00
CPC分类号： C23C14/34 , C23C14/54
摘要： A method comprises measuring an RF voltage and ion current at a wafer during a plasma-enhanced deposition process, determining a sputter rate in response to the RF voltage and ion current measurements, detecting an abnormal condition in response to one of the RF voltage and ion current measurements, and sputter rate, and taking a corrective action in response to detecting an abnormal condition.
摘要翻译：一种方法包括在等离子体增强沉积过程期间测量晶片处的RF电压和离子电流，响应于RF电压和离子电流测量确定溅射速率，响应于RF电压和离子之一检测异常状况电流测量和溅射速率，并且响应于检测到异常状况采取校正动作。

5. 发明申请

US20090035909A1 METHOD OF FABRICATION OF A FINFET ELEMENT 有权
标题翻译： FINFET元件的制造方法
公开(公告)号：US20090035909A1
公开(公告)日：2009-02-05
申请号：US11831098
申请日：2007-07-31
申请人： Cheng-Hung Chang , Chen-Hua Yu , Chen-Nan Yeh , Chu-Yun Fu , Yu-Rung Hsu , Ding-Yuan Chen
发明人： Cheng-Hung Chang , Chen-Hua Yu , Chen-Nan Yeh , Chu-Yun Fu , Yu-Rung Hsu , Ding-Yuan Chen
IPC分类号： H01L21/8238
CPC分类号： H01L21/823828 , H01L21/823807 , H01L21/823821 , H01L21/823857 , H01L29/66795 , H01L29/785
摘要： The present disclosure provides a method of fabricating a FinFET element including providing a substrate including a first fin and a second fin. A first layer is formed on the first fin. The first layer comprises a dopant of a first type. A dopant of a second type is provided to the second fin. High temperature processing of the substrate is performed on the substrate including the formed first layer and the dopant of the second type.
摘要翻译：本公开提供了一种制造FinFET元件的方法，包括提供包括第一鳍片和第二鳍片的衬底。在第一散热片上形成第一层。第一层包括第一类型的掺杂剂。第二类型的掺杂剂被提供到第二鳍。在包括所形成的第一层和第二类型的掺杂剂的衬底上进行衬底的高温处理。

6. 发明申请

US20060024879A1 Selectively strained MOSFETs to improve drive current 审中-公开
标题翻译：选择性应变MOSFET来提高驱动电流
公开(公告)号：US20060024879A1
公开(公告)日：2006-02-02
申请号：US10902973
申请日：2004-07-31
申请人： Chu-Yun Fu , Cheng-Hung Chang
发明人： Chu-Yun Fu , Cheng-Hung Chang
IPC分类号： H01L21/8238 , H01L21/31
CPC分类号： H01L21/0214 , H01L21/0217 , H01L21/02274 , H01L21/3185 , H01L21/823807 , H01L29/7842 , H01L29/7843
摘要： A MOSFET device pair with improved drive current and a method for producing the same to selectively introduce strain into a respective N-type and P-type MOSFET device channel region, the method including forming a compressive stressed nitride layer on over the P-type MOSFET device and a tensile stressed nitride layer on the N-type MOSFET device followed by forming a PMD layer having a less compressive or tensile stress.
摘要翻译：一种具有改进的驱动电流的MOSFET器件对及其制造方法，用于选择性地将应变引入相应的N型和P型MOSFET器件沟道区，该方法包括在P型MOSFET上形成压应力氮化物层器件和N型MOSFET器件上的拉伸应力氮化物层，随后形成具有较小压缩或拉伸应力的PMD层。

7. 发明授权

US08883597B2 Method of fabrication of a FinFET element 有权
标题翻译： FinFET元件的制造方法
公开(公告)号：US08883597B2
公开(公告)日：2014-11-11
申请号：US11831098
申请日：2007-07-31
申请人： Cheng-Hung Chang , Chen-Hua Yu , Chen-Nan Yeh , Chu-Yun Fu , Yu-Rang Hsu , Ding-Yuan Chen
发明人： Cheng-Hung Chang , Chen-Hua Yu , Chen-Nan Yeh , Chu-Yun Fu , Yu-Rang Hsu , Ding-Yuan Chen
IPC分类号： H01L21/8236 , H01L21/8238 , H01L29/78 , H01L29/66
CPC分类号： H01L21/823828 , H01L21/823807 , H01L21/823821 , H01L21/823857 , H01L29/66795 , H01L29/785
摘要： The present disclosure provides a method of fabricating a FinFET element including providing a substrate including a first fin and a second fin. A first layer is formed on the first fin. The first layer comprises a dopant of a first type. A dopant of a second type is provided to the second fin. High temperature processing of the substrate is performed on the substrate including the formed first layer and the dopant of the second type.
摘要翻译：本公开提供了一种制造FinFET元件的方法，包括提供包括第一鳍片和第二鳍片的衬底。在第一散热片上形成第一层。第一层包括第一类型的掺杂剂。第二类型的掺杂剂被提供到第二鳍。在包括所形成的第一层和第二类型的掺杂剂的衬底上进行衬底的高温处理。

8. 发明授权

US11038056B2 System and method for source/drain contact processing 有权
公开(公告)号：US11038056B2
公开(公告)日：2021-06-15
申请号：US13371169
申请日：2012-02-10
申请人： Chen-Hua Yu , Cheng-Hung Chang , Chen-Nan Yeh , Yu-Rung Hsu
发明人： Chen-Hua Yu , Cheng-Hung Chang , Chen-Nan Yeh , Yu-Rung Hsu
IPC分类号： H01L29/76 , H01L29/78 , H01L29/417 , H01L29/66 , H01L29/20
摘要： System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin.

9. 发明授权

US08644904B2 Dry electrode 有权
标题翻译：干电极
公开(公告)号：US08644904B2
公开(公告)日：2014-02-04
申请号：US12488987
申请日：2009-06-22
申请人： Cheng-Hung Chang , Yi-Shiang Ouyang , Wen-Ying Chang
发明人： Cheng-Hung Chang , Yi-Shiang Ouyang , Wen-Ying Chang
IPC分类号： A61B5/04 , A61N1/00
CPC分类号： C25D5/56 , A61B5/0408
摘要： A flexible dry electrode and the manufacturing method thereof are provided. The electrode has an electroplated uneven surface and at least one hole and is made of porous material.
摘要翻译：提供柔性干电极及其制造方法。电极具有电镀不平坦表面和至少一个孔，并由多孔材料制成。

10. 发明申请

US20120025313A1 Germanium FinFETs Having Dielectric Punch-Through Stoppers 有权
标题翻译：具有介质穿孔塞的锗FinFET
公开(公告)号：US20120025313A1
公开(公告)日：2012-02-02
申请号：US13272994
申请日：2011-10-13
申请人： Cheng-Hung Chang , Yu-Rung Hsu , Chen-Yi Lee , Shih-Ting Hung , Chen-Nan Yeh , Chen-Hua Yu
发明人： Cheng-Hung Chang , Yu-Rung Hsu , Chen-Yi Lee , Shih-Ting Hung , Chen-Nan Yeh , Chen-Hua Yu
IPC分类号： H01L27/12 , H01L29/02
CPC分类号： H01L29/66795 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02617 , H01L29/1054 , H01L29/7851
摘要： A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fin. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.
摘要翻译：形成半导体结构的方法包括提供复合衬底，该复合衬底包括在本体硅衬底上并邻接体硅衬底的体硅衬底和硅锗（SiGe）层。对SiGe层进行第一次冷凝以形成冷凝的SiGe层，使得冷凝的SiGe层具有基本均匀的锗浓度。蚀刻冷凝的SiGe层和体硅衬底的顶部以在硅片上形成包括硅翅片和冷凝的SiGe鳍的复合翅片。该方法还包括氧化硅片的一部分; 并对冷凝的SiGe翅片进行第二冷凝。

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