会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 38. 发明申请
    • Method of generating an efficient stuck-at fault and transition delay fault truncated scan test pattern for an integrated circuit design
    • 产生集成电路设计的有效卡住故障和转换延迟故障截断扫描测试图案的方法
    • US20050125755A1
    • 2005-06-09
    • US10728036
    • 2003-12-03
    • Cam LuRobert BenwareThai Nguyen
    • Cam LuRobert BenwareThai Nguyen
    • G01R31/3183G06F11/00G06F17/50
    • G01R31/318328
    • A method of generating a truncated scan test pattern for an integrated circuit design includes steps of: (a) receiving as input an integrated circuit design; (b) estimating a number of transition delay fault test patterns and a corresponding number of top-off stuck-at fault patterns to achieve maximum stuck-at fault and transition delay fault coverage; (c) truncating the estimated number of transition delay fault patterns to generate a truncated set of transition delay fault patterns so that the truncated set of transition delay fault patterns and the corresponding number of top-off stuck-at fault patterns achieve maximum stuck-at fault and transition delay fault coverage within a selected scan memory limit; and (d) generating as output the truncated set of transition delay fault patterns and the corresponding number of top-off stuck-at fault patterns.
    • 生成用于集成电路设计的截头扫描测试图案的方法包括以下步骤:(a)接收作为输入的集成电路设计; (b)估计过渡延迟故障测试模式的数量和相应数量的顶点卡住故障模式,以实现最大卡住故障和转换延迟故障覆盖; (c)截断估计的转移延迟故障模式数,以产生截断的一组过渡延迟故障模式,使得截断的过渡延迟故障模式集合和相应数量的最大持续故障模式实现最大卡住 所选扫描存储限制内的故障和转换延迟故障覆盖; 和(d)产生截断的过渡延迟故障模式集合的输出以及相应数量的顶部卡住故障模式。
    • 39. 发明授权
    • Phase-locked loop with self-selecting multi-band VCO
    • 具有自选多频带VCO的锁相环
    • US06806786B1
    • 2004-10-19
    • US10143529
    • 2002-05-09
    • Christopher LamThai NguyenChet Sooraparth
    • Christopher LamThai NguyenChet Sooraparth
    • H03B100
    • H03L7/10
    • Techniques to select the proper frequency band for use in a PLL from among multiple frequency bands of a multi-band VCO. The PLL comprises a detector, a loop filter, the multi-band VCO, and a control unit. The detector receives a first signal to be locked to and a second signal that is related to a VCO signal and provides a detector output. The loop filter filters the detector output to provide a control signal. The multi-band VCO selects one of the multiple frequency bands based on a select signal and provides the VCO signal at a frequency determined by the control signal. The control unit derives the select signal for the multi-band VCO based on information extracted from a third signal (e.g., a filtered version of the control signal) and a timing signal from a timer unit.
    • 从多频带VCO的多个频带中选择用于PLL的适当频带的技术。 PLL包括检测器,环路滤波器,多频带VCO和控制单元。 检测器接收要锁定的第一信号和与VCO信号相关的第二信号并提供检测器输出。 环路滤波器对检测器输出进行滤波以提供控制信号。 多频带VCO基于选择信号选择多个频带中的一个,并以由控制信号确定的频率提供VCO信号。 控制单元基于从第三信号(例如,控制信号的滤波版本)提取的信息和来自定时器单元的定时信号,导出多频带VCO的选择信号。